1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 #include "cpu_bits.h" 29 30 #define TCG_GUEST_DEFAULT_MO 0 31 32 #define TYPE_RISCV_CPU "riscv-cpu" 33 34 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 35 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 36 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 37 38 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 39 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 40 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 41 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 42 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 43 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 44 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 45 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 46 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 47 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 48 49 #if defined(TARGET_RISCV32) 50 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 51 #elif defined(TARGET_RISCV64) 52 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 53 #endif 54 55 #define RV(x) ((target_ulong)1 << (x - 'A')) 56 57 #define RVI RV('I') 58 #define RVE RV('E') /* E and I are mutually exclusive */ 59 #define RVM RV('M') 60 #define RVA RV('A') 61 #define RVF RV('F') 62 #define RVD RV('D') 63 #define RVV RV('V') 64 #define RVC RV('C') 65 #define RVS RV('S') 66 #define RVU RV('U') 67 #define RVH RV('H') 68 #define RVJ RV('J') 69 70 /* S extension denotes that Supervisor mode exists, however it is possible 71 to have a core that support S mode but does not have an MMU and there 72 is currently no bit in misa to indicate whether an MMU exists or not 73 so a cpu features bitfield is required, likewise for optional PMP support */ 74 enum { 75 RISCV_FEATURE_MMU, 76 RISCV_FEATURE_PMP, 77 RISCV_FEATURE_EPMP, 78 RISCV_FEATURE_MISA 79 }; 80 81 #define PRIV_VERSION_1_10_0 0x00011000 82 #define PRIV_VERSION_1_11_0 0x00011100 83 84 #define VEXT_VERSION_1_00_0 0x00010000 85 86 enum { 87 TRANSLATE_SUCCESS, 88 TRANSLATE_FAIL, 89 TRANSLATE_PMP_FAIL, 90 TRANSLATE_G_STAGE_FAIL 91 }; 92 93 #define MMU_USER_IDX 3 94 95 #define MAX_RISCV_PMPS (16) 96 97 typedef struct CPURISCVState CPURISCVState; 98 99 #if !defined(CONFIG_USER_ONLY) 100 #include "pmp.h" 101 #endif 102 103 #define RV_VLEN_MAX 1024 104 105 FIELD(VTYPE, VLMUL, 0, 3) 106 FIELD(VTYPE, VSEW, 3, 3) 107 FIELD(VTYPE, VTA, 6, 1) 108 FIELD(VTYPE, VMA, 7, 1) 109 FIELD(VTYPE, VEDIV, 8, 2) 110 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 111 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 112 113 struct CPURISCVState { 114 target_ulong gpr[32]; 115 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 116 uint64_t fpr[32]; /* assume both F and D extensions */ 117 118 /* vector coprocessor state. */ 119 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 120 target_ulong vxrm; 121 target_ulong vxsat; 122 target_ulong vl; 123 target_ulong vstart; 124 target_ulong vtype; 125 126 target_ulong pc; 127 target_ulong load_res; 128 target_ulong load_val; 129 130 target_ulong frm; 131 132 target_ulong badaddr; 133 target_ulong guest_phys_fault_addr; 134 135 target_ulong priv_ver; 136 target_ulong bext_ver; 137 target_ulong vext_ver; 138 139 /* RISCVMXL, but uint32_t for vmstate migration */ 140 uint32_t misa_mxl; /* current mxl */ 141 uint32_t misa_mxl_max; /* max mxl for this cpu */ 142 uint32_t misa_ext; /* current extensions */ 143 uint32_t misa_ext_mask; /* max ext for this cpu */ 144 145 uint32_t features; 146 147 #ifdef CONFIG_USER_ONLY 148 uint32_t elf_flags; 149 #endif 150 151 #ifndef CONFIG_USER_ONLY 152 target_ulong priv; 153 /* This contains QEMU specific information about the virt state. */ 154 target_ulong virt; 155 target_ulong resetvec; 156 157 target_ulong mhartid; 158 /* 159 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 160 * For RV64 this is a 64-bit mstatus. 161 */ 162 uint64_t mstatus; 163 164 target_ulong mip; 165 166 uint32_t miclaim; 167 168 target_ulong mie; 169 target_ulong mideleg; 170 171 target_ulong satp; /* since: priv-1.10.0 */ 172 target_ulong stval; 173 target_ulong medeleg; 174 175 target_ulong stvec; 176 target_ulong sepc; 177 target_ulong scause; 178 179 target_ulong mtvec; 180 target_ulong mepc; 181 target_ulong mcause; 182 target_ulong mtval; /* since: priv-1.10.0 */ 183 184 /* Hypervisor CSRs */ 185 target_ulong hstatus; 186 target_ulong hedeleg; 187 target_ulong hideleg; 188 target_ulong hcounteren; 189 target_ulong htval; 190 target_ulong htinst; 191 target_ulong hgatp; 192 uint64_t htimedelta; 193 194 /* Virtual CSRs */ 195 /* 196 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 197 * For RV64 this is a 64-bit vsstatus. 198 */ 199 uint64_t vsstatus; 200 target_ulong vstvec; 201 target_ulong vsscratch; 202 target_ulong vsepc; 203 target_ulong vscause; 204 target_ulong vstval; 205 target_ulong vsatp; 206 207 target_ulong mtval2; 208 target_ulong mtinst; 209 210 /* HS Backup CSRs */ 211 target_ulong stvec_hs; 212 target_ulong sscratch_hs; 213 target_ulong sepc_hs; 214 target_ulong scause_hs; 215 target_ulong stval_hs; 216 target_ulong satp_hs; 217 uint64_t mstatus_hs; 218 219 /* Signals whether the current exception occurred with two-stage address 220 translation active. */ 221 bool two_stage_lookup; 222 223 target_ulong scounteren; 224 target_ulong mcounteren; 225 226 target_ulong sscratch; 227 target_ulong mscratch; 228 229 /* temporary htif regs */ 230 uint64_t mfromhost; 231 uint64_t mtohost; 232 uint64_t timecmp; 233 234 /* physical memory protection */ 235 pmp_table_t pmp_state; 236 target_ulong mseccfg; 237 238 /* machine specific rdtime callback */ 239 uint64_t (*rdtime_fn)(uint32_t); 240 uint32_t rdtime_fn_arg; 241 242 /* True if in debugger mode. */ 243 bool debugger; 244 245 /* 246 * CSRs for PointerMasking extension 247 */ 248 target_ulong mmte; 249 target_ulong mpmmask; 250 target_ulong mpmbase; 251 target_ulong spmmask; 252 target_ulong spmbase; 253 target_ulong upmmask; 254 target_ulong upmbase; 255 #endif 256 257 float_status fp_status; 258 259 /* Fields from here on are preserved across CPU reset. */ 260 QEMUTimer *timer; /* Internal timer */ 261 }; 262 263 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 264 RISCV_CPU) 265 266 /** 267 * RISCVCPUClass: 268 * @parent_realize: The parent class' realize handler. 269 * @parent_reset: The parent class' reset handler. 270 * 271 * A RISCV CPU model. 272 */ 273 struct RISCVCPUClass { 274 /*< private >*/ 275 CPUClass parent_class; 276 /*< public >*/ 277 DeviceRealize parent_realize; 278 DeviceReset parent_reset; 279 }; 280 281 /** 282 * RISCVCPU: 283 * @env: #CPURISCVState 284 * 285 * A RISCV CPU. 286 */ 287 struct RISCVCPU { 288 /*< private >*/ 289 CPUState parent_obj; 290 /*< public >*/ 291 CPUNegativeOffsetState neg; 292 CPURISCVState env; 293 294 char *dyn_csr_xml; 295 char *dyn_vreg_xml; 296 297 /* Configuration Settings */ 298 struct { 299 bool ext_i; 300 bool ext_e; 301 bool ext_g; 302 bool ext_m; 303 bool ext_a; 304 bool ext_f; 305 bool ext_d; 306 bool ext_c; 307 bool ext_s; 308 bool ext_u; 309 bool ext_h; 310 bool ext_j; 311 bool ext_v; 312 bool ext_zba; 313 bool ext_zbb; 314 bool ext_zbc; 315 bool ext_zbs; 316 bool ext_counters; 317 bool ext_ifencei; 318 bool ext_icsr; 319 bool ext_zfh; 320 bool ext_zfhmin; 321 322 char *priv_spec; 323 char *user_spec; 324 char *bext_spec; 325 char *vext_spec; 326 uint16_t vlen; 327 uint16_t elen; 328 bool mmu; 329 bool pmp; 330 bool epmp; 331 uint64_t resetvec; 332 } cfg; 333 }; 334 335 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 336 { 337 return (env->misa_ext & ext) != 0; 338 } 339 340 static inline bool riscv_feature(CPURISCVState *env, int feature) 341 { 342 return env->features & (1ULL << feature); 343 } 344 345 #include "cpu_user.h" 346 347 extern const char * const riscv_int_regnames[]; 348 extern const char * const riscv_int_regnamesh[]; 349 extern const char * const riscv_fpr_regnames[]; 350 351 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 352 void riscv_cpu_do_interrupt(CPUState *cpu); 353 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 354 int cpuid, void *opaque); 355 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 356 int cpuid, void *opaque); 357 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 358 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 359 bool riscv_cpu_fp_enabled(CPURISCVState *env); 360 bool riscv_cpu_vector_enabled(CPURISCVState *env); 361 bool riscv_cpu_virt_enabled(CPURISCVState *env); 362 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 363 bool riscv_cpu_two_stage_lookup(int mmu_idx); 364 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 365 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 366 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 367 MMUAccessType access_type, int mmu_idx, 368 uintptr_t retaddr) QEMU_NORETURN; 369 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 370 MMUAccessType access_type, int mmu_idx, 371 bool probe, uintptr_t retaddr); 372 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 373 vaddr addr, unsigned size, 374 MMUAccessType access_type, 375 int mmu_idx, MemTxAttrs attrs, 376 MemTxResult response, uintptr_t retaddr); 377 char *riscv_isa_string(RISCVCPU *cpu); 378 void riscv_cpu_list(void); 379 380 #define cpu_list riscv_cpu_list 381 #define cpu_mmu_index riscv_cpu_mmu_index 382 383 #ifndef CONFIG_USER_ONLY 384 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 385 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 386 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 387 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 388 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 389 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 390 uint32_t arg); 391 #endif 392 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 393 394 void riscv_translate_init(void); 395 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 396 uint32_t exception, uintptr_t pc); 397 398 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 399 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 400 401 #define TB_FLAGS_PRIV_MMU_MASK 3 402 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 403 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 404 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 405 406 typedef CPURISCVState CPUArchState; 407 typedef RISCVCPU ArchCPU; 408 #include "exec/cpu-all.h" 409 410 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 411 FIELD(TB_FLAGS, LMUL, 3, 3) 412 FIELD(TB_FLAGS, SEW, 6, 3) 413 /* Skip MSTATUS_VS (0x600) bits */ 414 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 415 FIELD(TB_FLAGS, VILL, 12, 1) 416 /* Skip MSTATUS_FS (0x6000) bits */ 417 /* Is a Hypervisor instruction load/store allowed? */ 418 FIELD(TB_FLAGS, HLSX, 15, 1) 419 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 420 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 421 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 422 FIELD(TB_FLAGS, XL, 20, 2) 423 /* If PointerMasking should be applied */ 424 FIELD(TB_FLAGS, PM_ENABLED, 22, 1) 425 426 #ifdef TARGET_RISCV32 427 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 428 #else 429 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 430 { 431 return env->misa_mxl; 432 } 433 #endif 434 435 /* 436 * Encode LMUL to lmul as follows: 437 * LMUL vlmul lmul 438 * 1 000 0 439 * 2 001 1 440 * 4 010 2 441 * 8 011 3 442 * - 100 - 443 * 1/8 101 -3 444 * 1/4 110 -2 445 * 1/2 111 -1 446 * 447 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 448 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 449 * => VLMAX = vlen >> (1 + 3 - (-3)) 450 * = 256 >> 7 451 * = 2 452 */ 453 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 454 { 455 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 456 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 457 return cpu->cfg.vlen >> (sew + 3 - lmul); 458 } 459 460 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 461 target_ulong *cs_base, uint32_t *pflags); 462 463 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 464 target_ulong *ret_value, 465 target_ulong new_value, target_ulong write_mask); 466 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 467 target_ulong *ret_value, 468 target_ulong new_value, 469 target_ulong write_mask); 470 471 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 472 target_ulong val) 473 { 474 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 475 } 476 477 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 478 { 479 target_ulong val = 0; 480 riscv_csrrw(env, csrno, &val, 0, 0); 481 return val; 482 } 483 484 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 485 int csrno); 486 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 487 target_ulong *ret_value); 488 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 489 target_ulong new_value); 490 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 491 target_ulong *ret_value, 492 target_ulong new_value, 493 target_ulong write_mask); 494 495 typedef struct { 496 const char *name; 497 riscv_csr_predicate_fn predicate; 498 riscv_csr_read_fn read; 499 riscv_csr_write_fn write; 500 riscv_csr_op_fn op; 501 } riscv_csr_operations; 502 503 /* CSR function table constants */ 504 enum { 505 CSR_TABLE_SIZE = 0x1000 506 }; 507 508 /* CSR function table */ 509 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 510 511 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 512 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 513 514 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 515 516 #endif /* RISCV_CPU_H */ 517