1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 /* 34 * RISC-V-specific extra insn start words: 35 * 1: Original instruction opcode 36 */ 37 #define TARGET_INSN_START_EXTRA_WORDS 1 38 39 #define TYPE_RISCV_CPU "riscv-cpu" 40 41 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 42 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 43 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 44 45 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 46 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 47 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 48 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 49 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 50 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 51 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 52 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 53 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 54 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 55 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 56 #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") 57 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 58 59 #if defined(TARGET_RISCV32) 60 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 61 #elif defined(TARGET_RISCV64) 62 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 63 #endif 64 65 #define RV(x) ((target_ulong)1 << (x - 'A')) 66 67 /* 68 * Consider updating register_cpu_props() when adding 69 * new MISA bits here. 70 */ 71 #define RVI RV('I') 72 #define RVE RV('E') /* E and I are mutually exclusive */ 73 #define RVM RV('M') 74 #define RVA RV('A') 75 #define RVF RV('F') 76 #define RVD RV('D') 77 #define RVV RV('V') 78 #define RVC RV('C') 79 #define RVS RV('S') 80 #define RVU RV('U') 81 #define RVH RV('H') 82 #define RVJ RV('J') 83 84 /* S extension denotes that Supervisor mode exists, however it is possible 85 to have a core that support S mode but does not have an MMU and there 86 is currently no bit in misa to indicate whether an MMU exists or not 87 so a cpu features bitfield is required, likewise for optional PMP support */ 88 enum { 89 RISCV_FEATURE_MMU, 90 RISCV_FEATURE_PMP, 91 RISCV_FEATURE_EPMP, 92 RISCV_FEATURE_MISA, 93 RISCV_FEATURE_DEBUG 94 }; 95 96 /* Privileged specification version */ 97 enum { 98 PRIV_VERSION_1_10_0 = 0, 99 PRIV_VERSION_1_11_0, 100 PRIV_VERSION_1_12_0, 101 }; 102 103 #define VEXT_VERSION_1_00_0 0x00010000 104 105 enum { 106 TRANSLATE_SUCCESS, 107 TRANSLATE_FAIL, 108 TRANSLATE_PMP_FAIL, 109 TRANSLATE_G_STAGE_FAIL 110 }; 111 112 #define MMU_USER_IDX 3 113 114 #define MAX_RISCV_PMPS (16) 115 116 typedef struct CPUArchState CPURISCVState; 117 118 #if !defined(CONFIG_USER_ONLY) 119 #include "pmp.h" 120 #include "debug.h" 121 #endif 122 123 #define RV_VLEN_MAX 1024 124 #define RV_MAX_MHPMEVENTS 32 125 #define RV_MAX_MHPMCOUNTERS 32 126 127 FIELD(VTYPE, VLMUL, 0, 3) 128 FIELD(VTYPE, VSEW, 3, 3) 129 FIELD(VTYPE, VTA, 6, 1) 130 FIELD(VTYPE, VMA, 7, 1) 131 FIELD(VTYPE, VEDIV, 8, 2) 132 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 133 134 typedef struct PMUCTRState { 135 /* Current value of a counter */ 136 target_ulong mhpmcounter_val; 137 /* Current value of a counter in RV32*/ 138 target_ulong mhpmcounterh_val; 139 /* Snapshot values of counter */ 140 target_ulong mhpmcounter_prev; 141 /* Snapshort value of a counter in RV32 */ 142 target_ulong mhpmcounterh_prev; 143 bool started; 144 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 145 target_ulong irq_overflow_left; 146 } PMUCTRState; 147 148 struct CPUArchState { 149 target_ulong gpr[32]; 150 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 151 152 /* vector coprocessor state. */ 153 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 154 target_ulong vxrm; 155 target_ulong vxsat; 156 target_ulong vl; 157 target_ulong vstart; 158 target_ulong vtype; 159 bool vill; 160 161 target_ulong pc; 162 target_ulong load_res; 163 target_ulong load_val; 164 165 /* Floating-Point state */ 166 uint64_t fpr[32]; /* assume both F and D extensions */ 167 target_ulong frm; 168 float_status fp_status; 169 170 target_ulong badaddr; 171 target_ulong bins; 172 173 target_ulong guest_phys_fault_addr; 174 175 target_ulong priv_ver; 176 target_ulong bext_ver; 177 target_ulong vext_ver; 178 179 /* RISCVMXL, but uint32_t for vmstate migration */ 180 uint32_t misa_mxl; /* current mxl */ 181 uint32_t misa_mxl_max; /* max mxl for this cpu */ 182 uint32_t misa_ext; /* current extensions */ 183 uint32_t misa_ext_mask; /* max ext for this cpu */ 184 uint32_t xl; /* current xlen */ 185 186 /* 128-bit helpers upper part return value */ 187 target_ulong retxh; 188 189 uint32_t features; 190 191 #ifdef CONFIG_USER_ONLY 192 uint32_t elf_flags; 193 #endif 194 195 #ifndef CONFIG_USER_ONLY 196 target_ulong priv; 197 /* This contains QEMU specific information about the virt state. */ 198 target_ulong virt; 199 target_ulong geilen; 200 uint64_t resetvec; 201 202 target_ulong mhartid; 203 /* 204 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 205 * For RV64 this is a 64-bit mstatus. 206 */ 207 uint64_t mstatus; 208 209 uint64_t mip; 210 /* 211 * MIP contains the software writable version of SEIP ORed with the 212 * external interrupt value. The MIP register is always up-to-date. 213 * To keep track of the current source, we also save booleans of the values 214 * here. 215 */ 216 bool external_seip; 217 bool software_seip; 218 219 uint64_t miclaim; 220 221 uint64_t mie; 222 uint64_t mideleg; 223 224 target_ulong satp; /* since: priv-1.10.0 */ 225 target_ulong stval; 226 target_ulong medeleg; 227 228 target_ulong stvec; 229 target_ulong sepc; 230 target_ulong scause; 231 232 target_ulong mtvec; 233 target_ulong mepc; 234 target_ulong mcause; 235 target_ulong mtval; /* since: priv-1.10.0 */ 236 237 /* Machine and Supervisor interrupt priorities */ 238 uint8_t miprio[64]; 239 uint8_t siprio[64]; 240 241 /* AIA CSRs */ 242 target_ulong miselect; 243 target_ulong siselect; 244 245 /* Hypervisor CSRs */ 246 target_ulong hstatus; 247 target_ulong hedeleg; 248 uint64_t hideleg; 249 target_ulong hcounteren; 250 target_ulong htval; 251 target_ulong htinst; 252 target_ulong hgatp; 253 target_ulong hgeie; 254 target_ulong hgeip; 255 uint64_t htimedelta; 256 257 /* Hypervisor controlled virtual interrupt priorities */ 258 target_ulong hvictl; 259 uint8_t hviprio[64]; 260 261 /* Upper 64-bits of 128-bit CSRs */ 262 uint64_t mscratchh; 263 uint64_t sscratchh; 264 265 /* Virtual CSRs */ 266 /* 267 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 268 * For RV64 this is a 64-bit vsstatus. 269 */ 270 uint64_t vsstatus; 271 target_ulong vstvec; 272 target_ulong vsscratch; 273 target_ulong vsepc; 274 target_ulong vscause; 275 target_ulong vstval; 276 target_ulong vsatp; 277 278 /* AIA VS-mode CSRs */ 279 target_ulong vsiselect; 280 281 target_ulong mtval2; 282 target_ulong mtinst; 283 284 /* HS Backup CSRs */ 285 target_ulong stvec_hs; 286 target_ulong sscratch_hs; 287 target_ulong sepc_hs; 288 target_ulong scause_hs; 289 target_ulong stval_hs; 290 target_ulong satp_hs; 291 uint64_t mstatus_hs; 292 293 /* Signals whether the current exception occurred with two-stage address 294 translation active. */ 295 bool two_stage_lookup; 296 /* 297 * Signals whether the current exception occurred while doing two-stage 298 * address translation for the VS-stage page table walk. 299 */ 300 bool two_stage_indirect_lookup; 301 302 target_ulong scounteren; 303 target_ulong mcounteren; 304 305 target_ulong mcountinhibit; 306 307 /* PMU counter state */ 308 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 309 310 /* PMU event selector configured values. First three are unused*/ 311 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 312 313 /* PMU event selector configured values for RV32*/ 314 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 315 316 target_ulong sscratch; 317 target_ulong mscratch; 318 319 /* Sstc CSRs */ 320 uint64_t stimecmp; 321 322 uint64_t vstimecmp; 323 324 /* physical memory protection */ 325 pmp_table_t pmp_state; 326 target_ulong mseccfg; 327 328 /* trigger module */ 329 target_ulong trigger_cur; 330 target_ulong tdata1[RV_MAX_TRIGGERS]; 331 target_ulong tdata2[RV_MAX_TRIGGERS]; 332 target_ulong tdata3[RV_MAX_TRIGGERS]; 333 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 334 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 335 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 336 int64_t last_icount; 337 bool itrigger_enabled; 338 339 /* machine specific rdtime callback */ 340 uint64_t (*rdtime_fn)(void *); 341 void *rdtime_fn_arg; 342 343 /* machine specific AIA ireg read-modify-write callback */ 344 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 345 ((((__xlen) & 0xff) << 24) | \ 346 (((__vgein) & 0x3f) << 20) | \ 347 (((__virt) & 0x1) << 18) | \ 348 (((__priv) & 0x3) << 16) | \ 349 (__isel & 0xffff)) 350 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 351 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 352 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 353 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 354 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 355 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 356 target_ulong *val, target_ulong new_val, target_ulong write_mask); 357 void *aia_ireg_rmw_fn_arg[4]; 358 359 /* True if in debugger mode. */ 360 bool debugger; 361 362 /* 363 * CSRs for PointerMasking extension 364 */ 365 target_ulong mmte; 366 target_ulong mpmmask; 367 target_ulong mpmbase; 368 target_ulong spmmask; 369 target_ulong spmbase; 370 target_ulong upmmask; 371 target_ulong upmbase; 372 373 /* CSRs for execution enviornment configuration */ 374 uint64_t menvcfg; 375 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 376 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 377 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 378 target_ulong senvcfg; 379 uint64_t henvcfg; 380 #endif 381 target_ulong cur_pmmask; 382 target_ulong cur_pmbase; 383 384 /* Fields from here on are preserved across CPU reset. */ 385 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 386 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 387 bool vstime_irq; 388 389 hwaddr kernel_addr; 390 hwaddr fdt_addr; 391 392 /* kvm timer */ 393 bool kvm_timer_dirty; 394 uint64_t kvm_timer_time; 395 uint64_t kvm_timer_compare; 396 uint64_t kvm_timer_state; 397 uint64_t kvm_timer_frequency; 398 }; 399 400 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 401 402 /** 403 * RISCVCPUClass: 404 * @parent_realize: The parent class' realize handler. 405 * @parent_phases: The parent class' reset phase handlers. 406 * 407 * A RISCV CPU model. 408 */ 409 struct RISCVCPUClass { 410 /*< private >*/ 411 CPUClass parent_class; 412 /*< public >*/ 413 DeviceRealize parent_realize; 414 ResettablePhases parent_phases; 415 }; 416 417 struct RISCVCPUConfig { 418 bool ext_i; 419 bool ext_e; 420 bool ext_g; 421 bool ext_m; 422 bool ext_a; 423 bool ext_f; 424 bool ext_d; 425 bool ext_c; 426 bool ext_s; 427 bool ext_u; 428 bool ext_h; 429 bool ext_j; 430 bool ext_v; 431 bool ext_zba; 432 bool ext_zbb; 433 bool ext_zbc; 434 bool ext_zbkb; 435 bool ext_zbkc; 436 bool ext_zbkx; 437 bool ext_zbs; 438 bool ext_zk; 439 bool ext_zkn; 440 bool ext_zknd; 441 bool ext_zkne; 442 bool ext_zknh; 443 bool ext_zkr; 444 bool ext_zks; 445 bool ext_zksed; 446 bool ext_zksh; 447 bool ext_zkt; 448 bool ext_ifencei; 449 bool ext_icsr; 450 bool ext_zihintpause; 451 bool ext_smstateen; 452 bool ext_sstc; 453 bool ext_svinval; 454 bool ext_svnapot; 455 bool ext_svpbmt; 456 bool ext_zdinx; 457 bool ext_zawrs; 458 bool ext_zfh; 459 bool ext_zfhmin; 460 bool ext_zfinx; 461 bool ext_zhinx; 462 bool ext_zhinxmin; 463 bool ext_zve32f; 464 bool ext_zve64f; 465 bool ext_zmmul; 466 bool ext_smaia; 467 bool ext_ssaia; 468 bool ext_sscofpmf; 469 bool rvv_ta_all_1s; 470 bool rvv_ma_all_1s; 471 472 uint32_t mvendorid; 473 uint64_t marchid; 474 uint64_t mimpid; 475 476 /* Vendor-specific custom extensions */ 477 bool ext_xtheadba; 478 bool ext_xtheadbb; 479 bool ext_xtheadbs; 480 bool ext_xtheadcmo; 481 bool ext_xtheadcondmov; 482 bool ext_xtheadfmemidx; 483 bool ext_xtheadfmv; 484 bool ext_xtheadmac; 485 bool ext_xtheadmemidx; 486 bool ext_xtheadmempair; 487 bool ext_xtheadsync; 488 bool ext_XVentanaCondOps; 489 490 uint8_t pmu_num; 491 char *priv_spec; 492 char *user_spec; 493 char *bext_spec; 494 char *vext_spec; 495 uint16_t vlen; 496 uint16_t elen; 497 bool mmu; 498 bool pmp; 499 bool epmp; 500 bool debug; 501 502 bool short_isa_string; 503 }; 504 505 typedef struct RISCVCPUConfig RISCVCPUConfig; 506 507 /** 508 * RISCVCPU: 509 * @env: #CPURISCVState 510 * 511 * A RISCV CPU. 512 */ 513 struct ArchCPU { 514 /*< private >*/ 515 CPUState parent_obj; 516 /*< public >*/ 517 CPUNegativeOffsetState neg; 518 CPURISCVState env; 519 520 char *dyn_csr_xml; 521 char *dyn_vreg_xml; 522 523 /* Configuration Settings */ 524 RISCVCPUConfig cfg; 525 526 QEMUTimer *pmu_timer; 527 /* A bitmask of Available programmable counters */ 528 uint32_t pmu_avail_ctrs; 529 /* Mapping of events to counters */ 530 GHashTable *pmu_event_ctr_map; 531 }; 532 533 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 534 { 535 return (env->misa_ext & ext) != 0; 536 } 537 538 static inline bool riscv_feature(CPURISCVState *env, int feature) 539 { 540 return env->features & (1ULL << feature); 541 } 542 543 static inline void riscv_set_feature(CPURISCVState *env, int feature) 544 { 545 env->features |= (1ULL << feature); 546 } 547 548 #include "cpu_user.h" 549 550 extern const char * const riscv_int_regnames[]; 551 extern const char * const riscv_int_regnamesh[]; 552 extern const char * const riscv_fpr_regnames[]; 553 554 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 555 void riscv_cpu_do_interrupt(CPUState *cpu); 556 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 557 int cpuid, DumpState *s); 558 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 559 int cpuid, DumpState *s); 560 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 561 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 562 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 563 uint8_t riscv_cpu_default_priority(int irq); 564 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 565 int riscv_cpu_mirq_pending(CPURISCVState *env); 566 int riscv_cpu_sirq_pending(CPURISCVState *env); 567 int riscv_cpu_vsirq_pending(CPURISCVState *env); 568 bool riscv_cpu_fp_enabled(CPURISCVState *env); 569 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 570 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 571 bool riscv_cpu_vector_enabled(CPURISCVState *env); 572 bool riscv_cpu_virt_enabled(CPURISCVState *env); 573 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 574 bool riscv_cpu_two_stage_lookup(int mmu_idx); 575 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 576 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 577 MMUAccessType access_type, int mmu_idx, 578 uintptr_t retaddr); 579 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 580 MMUAccessType access_type, int mmu_idx, 581 bool probe, uintptr_t retaddr); 582 char *riscv_isa_string(RISCVCPU *cpu); 583 void riscv_cpu_list(void); 584 585 #define cpu_list riscv_cpu_list 586 #define cpu_mmu_index riscv_cpu_mmu_index 587 588 #ifndef CONFIG_USER_ONLY 589 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 590 vaddr addr, unsigned size, 591 MMUAccessType access_type, 592 int mmu_idx, MemTxAttrs attrs, 593 MemTxResult response, uintptr_t retaddr); 594 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 595 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 596 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 597 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 598 uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value); 599 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 600 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 601 void *arg); 602 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 603 int (*rmw_fn)(void *arg, 604 target_ulong reg, 605 target_ulong *val, 606 target_ulong new_val, 607 target_ulong write_mask), 608 void *rmw_fn_arg); 609 #endif 610 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 611 612 void riscv_translate_init(void); 613 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 614 uint32_t exception, uintptr_t pc); 615 616 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 617 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 618 619 #define TB_FLAGS_PRIV_MMU_MASK 3 620 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 621 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 622 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 623 624 #include "exec/cpu-all.h" 625 626 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 627 FIELD(TB_FLAGS, LMUL, 3, 3) 628 FIELD(TB_FLAGS, SEW, 6, 3) 629 /* Skip MSTATUS_VS (0x600) bits */ 630 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 631 FIELD(TB_FLAGS, VILL, 12, 1) 632 /* Skip MSTATUS_FS (0x6000) bits */ 633 /* Is a Hypervisor instruction load/store allowed? */ 634 FIELD(TB_FLAGS, HLSX, 15, 1) 635 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 636 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 637 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 638 FIELD(TB_FLAGS, XL, 20, 2) 639 /* If PointerMasking should be applied */ 640 FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) 641 FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) 642 FIELD(TB_FLAGS, VTA, 24, 1) 643 FIELD(TB_FLAGS, VMA, 25, 1) 644 /* Native debug itrigger */ 645 FIELD(TB_FLAGS, ITRIGGER, 26, 1) 646 647 #ifdef TARGET_RISCV32 648 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 649 #else 650 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 651 { 652 return env->misa_mxl; 653 } 654 #endif 655 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 656 657 #if defined(TARGET_RISCV32) 658 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 659 #else 660 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 661 { 662 RISCVMXL xl = env->misa_mxl; 663 #if !defined(CONFIG_USER_ONLY) 664 /* 665 * When emulating a 32-bit-only cpu, use RV32. 666 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 667 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 668 * back to RV64 for lower privs. 669 */ 670 if (xl != MXL_RV32) { 671 switch (env->priv) { 672 case PRV_M: 673 break; 674 case PRV_U: 675 xl = get_field(env->mstatus, MSTATUS64_UXL); 676 break; 677 default: /* PRV_S | PRV_H */ 678 xl = get_field(env->mstatus, MSTATUS64_SXL); 679 break; 680 } 681 } 682 #endif 683 return xl; 684 } 685 #endif 686 687 static inline int riscv_cpu_xlen(CPURISCVState *env) 688 { 689 return 16 << env->xl; 690 } 691 692 #ifdef TARGET_RISCV32 693 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 694 #else 695 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 696 { 697 #ifdef CONFIG_USER_ONLY 698 return env->misa_mxl; 699 #else 700 return get_field(env->mstatus, MSTATUS64_SXL); 701 #endif 702 } 703 #endif 704 705 /* 706 * Encode LMUL to lmul as follows: 707 * LMUL vlmul lmul 708 * 1 000 0 709 * 2 001 1 710 * 4 010 2 711 * 8 011 3 712 * - 100 - 713 * 1/8 101 -3 714 * 1/4 110 -2 715 * 1/2 111 -1 716 * 717 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 718 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 719 * => VLMAX = vlen >> (1 + 3 - (-3)) 720 * = 256 >> 7 721 * = 2 722 */ 723 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 724 { 725 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 726 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 727 return cpu->cfg.vlen >> (sew + 3 - lmul); 728 } 729 730 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 731 target_ulong *cs_base, uint32_t *pflags); 732 733 void riscv_cpu_update_mask(CPURISCVState *env); 734 735 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 736 target_ulong *ret_value, 737 target_ulong new_value, target_ulong write_mask); 738 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 739 target_ulong *ret_value, 740 target_ulong new_value, 741 target_ulong write_mask); 742 743 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 744 target_ulong val) 745 { 746 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 747 } 748 749 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 750 { 751 target_ulong val = 0; 752 riscv_csrrw(env, csrno, &val, 0, 0); 753 return val; 754 } 755 756 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 757 int csrno); 758 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 759 target_ulong *ret_value); 760 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 761 target_ulong new_value); 762 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 763 target_ulong *ret_value, 764 target_ulong new_value, 765 target_ulong write_mask); 766 767 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 768 Int128 *ret_value, 769 Int128 new_value, Int128 write_mask); 770 771 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 772 Int128 *ret_value); 773 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 774 Int128 new_value); 775 776 typedef struct { 777 const char *name; 778 riscv_csr_predicate_fn predicate; 779 riscv_csr_read_fn read; 780 riscv_csr_write_fn write; 781 riscv_csr_op_fn op; 782 riscv_csr_read128_fn read128; 783 riscv_csr_write128_fn write128; 784 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 785 uint32_t min_priv_ver; 786 } riscv_csr_operations; 787 788 /* CSR function table constants */ 789 enum { 790 CSR_TABLE_SIZE = 0x1000 791 }; 792 793 /** 794 * The event id are encoded based on the encoding specified in the 795 * SBI specification v0.3 796 */ 797 798 enum riscv_pmu_event_idx { 799 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 800 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 801 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 802 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 803 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 804 }; 805 806 /* CSR function table */ 807 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 808 809 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 810 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 811 812 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 813 814 #endif /* RISCV_CPU_H */ 815