1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "qemu/cpu-float.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 #include "qapi/qapi-types-common.h" 31 #include "cpu-qom.h" 32 33 #define TCG_GUEST_DEFAULT_MO 0 34 35 /* 36 * RISC-V-specific extra insn start words: 37 * 1: Original instruction opcode 38 */ 39 #define TARGET_INSN_START_EXTRA_WORDS 1 40 41 #define RV(x) ((target_ulong)1 << (x - 'A')) 42 43 /* Consider updating misa_ext_cfgs[] when adding new MISA bits here */ 44 #define RVI RV('I') 45 #define RVE RV('E') /* E and I are mutually exclusive */ 46 #define RVM RV('M') 47 #define RVA RV('A') 48 #define RVF RV('F') 49 #define RVD RV('D') 50 #define RVV RV('V') 51 #define RVC RV('C') 52 #define RVS RV('S') 53 #define RVU RV('U') 54 #define RVH RV('H') 55 #define RVJ RV('J') 56 #define RVG RV('G') 57 58 59 /* Privileged specification version */ 60 enum { 61 PRIV_VERSION_1_10_0 = 0, 62 PRIV_VERSION_1_11_0, 63 PRIV_VERSION_1_12_0, 64 }; 65 66 #define VEXT_VERSION_1_00_0 0x00010000 67 68 enum { 69 TRANSLATE_SUCCESS, 70 TRANSLATE_FAIL, 71 TRANSLATE_PMP_FAIL, 72 TRANSLATE_G_STAGE_FAIL 73 }; 74 75 /* Extension context status */ 76 typedef enum { 77 EXT_STATUS_DISABLED = 0, 78 EXT_STATUS_INITIAL, 79 EXT_STATUS_CLEAN, 80 EXT_STATUS_DIRTY, 81 } RISCVExtStatus; 82 83 #define MMU_USER_IDX 3 84 85 #define MAX_RISCV_PMPS (16) 86 87 #if !defined(CONFIG_USER_ONLY) 88 #include "pmp.h" 89 #include "debug.h" 90 #endif 91 92 #define RV_VLEN_MAX 1024 93 #define RV_MAX_MHPMEVENTS 32 94 #define RV_MAX_MHPMCOUNTERS 32 95 96 FIELD(VTYPE, VLMUL, 0, 3) 97 FIELD(VTYPE, VSEW, 3, 3) 98 FIELD(VTYPE, VTA, 6, 1) 99 FIELD(VTYPE, VMA, 7, 1) 100 FIELD(VTYPE, VEDIV, 8, 2) 101 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 102 103 typedef struct PMUCTRState { 104 /* Current value of a counter */ 105 target_ulong mhpmcounter_val; 106 /* Current value of a counter in RV32 */ 107 target_ulong mhpmcounterh_val; 108 /* Snapshot values of counter */ 109 target_ulong mhpmcounter_prev; 110 /* Snapshort value of a counter in RV32 */ 111 target_ulong mhpmcounterh_prev; 112 bool started; 113 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 114 target_ulong irq_overflow_left; 115 } PMUCTRState; 116 117 struct CPUArchState { 118 target_ulong gpr[32]; 119 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 120 121 /* vector coprocessor state. */ 122 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 123 target_ulong vxrm; 124 target_ulong vxsat; 125 target_ulong vl; 126 target_ulong vstart; 127 target_ulong vtype; 128 bool vill; 129 130 target_ulong pc; 131 target_ulong load_res; 132 target_ulong load_val; 133 134 /* Floating-Point state */ 135 uint64_t fpr[32]; /* assume both F and D extensions */ 136 target_ulong frm; 137 float_status fp_status; 138 139 target_ulong badaddr; 140 target_ulong bins; 141 142 target_ulong guest_phys_fault_addr; 143 144 target_ulong priv_ver; 145 target_ulong bext_ver; 146 target_ulong vext_ver; 147 148 /* RISCVMXL, but uint32_t for vmstate migration */ 149 uint32_t misa_mxl; /* current mxl */ 150 uint32_t misa_mxl_max; /* max mxl for this cpu */ 151 uint32_t misa_ext; /* current extensions */ 152 uint32_t misa_ext_mask; /* max ext for this cpu */ 153 uint32_t xl; /* current xlen */ 154 155 /* 128-bit helpers upper part return value */ 156 target_ulong retxh; 157 158 target_ulong jvt; 159 160 #ifdef CONFIG_USER_ONLY 161 uint32_t elf_flags; 162 #endif 163 164 #ifndef CONFIG_USER_ONLY 165 target_ulong priv; 166 /* This contains QEMU specific information about the virt state. */ 167 bool virt_enabled; 168 target_ulong geilen; 169 uint64_t resetvec; 170 171 target_ulong mhartid; 172 /* 173 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 174 * For RV64 this is a 64-bit mstatus. 175 */ 176 uint64_t mstatus; 177 178 uint64_t mip; 179 /* 180 * MIP contains the software writable version of SEIP ORed with the 181 * external interrupt value. The MIP register is always up-to-date. 182 * To keep track of the current source, we also save booleans of the values 183 * here. 184 */ 185 bool external_seip; 186 bool software_seip; 187 188 uint64_t miclaim; 189 190 uint64_t mie; 191 uint64_t mideleg; 192 193 target_ulong satp; /* since: priv-1.10.0 */ 194 target_ulong stval; 195 target_ulong medeleg; 196 197 target_ulong stvec; 198 target_ulong sepc; 199 target_ulong scause; 200 201 target_ulong mtvec; 202 target_ulong mepc; 203 target_ulong mcause; 204 target_ulong mtval; /* since: priv-1.10.0 */ 205 206 /* Machine and Supervisor interrupt priorities */ 207 uint8_t miprio[64]; 208 uint8_t siprio[64]; 209 210 /* AIA CSRs */ 211 target_ulong miselect; 212 target_ulong siselect; 213 214 /* Hypervisor CSRs */ 215 target_ulong hstatus; 216 target_ulong hedeleg; 217 uint64_t hideleg; 218 target_ulong hcounteren; 219 target_ulong htval; 220 target_ulong htinst; 221 target_ulong hgatp; 222 target_ulong hgeie; 223 target_ulong hgeip; 224 uint64_t htimedelta; 225 226 /* Hypervisor controlled virtual interrupt priorities */ 227 target_ulong hvictl; 228 uint8_t hviprio[64]; 229 230 /* Upper 64-bits of 128-bit CSRs */ 231 uint64_t mscratchh; 232 uint64_t sscratchh; 233 234 /* Virtual CSRs */ 235 /* 236 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 237 * For RV64 this is a 64-bit vsstatus. 238 */ 239 uint64_t vsstatus; 240 target_ulong vstvec; 241 target_ulong vsscratch; 242 target_ulong vsepc; 243 target_ulong vscause; 244 target_ulong vstval; 245 target_ulong vsatp; 246 247 /* AIA VS-mode CSRs */ 248 target_ulong vsiselect; 249 250 target_ulong mtval2; 251 target_ulong mtinst; 252 253 /* HS Backup CSRs */ 254 target_ulong stvec_hs; 255 target_ulong sscratch_hs; 256 target_ulong sepc_hs; 257 target_ulong scause_hs; 258 target_ulong stval_hs; 259 target_ulong satp_hs; 260 uint64_t mstatus_hs; 261 262 /* 263 * Signals whether the current exception occurred with two-stage address 264 * translation active. 265 */ 266 bool two_stage_lookup; 267 /* 268 * Signals whether the current exception occurred while doing two-stage 269 * address translation for the VS-stage page table walk. 270 */ 271 bool two_stage_indirect_lookup; 272 273 target_ulong scounteren; 274 target_ulong mcounteren; 275 276 target_ulong mcountinhibit; 277 278 /* PMU counter state */ 279 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 280 281 /* PMU event selector configured values. First three are unused */ 282 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 283 284 /* PMU event selector configured values for RV32 */ 285 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 286 287 target_ulong sscratch; 288 target_ulong mscratch; 289 290 /* Sstc CSRs */ 291 uint64_t stimecmp; 292 293 uint64_t vstimecmp; 294 295 /* physical memory protection */ 296 pmp_table_t pmp_state; 297 target_ulong mseccfg; 298 299 /* trigger module */ 300 target_ulong trigger_cur; 301 target_ulong tdata1[RV_MAX_TRIGGERS]; 302 target_ulong tdata2[RV_MAX_TRIGGERS]; 303 target_ulong tdata3[RV_MAX_TRIGGERS]; 304 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 305 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 306 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 307 int64_t last_icount; 308 bool itrigger_enabled; 309 310 /* machine specific rdtime callback */ 311 uint64_t (*rdtime_fn)(void *); 312 void *rdtime_fn_arg; 313 314 /* machine specific AIA ireg read-modify-write callback */ 315 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 316 ((((__xlen) & 0xff) << 24) | \ 317 (((__vgein) & 0x3f) << 20) | \ 318 (((__virt) & 0x1) << 18) | \ 319 (((__priv) & 0x3) << 16) | \ 320 (__isel & 0xffff)) 321 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 322 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 323 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 324 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 325 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 326 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 327 target_ulong *val, target_ulong new_val, target_ulong write_mask); 328 void *aia_ireg_rmw_fn_arg[4]; 329 330 /* True if in debugger mode. */ 331 bool debugger; 332 333 /* 334 * CSRs for PointerMasking extension 335 */ 336 target_ulong mmte; 337 target_ulong mpmmask; 338 target_ulong mpmbase; 339 target_ulong spmmask; 340 target_ulong spmbase; 341 target_ulong upmmask; 342 target_ulong upmbase; 343 344 /* CSRs for execution enviornment configuration */ 345 uint64_t menvcfg; 346 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 347 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 348 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 349 target_ulong senvcfg; 350 uint64_t henvcfg; 351 #endif 352 target_ulong cur_pmmask; 353 target_ulong cur_pmbase; 354 355 /* Fields from here on are preserved across CPU reset. */ 356 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 357 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 358 bool vstime_irq; 359 360 hwaddr kernel_addr; 361 hwaddr fdt_addr; 362 363 /* kvm timer */ 364 bool kvm_timer_dirty; 365 uint64_t kvm_timer_time; 366 uint64_t kvm_timer_compare; 367 uint64_t kvm_timer_state; 368 uint64_t kvm_timer_frequency; 369 }; 370 371 /* 372 * map is a 16-bit bitmap: the most significant set bit in map is the maximum 373 * satp mode that is supported. It may be chosen by the user and must respect 374 * what qemu implements (valid_1_10_32/64) and what the hw is capable of 375 * (supported bitmap below). 376 * 377 * init is a 16-bit bitmap used to make sure the user selected a correct 378 * configuration as per the specification. 379 * 380 * supported is a 16-bit bitmap used to reflect the hw capabilities. 381 */ 382 typedef struct { 383 uint16_t map, init, supported; 384 } RISCVSATPMap; 385 386 struct RISCVCPUConfig { 387 bool ext_zba; 388 bool ext_zbb; 389 bool ext_zbc; 390 bool ext_zbkb; 391 bool ext_zbkc; 392 bool ext_zbkx; 393 bool ext_zbs; 394 bool ext_zca; 395 bool ext_zcb; 396 bool ext_zcd; 397 bool ext_zce; 398 bool ext_zcf; 399 bool ext_zcmp; 400 bool ext_zcmt; 401 bool ext_zk; 402 bool ext_zkn; 403 bool ext_zknd; 404 bool ext_zkne; 405 bool ext_zknh; 406 bool ext_zkr; 407 bool ext_zks; 408 bool ext_zksed; 409 bool ext_zksh; 410 bool ext_zkt; 411 bool ext_ifencei; 412 bool ext_icsr; 413 bool ext_icbom; 414 bool ext_icboz; 415 bool ext_zicond; 416 bool ext_zihintpause; 417 bool ext_smstateen; 418 bool ext_sstc; 419 bool ext_svadu; 420 bool ext_svinval; 421 bool ext_svnapot; 422 bool ext_svpbmt; 423 bool ext_zdinx; 424 bool ext_zawrs; 425 bool ext_zfh; 426 bool ext_zfhmin; 427 bool ext_zfinx; 428 bool ext_zhinx; 429 bool ext_zhinxmin; 430 bool ext_zve32f; 431 bool ext_zve64f; 432 bool ext_zve64d; 433 bool ext_zmmul; 434 bool ext_zvfh; 435 bool ext_zvfhmin; 436 bool ext_smaia; 437 bool ext_ssaia; 438 bool ext_sscofpmf; 439 bool rvv_ta_all_1s; 440 bool rvv_ma_all_1s; 441 442 uint32_t mvendorid; 443 uint64_t marchid; 444 uint64_t mimpid; 445 446 /* Vendor-specific custom extensions */ 447 bool ext_xtheadba; 448 bool ext_xtheadbb; 449 bool ext_xtheadbs; 450 bool ext_xtheadcmo; 451 bool ext_xtheadcondmov; 452 bool ext_xtheadfmemidx; 453 bool ext_xtheadfmv; 454 bool ext_xtheadmac; 455 bool ext_xtheadmemidx; 456 bool ext_xtheadmempair; 457 bool ext_xtheadsync; 458 bool ext_XVentanaCondOps; 459 460 uint8_t pmu_num; 461 char *priv_spec; 462 char *user_spec; 463 char *bext_spec; 464 char *vext_spec; 465 uint16_t vlen; 466 uint16_t elen; 467 uint16_t cbom_blocksize; 468 uint16_t cboz_blocksize; 469 bool mmu; 470 bool pmp; 471 bool epmp; 472 bool debug; 473 bool misa_w; 474 475 bool short_isa_string; 476 477 #ifndef CONFIG_USER_ONLY 478 RISCVSATPMap satp_mode; 479 #endif 480 }; 481 482 typedef struct RISCVCPUConfig RISCVCPUConfig; 483 484 /* 485 * RISCVCPU: 486 * @env: #CPURISCVState 487 * 488 * A RISCV CPU. 489 */ 490 struct ArchCPU { 491 /* < private > */ 492 CPUState parent_obj; 493 /* < public > */ 494 CPUNegativeOffsetState neg; 495 CPURISCVState env; 496 497 char *dyn_csr_xml; 498 char *dyn_vreg_xml; 499 500 /* Configuration Settings */ 501 RISCVCPUConfig cfg; 502 503 QEMUTimer *pmu_timer; 504 /* A bitmask of Available programmable counters */ 505 uint32_t pmu_avail_ctrs; 506 /* Mapping of events to counters */ 507 GHashTable *pmu_event_ctr_map; 508 }; 509 510 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 511 { 512 return (env->misa_ext & ext) != 0; 513 } 514 515 #include "cpu_user.h" 516 517 extern const char * const riscv_int_regnames[]; 518 extern const char * const riscv_int_regnamesh[]; 519 extern const char * const riscv_fpr_regnames[]; 520 521 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 522 void riscv_cpu_do_interrupt(CPUState *cpu); 523 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 524 int cpuid, DumpState *s); 525 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 526 int cpuid, DumpState *s); 527 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 528 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 529 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 530 uint8_t riscv_cpu_default_priority(int irq); 531 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 532 int riscv_cpu_mirq_pending(CPURISCVState *env); 533 int riscv_cpu_sirq_pending(CPURISCVState *env); 534 int riscv_cpu_vsirq_pending(CPURISCVState *env); 535 bool riscv_cpu_fp_enabled(CPURISCVState *env); 536 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 537 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 538 bool riscv_cpu_vector_enabled(CPURISCVState *env); 539 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 540 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 541 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 542 MMUAccessType access_type, 543 int mmu_idx, uintptr_t retaddr); 544 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 545 MMUAccessType access_type, int mmu_idx, 546 bool probe, uintptr_t retaddr); 547 char *riscv_isa_string(RISCVCPU *cpu); 548 void riscv_cpu_list(void); 549 550 #define cpu_list riscv_cpu_list 551 #define cpu_mmu_index riscv_cpu_mmu_index 552 553 #ifndef CONFIG_USER_ONLY 554 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 555 vaddr addr, unsigned size, 556 MMUAccessType access_type, 557 int mmu_idx, MemTxAttrs attrs, 558 MemTxResult response, uintptr_t retaddr); 559 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 560 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 561 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 562 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 563 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 564 uint64_t value); 565 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 566 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 567 void *arg); 568 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 569 int (*rmw_fn)(void *arg, 570 target_ulong reg, 571 target_ulong *val, 572 target_ulong new_val, 573 target_ulong write_mask), 574 void *rmw_fn_arg); 575 576 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 577 #endif 578 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 579 580 void riscv_translate_init(void); 581 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 582 uint32_t exception, uintptr_t pc); 583 584 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 585 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 586 587 #include "exec/cpu-all.h" 588 589 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 590 FIELD(TB_FLAGS, FS, 3, 2) 591 /* Vector flags */ 592 FIELD(TB_FLAGS, VS, 5, 2) 593 FIELD(TB_FLAGS, LMUL, 7, 3) 594 FIELD(TB_FLAGS, SEW, 10, 3) 595 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) 596 FIELD(TB_FLAGS, VILL, 14, 1) 597 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) 598 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 599 FIELD(TB_FLAGS, XL, 16, 2) 600 /* If PointerMasking should be applied */ 601 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) 602 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) 603 FIELD(TB_FLAGS, VTA, 20, 1) 604 FIELD(TB_FLAGS, VMA, 21, 1) 605 /* Native debug itrigger */ 606 FIELD(TB_FLAGS, ITRIGGER, 22, 1) 607 /* Virtual mode enabled */ 608 FIELD(TB_FLAGS, VIRT_ENABLED, 23, 1) 609 FIELD(TB_FLAGS, PRIV, 24, 2) 610 611 #ifdef TARGET_RISCV32 612 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 613 #else 614 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 615 { 616 return env->misa_mxl; 617 } 618 #endif 619 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 620 621 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 622 { 623 return &env_archcpu(env)->cfg; 624 } 625 626 #if defined(TARGET_RISCV32) 627 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 628 #else 629 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 630 { 631 RISCVMXL xl = env->misa_mxl; 632 #if !defined(CONFIG_USER_ONLY) 633 /* 634 * When emulating a 32-bit-only cpu, use RV32. 635 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 636 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 637 * back to RV64 for lower privs. 638 */ 639 if (xl != MXL_RV32) { 640 switch (env->priv) { 641 case PRV_M: 642 break; 643 case PRV_U: 644 xl = get_field(env->mstatus, MSTATUS64_UXL); 645 break; 646 default: /* PRV_S */ 647 xl = get_field(env->mstatus, MSTATUS64_SXL); 648 break; 649 } 650 } 651 #endif 652 return xl; 653 } 654 #endif 655 656 static inline int riscv_cpu_xlen(CPURISCVState *env) 657 { 658 return 16 << env->xl; 659 } 660 661 #ifdef TARGET_RISCV32 662 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 663 #else 664 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 665 { 666 #ifdef CONFIG_USER_ONLY 667 return env->misa_mxl; 668 #else 669 return get_field(env->mstatus, MSTATUS64_SXL); 670 #endif 671 } 672 #endif 673 674 /* 675 * Encode LMUL to lmul as follows: 676 * LMUL vlmul lmul 677 * 1 000 0 678 * 2 001 1 679 * 4 010 2 680 * 8 011 3 681 * - 100 - 682 * 1/8 101 -3 683 * 1/4 110 -2 684 * 1/2 111 -1 685 * 686 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 687 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 688 * => VLMAX = vlen >> (1 + 3 - (-3)) 689 * = 256 >> 7 690 * = 2 691 */ 692 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 693 { 694 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 695 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 696 return cpu->cfg.vlen >> (sew + 3 - lmul); 697 } 698 699 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 700 target_ulong *cs_base, uint32_t *pflags); 701 702 void riscv_cpu_update_mask(CPURISCVState *env); 703 704 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 705 target_ulong *ret_value, 706 target_ulong new_value, target_ulong write_mask); 707 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 708 target_ulong *ret_value, 709 target_ulong new_value, 710 target_ulong write_mask); 711 712 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 713 target_ulong val) 714 { 715 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 716 } 717 718 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 719 { 720 target_ulong val = 0; 721 riscv_csrrw(env, csrno, &val, 0, 0); 722 return val; 723 } 724 725 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 726 int csrno); 727 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 728 target_ulong *ret_value); 729 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 730 target_ulong new_value); 731 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 732 target_ulong *ret_value, 733 target_ulong new_value, 734 target_ulong write_mask); 735 736 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 737 Int128 *ret_value, 738 Int128 new_value, Int128 write_mask); 739 740 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 741 Int128 *ret_value); 742 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 743 Int128 new_value); 744 745 typedef struct { 746 const char *name; 747 riscv_csr_predicate_fn predicate; 748 riscv_csr_read_fn read; 749 riscv_csr_write_fn write; 750 riscv_csr_op_fn op; 751 riscv_csr_read128_fn read128; 752 riscv_csr_write128_fn write128; 753 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 754 uint32_t min_priv_ver; 755 } riscv_csr_operations; 756 757 /* CSR function table constants */ 758 enum { 759 CSR_TABLE_SIZE = 0x1000 760 }; 761 762 /* 763 * The event id are encoded based on the encoding specified in the 764 * SBI specification v0.3 765 */ 766 767 enum riscv_pmu_event_idx { 768 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 769 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 770 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 771 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 772 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 773 }; 774 775 /* CSR function table */ 776 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 777 778 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 779 780 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 781 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 782 783 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 784 785 uint8_t satp_mode_max_from_map(uint32_t map); 786 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 787 788 #endif /* RISCV_CPU_H */ 789