1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "exec/cpu-defs.h" 26 #include "fpu/softfloat-types.h" 27 #include "qom/object.h" 28 #include "qemu/int128.h" 29 #include "cpu_bits.h" 30 31 #define TCG_GUEST_DEFAULT_MO 0 32 33 #define TYPE_RISCV_CPU "riscv-cpu" 34 35 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 36 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 37 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 38 39 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 40 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 41 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 42 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 43 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 44 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 45 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 46 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 47 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 48 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 49 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 50 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 51 52 #if defined(TARGET_RISCV32) 53 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 54 #elif defined(TARGET_RISCV64) 55 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 56 #endif 57 58 #define RV(x) ((target_ulong)1 << (x - 'A')) 59 60 #define RVI RV('I') 61 #define RVE RV('E') /* E and I are mutually exclusive */ 62 #define RVM RV('M') 63 #define RVA RV('A') 64 #define RVF RV('F') 65 #define RVD RV('D') 66 #define RVV RV('V') 67 #define RVC RV('C') 68 #define RVS RV('S') 69 #define RVU RV('U') 70 #define RVH RV('H') 71 #define RVJ RV('J') 72 73 /* S extension denotes that Supervisor mode exists, however it is possible 74 to have a core that support S mode but does not have an MMU and there 75 is currently no bit in misa to indicate whether an MMU exists or not 76 so a cpu features bitfield is required, likewise for optional PMP support */ 77 enum { 78 RISCV_FEATURE_MMU, 79 RISCV_FEATURE_PMP, 80 RISCV_FEATURE_EPMP, 81 RISCV_FEATURE_MISA 82 }; 83 84 #define PRIV_VERSION_1_10_0 0x00011000 85 #define PRIV_VERSION_1_11_0 0x00011100 86 87 #define VEXT_VERSION_1_00_0 0x00010000 88 89 enum { 90 TRANSLATE_SUCCESS, 91 TRANSLATE_FAIL, 92 TRANSLATE_PMP_FAIL, 93 TRANSLATE_G_STAGE_FAIL 94 }; 95 96 #define MMU_USER_IDX 3 97 98 #define MAX_RISCV_PMPS (16) 99 100 typedef struct CPURISCVState CPURISCVState; 101 102 #if !defined(CONFIG_USER_ONLY) 103 #include "pmp.h" 104 #endif 105 106 #define RV_VLEN_MAX 1024 107 108 FIELD(VTYPE, VLMUL, 0, 3) 109 FIELD(VTYPE, VSEW, 3, 3) 110 FIELD(VTYPE, VTA, 6, 1) 111 FIELD(VTYPE, VMA, 7, 1) 112 FIELD(VTYPE, VEDIV, 8, 2) 113 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 114 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1) 115 116 struct CPURISCVState { 117 target_ulong gpr[32]; 118 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 119 uint64_t fpr[32]; /* assume both F and D extensions */ 120 121 /* vector coprocessor state. */ 122 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 123 target_ulong vxrm; 124 target_ulong vxsat; 125 target_ulong vl; 126 target_ulong vstart; 127 target_ulong vtype; 128 129 target_ulong pc; 130 target_ulong load_res; 131 target_ulong load_val; 132 133 target_ulong frm; 134 135 target_ulong badaddr; 136 uint32_t bins; 137 138 target_ulong guest_phys_fault_addr; 139 140 target_ulong priv_ver; 141 target_ulong bext_ver; 142 target_ulong vext_ver; 143 144 /* RISCVMXL, but uint32_t for vmstate migration */ 145 uint32_t misa_mxl; /* current mxl */ 146 uint32_t misa_mxl_max; /* max mxl for this cpu */ 147 uint32_t misa_ext; /* current extensions */ 148 uint32_t misa_ext_mask; /* max ext for this cpu */ 149 150 /* 128-bit helpers upper part return value */ 151 target_ulong retxh; 152 153 uint32_t features; 154 155 #ifdef CONFIG_USER_ONLY 156 uint32_t elf_flags; 157 #endif 158 159 #ifndef CONFIG_USER_ONLY 160 target_ulong priv; 161 /* This contains QEMU specific information about the virt state. */ 162 target_ulong virt; 163 target_ulong resetvec; 164 165 target_ulong mhartid; 166 /* 167 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 168 * For RV64 this is a 64-bit mstatus. 169 */ 170 uint64_t mstatus; 171 172 target_ulong mip; 173 174 uint32_t miclaim; 175 176 target_ulong mie; 177 target_ulong mideleg; 178 179 target_ulong satp; /* since: priv-1.10.0 */ 180 target_ulong stval; 181 target_ulong medeleg; 182 183 target_ulong stvec; 184 target_ulong sepc; 185 target_ulong scause; 186 187 target_ulong mtvec; 188 target_ulong mepc; 189 target_ulong mcause; 190 target_ulong mtval; /* since: priv-1.10.0 */ 191 192 /* Hypervisor CSRs */ 193 target_ulong hstatus; 194 target_ulong hedeleg; 195 target_ulong hideleg; 196 target_ulong hcounteren; 197 target_ulong htval; 198 target_ulong htinst; 199 target_ulong hgatp; 200 uint64_t htimedelta; 201 202 /* Upper 64-bits of 128-bit CSRs */ 203 uint64_t mscratchh; 204 uint64_t sscratchh; 205 206 /* Virtual CSRs */ 207 /* 208 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 209 * For RV64 this is a 64-bit vsstatus. 210 */ 211 uint64_t vsstatus; 212 target_ulong vstvec; 213 target_ulong vsscratch; 214 target_ulong vsepc; 215 target_ulong vscause; 216 target_ulong vstval; 217 target_ulong vsatp; 218 219 target_ulong mtval2; 220 target_ulong mtinst; 221 222 /* HS Backup CSRs */ 223 target_ulong stvec_hs; 224 target_ulong sscratch_hs; 225 target_ulong sepc_hs; 226 target_ulong scause_hs; 227 target_ulong stval_hs; 228 target_ulong satp_hs; 229 uint64_t mstatus_hs; 230 231 /* Signals whether the current exception occurred with two-stage address 232 translation active. */ 233 bool two_stage_lookup; 234 235 target_ulong scounteren; 236 target_ulong mcounteren; 237 238 target_ulong sscratch; 239 target_ulong mscratch; 240 241 /* temporary htif regs */ 242 uint64_t mfromhost; 243 uint64_t mtohost; 244 uint64_t timecmp; 245 246 /* physical memory protection */ 247 pmp_table_t pmp_state; 248 target_ulong mseccfg; 249 250 /* machine specific rdtime callback */ 251 uint64_t (*rdtime_fn)(uint32_t); 252 uint32_t rdtime_fn_arg; 253 254 /* True if in debugger mode. */ 255 bool debugger; 256 257 /* 258 * CSRs for PointerMasking extension 259 */ 260 target_ulong mmte; 261 target_ulong mpmmask; 262 target_ulong mpmbase; 263 target_ulong spmmask; 264 target_ulong spmbase; 265 target_ulong upmmask; 266 target_ulong upmbase; 267 #endif 268 269 float_status fp_status; 270 271 /* Fields from here on are preserved across CPU reset. */ 272 QEMUTimer *timer; /* Internal timer */ 273 274 hwaddr kernel_addr; 275 hwaddr fdt_addr; 276 }; 277 278 OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, 279 RISCV_CPU) 280 281 /** 282 * RISCVCPUClass: 283 * @parent_realize: The parent class' realize handler. 284 * @parent_reset: The parent class' reset handler. 285 * 286 * A RISCV CPU model. 287 */ 288 struct RISCVCPUClass { 289 /*< private >*/ 290 CPUClass parent_class; 291 /*< public >*/ 292 DeviceRealize parent_realize; 293 DeviceReset parent_reset; 294 }; 295 296 /** 297 * RISCVCPU: 298 * @env: #CPURISCVState 299 * 300 * A RISCV CPU. 301 */ 302 struct RISCVCPU { 303 /*< private >*/ 304 CPUState parent_obj; 305 /*< public >*/ 306 CPUNegativeOffsetState neg; 307 CPURISCVState env; 308 309 char *dyn_csr_xml; 310 char *dyn_vreg_xml; 311 312 /* Configuration Settings */ 313 struct { 314 bool ext_i; 315 bool ext_e; 316 bool ext_g; 317 bool ext_m; 318 bool ext_a; 319 bool ext_f; 320 bool ext_d; 321 bool ext_c; 322 bool ext_s; 323 bool ext_u; 324 bool ext_h; 325 bool ext_j; 326 bool ext_v; 327 bool ext_zba; 328 bool ext_zbb; 329 bool ext_zbc; 330 bool ext_zbs; 331 bool ext_counters; 332 bool ext_ifencei; 333 bool ext_icsr; 334 bool ext_zfh; 335 bool ext_zfhmin; 336 337 char *priv_spec; 338 char *user_spec; 339 char *bext_spec; 340 char *vext_spec; 341 uint16_t vlen; 342 uint16_t elen; 343 bool mmu; 344 bool pmp; 345 bool epmp; 346 uint64_t resetvec; 347 } cfg; 348 }; 349 350 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 351 { 352 return (env->misa_ext & ext) != 0; 353 } 354 355 static inline bool riscv_feature(CPURISCVState *env, int feature) 356 { 357 return env->features & (1ULL << feature); 358 } 359 360 #include "cpu_user.h" 361 362 extern const char * const riscv_int_regnames[]; 363 extern const char * const riscv_int_regnamesh[]; 364 extern const char * const riscv_fpr_regnames[]; 365 366 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 367 void riscv_cpu_do_interrupt(CPUState *cpu); 368 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 369 int cpuid, void *opaque); 370 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 371 int cpuid, void *opaque); 372 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 373 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 374 bool riscv_cpu_fp_enabled(CPURISCVState *env); 375 bool riscv_cpu_vector_enabled(CPURISCVState *env); 376 bool riscv_cpu_virt_enabled(CPURISCVState *env); 377 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 378 bool riscv_cpu_two_stage_lookup(int mmu_idx); 379 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); 380 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 381 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 382 MMUAccessType access_type, int mmu_idx, 383 uintptr_t retaddr) QEMU_NORETURN; 384 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 385 MMUAccessType access_type, int mmu_idx, 386 bool probe, uintptr_t retaddr); 387 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 388 vaddr addr, unsigned size, 389 MMUAccessType access_type, 390 int mmu_idx, MemTxAttrs attrs, 391 MemTxResult response, uintptr_t retaddr); 392 char *riscv_isa_string(RISCVCPU *cpu); 393 void riscv_cpu_list(void); 394 395 #define cpu_list riscv_cpu_list 396 #define cpu_mmu_index riscv_cpu_mmu_index 397 398 #ifndef CONFIG_USER_ONLY 399 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 400 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 401 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); 402 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value); 403 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 404 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), 405 uint32_t arg); 406 #endif 407 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); 408 409 void riscv_translate_init(void); 410 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env, 411 uint32_t exception, uintptr_t pc); 412 413 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 414 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 415 416 #define TB_FLAGS_PRIV_MMU_MASK 3 417 #define TB_FLAGS_PRIV_HYP_ACCESS_MASK (1 << 2) 418 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS 419 #define TB_FLAGS_MSTATUS_VS MSTATUS_VS 420 421 typedef CPURISCVState CPUArchState; 422 typedef RISCVCPU ArchCPU; 423 #include "exec/cpu-all.h" 424 425 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 426 FIELD(TB_FLAGS, LMUL, 3, 3) 427 FIELD(TB_FLAGS, SEW, 6, 3) 428 /* Skip MSTATUS_VS (0x600) bits */ 429 FIELD(TB_FLAGS, VL_EQ_VLMAX, 11, 1) 430 FIELD(TB_FLAGS, VILL, 12, 1) 431 /* Skip MSTATUS_FS (0x6000) bits */ 432 /* Is a Hypervisor instruction load/store allowed? */ 433 FIELD(TB_FLAGS, HLSX, 15, 1) 434 FIELD(TB_FLAGS, MSTATUS_HS_FS, 16, 2) 435 FIELD(TB_FLAGS, MSTATUS_HS_VS, 18, 2) 436 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 437 FIELD(TB_FLAGS, XL, 20, 2) 438 /* If PointerMasking should be applied */ 439 FIELD(TB_FLAGS, PM_ENABLED, 22, 1) 440 441 #ifdef TARGET_RISCV32 442 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 443 #else 444 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 445 { 446 return env->misa_mxl; 447 } 448 #endif 449 450 /* 451 * Encode LMUL to lmul as follows: 452 * LMUL vlmul lmul 453 * 1 000 0 454 * 2 001 1 455 * 4 010 2 456 * 8 011 3 457 * - 100 - 458 * 1/8 101 -3 459 * 1/4 110 -2 460 * 1/2 111 -1 461 * 462 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 463 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 464 * => VLMAX = vlen >> (1 + 3 - (-3)) 465 * = 256 >> 7 466 * = 2 467 */ 468 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype) 469 { 470 uint8_t sew = FIELD_EX64(vtype, VTYPE, VSEW); 471 int8_t lmul = sextract32(FIELD_EX64(vtype, VTYPE, VLMUL), 0, 3); 472 return cpu->cfg.vlen >> (sew + 3 - lmul); 473 } 474 475 void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, 476 target_ulong *cs_base, uint32_t *pflags); 477 478 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 479 target_ulong *ret_value, 480 target_ulong new_value, target_ulong write_mask); 481 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 482 target_ulong *ret_value, 483 target_ulong new_value, 484 target_ulong write_mask); 485 486 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 487 target_ulong val) 488 { 489 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 490 } 491 492 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 493 { 494 target_ulong val = 0; 495 riscv_csrrw(env, csrno, &val, 0, 0); 496 return val; 497 } 498 499 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 500 int csrno); 501 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 502 target_ulong *ret_value); 503 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 504 target_ulong new_value); 505 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 506 target_ulong *ret_value, 507 target_ulong new_value, 508 target_ulong write_mask); 509 510 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 511 Int128 *ret_value, 512 Int128 new_value, Int128 write_mask); 513 514 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 515 Int128 *ret_value); 516 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 517 Int128 new_value); 518 519 typedef struct { 520 const char *name; 521 riscv_csr_predicate_fn predicate; 522 riscv_csr_read_fn read; 523 riscv_csr_write_fn write; 524 riscv_csr_op_fn op; 525 riscv_csr_read128_fn read128; 526 riscv_csr_write128_fn write128; 527 } riscv_csr_operations; 528 529 /* CSR function table constants */ 530 enum { 531 CSR_TABLE_SIZE = 0x1000 532 }; 533 534 /* CSR function table */ 535 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 536 537 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 538 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 539 540 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 541 542 #endif /* RISCV_CPU_H */ 543