1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef RISCV_CPU_H 21 #define RISCV_CPU_H 22 23 #include "hw/core/cpu.h" 24 #include "hw/registerfields.h" 25 #include "hw/qdev-properties.h" 26 #include "exec/cpu-common.h" 27 #include "exec/cpu-defs.h" 28 #include "exec/cpu-interrupt.h" 29 #include "exec/gdbstub.h" 30 #include "qemu/cpu-float.h" 31 #include "qom/object.h" 32 #include "qemu/int128.h" 33 #include "cpu_bits.h" 34 #include "cpu_cfg.h" 35 #include "qapi/qapi-types-common.h" 36 #include "cpu-qom.h" 37 38 typedef struct CPUArchState CPURISCVState; 39 40 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 41 42 #if defined(TARGET_RISCV32) 43 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 44 #elif defined(TARGET_RISCV64) 45 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 46 #endif 47 48 /* 49 * RISC-V-specific extra insn start words: 50 * 1: Original instruction opcode 51 * 2: more information about instruction 52 */ 53 #define TARGET_INSN_START_EXTRA_WORDS 2 54 /* 55 * b0: Whether a instruction always raise a store AMO or not. 56 */ 57 #define RISCV_UW2_ALWAYS_STORE_AMO 1 58 59 #define RV(x) ((target_ulong)1 << (x - 'A')) 60 61 /* 62 * Update misa_bits[], misa_ext_info_arr[] and misa_ext_cfgs[] 63 * when adding new MISA bits here. 64 */ 65 #define RVI RV('I') 66 #define RVE RV('E') /* E and I are mutually exclusive */ 67 #define RVM RV('M') 68 #define RVA RV('A') 69 #define RVF RV('F') 70 #define RVD RV('D') 71 #define RVV RV('V') 72 #define RVC RV('C') 73 #define RVS RV('S') 74 #define RVU RV('U') 75 #define RVH RV('H') 76 #define RVG RV('G') 77 #define RVB RV('B') 78 79 extern const uint32_t misa_bits[]; 80 const char *riscv_get_misa_ext_name(uint32_t bit); 81 const char *riscv_get_misa_ext_description(uint32_t bit); 82 83 #define CPU_CFG_OFFSET(_prop) offsetof(struct RISCVCPUConfig, _prop) 84 85 typedef struct riscv_cpu_profile { 86 struct riscv_cpu_profile *u_parent; 87 struct riscv_cpu_profile *s_parent; 88 const char *name; 89 uint32_t misa_ext; 90 bool enabled; 91 bool user_set; 92 int priv_spec; 93 int satp_mode; 94 const int32_t ext_offsets[]; 95 } RISCVCPUProfile; 96 97 #define RISCV_PROFILE_EXT_LIST_END -1 98 #define RISCV_PROFILE_ATTR_UNUSED -1 99 100 extern RISCVCPUProfile *riscv_profiles[]; 101 102 /* Privileged specification version */ 103 #define PRIV_VER_1_10_0_STR "v1.10.0" 104 #define PRIV_VER_1_11_0_STR "v1.11.0" 105 #define PRIV_VER_1_12_0_STR "v1.12.0" 106 #define PRIV_VER_1_13_0_STR "v1.13.0" 107 enum { 108 PRIV_VERSION_1_10_0 = 0, 109 PRIV_VERSION_1_11_0, 110 PRIV_VERSION_1_12_0, 111 PRIV_VERSION_1_13_0, 112 113 PRIV_VERSION_LATEST = PRIV_VERSION_1_13_0, 114 }; 115 116 #define VEXT_VERSION_1_00_0 0x00010000 117 #define VEXT_VER_1_00_0_STR "v1.0" 118 119 enum { 120 TRANSLATE_SUCCESS, 121 TRANSLATE_FAIL, 122 TRANSLATE_PMP_FAIL, 123 TRANSLATE_G_STAGE_FAIL 124 }; 125 126 /* Extension context status */ 127 typedef enum { 128 EXT_STATUS_DISABLED = 0, 129 EXT_STATUS_INITIAL, 130 EXT_STATUS_CLEAN, 131 EXT_STATUS_DIRTY, 132 } RISCVExtStatus; 133 134 /* Enum holds PMM field values for Zjpm v1.0 extension */ 135 typedef enum { 136 PMM_FIELD_DISABLED = 0, 137 PMM_FIELD_RESERVED = 1, 138 PMM_FIELD_PMLEN7 = 2, 139 PMM_FIELD_PMLEN16 = 3, 140 } RISCVPmPmm; 141 142 typedef struct riscv_cpu_implied_exts_rule { 143 #ifndef CONFIG_USER_ONLY 144 /* 145 * Bitmask indicates the rule enabled status for the harts. 146 * This enhancement is only available in system-mode QEMU, 147 * as we don't have a good way (e.g. mhartid) to distinguish 148 * the SMP cores in user-mode QEMU. 149 */ 150 unsigned long *enabled; 151 #endif 152 /* True if this is a MISA implied rule. */ 153 bool is_misa; 154 /* ext is MISA bit if is_misa flag is true, else multi extension offset. */ 155 const uint32_t ext; 156 const uint32_t implied_misa_exts; 157 const uint32_t implied_multi_exts[]; 158 } RISCVCPUImpliedExtsRule; 159 160 extern RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[]; 161 extern RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[]; 162 163 #define RISCV_IMPLIED_EXTS_RULE_END -1 164 165 #define MMU_USER_IDX 3 166 167 #define MAX_RISCV_PMPS (16) 168 169 #if !defined(CONFIG_USER_ONLY) 170 #include "pmp.h" 171 #include "debug.h" 172 #endif 173 174 #define RV_VLEN_MAX 1024 175 #define RV_MAX_MHPMEVENTS 32 176 #define RV_MAX_MHPMCOUNTERS 32 177 178 FIELD(VTYPE, VLMUL, 0, 3) 179 FIELD(VTYPE, VSEW, 3, 3) 180 FIELD(VTYPE, VTA, 6, 1) 181 FIELD(VTYPE, VMA, 7, 1) 182 FIELD(VTYPE, VEDIV, 8, 2) 183 FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) 184 185 typedef struct PMUCTRState { 186 /* Current value of a counter */ 187 target_ulong mhpmcounter_val; 188 /* Current value of a counter in RV32 */ 189 target_ulong mhpmcounterh_val; 190 /* Snapshot values of counter */ 191 target_ulong mhpmcounter_prev; 192 /* Snapshort value of a counter in RV32 */ 193 target_ulong mhpmcounterh_prev; 194 /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ 195 target_ulong irq_overflow_left; 196 } PMUCTRState; 197 198 typedef struct PMUFixedCtrState { 199 /* Track cycle and icount for each privilege mode */ 200 uint64_t counter[4]; 201 uint64_t counter_prev[4]; 202 /* Track cycle and icount for each privilege mode when V = 1*/ 203 uint64_t counter_virt[2]; 204 uint64_t counter_virt_prev[2]; 205 } PMUFixedCtrState; 206 207 struct CPUArchState { 208 target_ulong gpr[32]; 209 target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ 210 211 /* vector coprocessor state. */ 212 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16); 213 target_ulong vxrm; 214 target_ulong vxsat; 215 target_ulong vl; 216 target_ulong vstart; 217 target_ulong vtype; 218 bool vill; 219 220 target_ulong pc; 221 target_ulong load_res; 222 target_ulong load_val; 223 224 /* Floating-Point state */ 225 uint64_t fpr[32]; /* assume both F and D extensions */ 226 target_ulong frm; 227 float_status fp_status; 228 229 target_ulong badaddr; 230 target_ulong bins; 231 232 target_ulong guest_phys_fault_addr; 233 234 target_ulong priv_ver; 235 target_ulong vext_ver; 236 237 /* RISCVMXL, but uint32_t for vmstate migration */ 238 uint32_t misa_mxl; /* current mxl */ 239 uint32_t misa_ext; /* current extensions */ 240 uint32_t misa_ext_mask; /* max ext for this cpu */ 241 uint32_t xl; /* current xlen */ 242 243 /* 128-bit helpers upper part return value */ 244 target_ulong retxh; 245 246 target_ulong jvt; 247 248 /* elp state for zicfilp extension */ 249 bool elp; 250 /* shadow stack register for zicfiss extension */ 251 target_ulong ssp; 252 /* env place holder for extra word 2 during unwind */ 253 target_ulong excp_uw2; 254 /* sw check code for sw check exception */ 255 target_ulong sw_check_code; 256 #ifdef CONFIG_USER_ONLY 257 uint32_t elf_flags; 258 #endif 259 260 target_ulong priv; 261 /* CSRs for execution environment configuration */ 262 uint64_t menvcfg; 263 target_ulong senvcfg; 264 265 #ifndef CONFIG_USER_ONLY 266 /* This contains QEMU specific information about the virt state. */ 267 bool virt_enabled; 268 target_ulong geilen; 269 uint64_t resetvec; 270 271 target_ulong mhartid; 272 /* 273 * For RV32 this is 32-bit mstatus and 32-bit mstatush. 274 * For RV64 this is a 64-bit mstatus. 275 */ 276 uint64_t mstatus; 277 278 uint64_t mip; 279 /* 280 * MIP contains the software writable version of SEIP ORed with the 281 * external interrupt value. The MIP register is always up-to-date. 282 * To keep track of the current source, we also save booleans of the values 283 * here. 284 */ 285 bool external_seip; 286 bool software_seip; 287 288 uint64_t miclaim; 289 290 uint64_t mie; 291 uint64_t mideleg; 292 293 /* 294 * When mideleg[i]=0 and mvien[i]=1, sie[i] is no more 295 * alias of mie[i] and needs to be maintained separately. 296 */ 297 uint64_t sie; 298 299 /* 300 * When hideleg[i]=0 and hvien[i]=1, vsie[i] is no more 301 * alias of sie[i] (mie[i]) and needs to be maintained separately. 302 */ 303 uint64_t vsie; 304 305 target_ulong satp; /* since: priv-1.10.0 */ 306 target_ulong stval; 307 target_ulong medeleg; 308 309 target_ulong stvec; 310 target_ulong sepc; 311 target_ulong scause; 312 313 target_ulong mtvec; 314 target_ulong mepc; 315 target_ulong mcause; 316 target_ulong mtval; /* since: priv-1.10.0 */ 317 318 uint64_t mctrctl; 319 uint32_t sctrdepth; 320 uint32_t sctrstatus; 321 uint64_t vsctrctl; 322 323 uint64_t ctr_src[16 << SCTRDEPTH_MAX]; 324 uint64_t ctr_dst[16 << SCTRDEPTH_MAX]; 325 uint64_t ctr_data[16 << SCTRDEPTH_MAX]; 326 327 /* Machine and Supervisor interrupt priorities */ 328 uint8_t miprio[64]; 329 uint8_t siprio[64]; 330 331 /* AIA CSRs */ 332 target_ulong miselect; 333 target_ulong siselect; 334 uint64_t mvien; 335 uint64_t mvip; 336 337 /* Hypervisor CSRs */ 338 target_ulong hstatus; 339 target_ulong hedeleg; 340 uint64_t hideleg; 341 uint32_t hcounteren; 342 target_ulong htval; 343 target_ulong htinst; 344 target_ulong hgatp; 345 target_ulong hgeie; 346 target_ulong hgeip; 347 uint64_t htimedelta; 348 uint64_t hvien; 349 350 /* 351 * Bits VSSIP, VSTIP and VSEIP in hvip are maintained in mip. Other bits 352 * from 0:12 are reserved. Bits 13:63 are not aliased and must be separately 353 * maintain in hvip. 354 */ 355 uint64_t hvip; 356 357 /* Hypervisor controlled virtual interrupt priorities */ 358 target_ulong hvictl; 359 uint8_t hviprio[64]; 360 361 /* Upper 64-bits of 128-bit CSRs */ 362 uint64_t mscratchh; 363 uint64_t sscratchh; 364 365 /* Virtual CSRs */ 366 /* 367 * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. 368 * For RV64 this is a 64-bit vsstatus. 369 */ 370 uint64_t vsstatus; 371 target_ulong vstvec; 372 target_ulong vsscratch; 373 target_ulong vsepc; 374 target_ulong vscause; 375 target_ulong vstval; 376 target_ulong vsatp; 377 378 /* AIA VS-mode CSRs */ 379 target_ulong vsiselect; 380 381 target_ulong mtval2; 382 target_ulong mtinst; 383 384 /* HS Backup CSRs */ 385 target_ulong stvec_hs; 386 target_ulong sscratch_hs; 387 target_ulong sepc_hs; 388 target_ulong scause_hs; 389 target_ulong stval_hs; 390 target_ulong satp_hs; 391 uint64_t mstatus_hs; 392 393 /* 394 * Signals whether the current exception occurred with two-stage address 395 * translation active. 396 */ 397 bool two_stage_lookup; 398 /* 399 * Signals whether the current exception occurred while doing two-stage 400 * address translation for the VS-stage page table walk. 401 */ 402 bool two_stage_indirect_lookup; 403 404 uint32_t scounteren; 405 uint32_t mcounteren; 406 407 uint32_t scountinhibit; 408 uint32_t mcountinhibit; 409 410 /* PMU cycle & instret privilege mode filtering */ 411 target_ulong mcyclecfg; 412 target_ulong mcyclecfgh; 413 target_ulong minstretcfg; 414 target_ulong minstretcfgh; 415 416 /* PMU counter state */ 417 PMUCTRState pmu_ctrs[RV_MAX_MHPMCOUNTERS]; 418 419 /* PMU event selector configured values. First three are unused */ 420 target_ulong mhpmevent_val[RV_MAX_MHPMEVENTS]; 421 422 /* PMU event selector configured values for RV32 */ 423 target_ulong mhpmeventh_val[RV_MAX_MHPMEVENTS]; 424 425 PMUFixedCtrState pmu_fixed_ctrs[2]; 426 427 target_ulong sscratch; 428 target_ulong mscratch; 429 430 /* Sstc CSRs */ 431 uint64_t stimecmp; 432 433 uint64_t vstimecmp; 434 435 /* physical memory protection */ 436 pmp_table_t pmp_state; 437 target_ulong mseccfg; 438 439 /* trigger module */ 440 target_ulong trigger_cur; 441 target_ulong tdata1[RV_MAX_TRIGGERS]; 442 target_ulong tdata2[RV_MAX_TRIGGERS]; 443 target_ulong tdata3[RV_MAX_TRIGGERS]; 444 target_ulong mcontext; 445 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS]; 446 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS]; 447 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS]; 448 int64_t last_icount; 449 bool itrigger_enabled; 450 451 /* machine specific rdtime callback */ 452 uint64_t (*rdtime_fn)(void *); 453 void *rdtime_fn_arg; 454 455 /* machine specific AIA ireg read-modify-write callback */ 456 #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ 457 ((((__xlen) & 0xff) << 24) | \ 458 (((__vgein) & 0x3f) << 20) | \ 459 (((__virt) & 0x1) << 18) | \ 460 (((__priv) & 0x3) << 16) | \ 461 (__isel & 0xffff)) 462 #define AIA_IREG_ISEL(__ireg) ((__ireg) & 0xffff) 463 #define AIA_IREG_PRIV(__ireg) (((__ireg) >> 16) & 0x3) 464 #define AIA_IREG_VIRT(__ireg) (((__ireg) >> 18) & 0x1) 465 #define AIA_IREG_VGEIN(__ireg) (((__ireg) >> 20) & 0x3f) 466 #define AIA_IREG_XLEN(__ireg) (((__ireg) >> 24) & 0xff) 467 int (*aia_ireg_rmw_fn[4])(void *arg, target_ulong reg, 468 target_ulong *val, target_ulong new_val, target_ulong write_mask); 469 void *aia_ireg_rmw_fn_arg[4]; 470 471 /* True if in debugger mode. */ 472 bool debugger; 473 474 uint64_t mstateen[SMSTATEEN_MAX_COUNT]; 475 uint64_t hstateen[SMSTATEEN_MAX_COUNT]; 476 uint64_t sstateen[SMSTATEEN_MAX_COUNT]; 477 uint64_t henvcfg; 478 #endif 479 480 /* Fields from here on are preserved across CPU reset. */ 481 QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ 482 QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ 483 bool vstime_irq; 484 485 hwaddr kernel_addr; 486 hwaddr fdt_addr; 487 488 #ifdef CONFIG_KVM 489 /* kvm timer */ 490 bool kvm_timer_dirty; 491 uint64_t kvm_timer_time; 492 uint64_t kvm_timer_compare; 493 uint64_t kvm_timer_state; 494 uint64_t kvm_timer_frequency; 495 #endif /* CONFIG_KVM */ 496 497 /* RNMI */ 498 target_ulong mnscratch; 499 target_ulong mnepc; 500 target_ulong mncause; /* mncause without bit XLEN-1 set to 1 */ 501 target_ulong mnstatus; 502 target_ulong rnmip; 503 uint64_t rnmi_irqvec; 504 uint64_t rnmi_excpvec; 505 }; 506 507 /* 508 * RISCVCPU: 509 * @env: #CPURISCVState 510 * 511 * A RISCV CPU. 512 */ 513 struct ArchCPU { 514 CPUState parent_obj; 515 516 CPURISCVState env; 517 518 GDBFeature dyn_csr_feature; 519 GDBFeature dyn_vreg_feature; 520 521 /* Configuration Settings */ 522 RISCVCPUConfig cfg; 523 524 QEMUTimer *pmu_timer; 525 /* A bitmask of Available programmable counters */ 526 uint32_t pmu_avail_ctrs; 527 /* Mapping of events to counters */ 528 GHashTable *pmu_event_ctr_map; 529 const GPtrArray *decoders; 530 }; 531 532 /** 533 * RISCVCPUClass: 534 * @parent_realize: The parent class' realize handler. 535 * @parent_phases: The parent class' reset phase handlers. 536 * 537 * A RISCV CPU model. 538 */ 539 struct RISCVCPUClass { 540 CPUClass parent_class; 541 542 DeviceRealize parent_realize; 543 ResettablePhases parent_phases; 544 RISCVMXL misa_mxl_max; /* max mxl for this cpu */ 545 }; 546 547 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) 548 { 549 return (env->misa_ext & ext) != 0; 550 } 551 552 #include "cpu_user.h" 553 554 extern const char * const riscv_int_regnames[]; 555 extern const char * const riscv_int_regnamesh[]; 556 extern const char * const riscv_fpr_regnames[]; 557 558 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async); 559 int riscv_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, 560 int cpuid, DumpState *s); 561 int riscv_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs, 562 int cpuid, DumpState *s); 563 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); 564 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); 565 int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); 566 uint8_t riscv_cpu_default_priority(int irq); 567 uint64_t riscv_cpu_all_pending(CPURISCVState *env); 568 int riscv_cpu_mirq_pending(CPURISCVState *env); 569 int riscv_cpu_sirq_pending(CPURISCVState *env); 570 int riscv_cpu_vsirq_pending(CPURISCVState *env); 571 bool riscv_cpu_fp_enabled(CPURISCVState *env); 572 target_ulong riscv_cpu_get_geilen(CPURISCVState *env); 573 void riscv_cpu_set_geilen(CPURISCVState *env, target_ulong geilen); 574 bool riscv_cpu_vector_enabled(CPURISCVState *env); 575 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable); 576 int riscv_env_mmu_index(CPURISCVState *env, bool ifetch); 577 bool cpu_get_fcfien(CPURISCVState *env); 578 bool cpu_get_bcfien(CPURISCVState *env); 579 bool riscv_env_smode_dbltrp_enabled(CPURISCVState *env, bool virt); 580 G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, 581 MMUAccessType access_type, 582 int mmu_idx, uintptr_t retaddr); 583 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, 584 MMUAccessType access_type, int mmu_idx, 585 bool probe, uintptr_t retaddr); 586 char *riscv_isa_string(RISCVCPU *cpu); 587 int riscv_cpu_max_xlen(RISCVCPUClass *mcc); 588 bool riscv_cpu_option_set(const char *optname); 589 590 #ifndef CONFIG_USER_ONLY 591 void riscv_cpu_do_interrupt(CPUState *cpu); 592 void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename); 593 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, 594 vaddr addr, unsigned size, 595 MMUAccessType access_type, 596 int mmu_idx, MemTxAttrs attrs, 597 MemTxResult response, uintptr_t retaddr); 598 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 599 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); 600 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); 601 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); 602 uint64_t riscv_cpu_update_mip(CPURISCVState *env, uint64_t mask, 603 uint64_t value); 604 void riscv_cpu_set_rnmi(RISCVCPU *cpu, uint32_t irq, bool level); 605 void riscv_cpu_interrupt(CPURISCVState *env); 606 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */ 607 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), 608 void *arg); 609 void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, 610 int (*rmw_fn)(void *arg, 611 target_ulong reg, 612 target_ulong *val, 613 target_ulong new_val, 614 target_ulong write_mask), 615 void *rmw_fn_arg); 616 617 RISCVException smstateen_acc_ok(CPURISCVState *env, int index, uint64_t bit); 618 #endif /* !CONFIG_USER_ONLY */ 619 620 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv, bool virt_en); 621 622 void riscv_ctr_add_entry(CPURISCVState *env, target_long src, target_long dst, 623 enum CTRType type, target_ulong prev_priv, bool prev_virt); 624 void riscv_ctr_clear(CPURISCVState *env); 625 626 void riscv_translate_init(void); 627 void riscv_translate_code(CPUState *cs, TranslationBlock *tb, 628 int *max_insns, vaddr pc, void *host_pc); 629 630 G_NORETURN void riscv_raise_exception(CPURISCVState *env, 631 RISCVException exception, 632 uintptr_t pc); 633 634 target_ulong riscv_cpu_get_fflags(CPURISCVState *env); 635 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong); 636 637 FIELD(TB_FLAGS, MEM_IDX, 0, 3) 638 FIELD(TB_FLAGS, FS, 3, 2) 639 /* Vector flags */ 640 FIELD(TB_FLAGS, VS, 5, 2) 641 FIELD(TB_FLAGS, LMUL, 7, 3) 642 FIELD(TB_FLAGS, SEW, 10, 3) 643 FIELD(TB_FLAGS, VL_EQ_VLMAX, 13, 1) 644 FIELD(TB_FLAGS, VILL, 14, 1) 645 FIELD(TB_FLAGS, VSTART_EQ_ZERO, 15, 1) 646 /* The combination of MXL/SXL/UXL that applies to the current cpu mode. */ 647 FIELD(TB_FLAGS, XL, 16, 2) 648 /* If PointerMasking should be applied */ 649 FIELD(TB_FLAGS, PM_MASK_ENABLED, 18, 1) 650 FIELD(TB_FLAGS, PM_BASE_ENABLED, 19, 1) 651 FIELD(TB_FLAGS, VTA, 18, 1) 652 FIELD(TB_FLAGS, VMA, 19, 1) 653 /* Native debug itrigger */ 654 FIELD(TB_FLAGS, ITRIGGER, 20, 1) 655 /* Virtual mode enabled */ 656 FIELD(TB_FLAGS, VIRT_ENABLED, 21, 1) 657 FIELD(TB_FLAGS, PRIV, 22, 2) 658 FIELD(TB_FLAGS, AXL, 24, 2) 659 /* zicfilp needs a TB flag to track indirect branches */ 660 FIELD(TB_FLAGS, FCFI_ENABLED, 26, 1) 661 FIELD(TB_FLAGS, FCFI_LP_EXPECTED, 27, 1) 662 /* zicfiss needs a TB flag so that correct TB is located based on tb flags */ 663 FIELD(TB_FLAGS, BCFI_ENABLED, 28, 1) 664 /* If pointer masking should be applied and address sign extended */ 665 FIELD(TB_FLAGS, PM_PMM, 29, 2) 666 FIELD(TB_FLAGS, PM_SIGNEXTEND, 31, 1) 667 668 #ifdef TARGET_RISCV32 669 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) 670 #else 671 static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) 672 { 673 return env->misa_mxl; 674 } 675 #endif 676 #define riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env))) 677 678 static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) 679 { 680 return &env_archcpu(env)->cfg; 681 } 682 683 #if !defined(CONFIG_USER_ONLY) 684 static inline int cpu_address_mode(CPURISCVState *env) 685 { 686 int mode = env->priv; 687 688 if (mode == PRV_M && get_field(env->mstatus, MSTATUS_MPRV)) { 689 mode = get_field(env->mstatus, MSTATUS_MPP); 690 } 691 return mode; 692 } 693 694 static inline RISCVMXL cpu_get_xl(CPURISCVState *env, target_ulong mode) 695 { 696 RISCVMXL xl = env->misa_mxl; 697 /* 698 * When emulating a 32-bit-only cpu, use RV32. 699 * When emulating a 64-bit cpu, and MXL has been reduced to RV32, 700 * MSTATUSH doesn't have UXL/SXL, therefore XLEN cannot be widened 701 * back to RV64 for lower privs. 702 */ 703 if (xl != MXL_RV32) { 704 switch (mode) { 705 case PRV_M: 706 break; 707 case PRV_U: 708 xl = get_field(env->mstatus, MSTATUS64_UXL); 709 break; 710 default: /* PRV_S */ 711 xl = get_field(env->mstatus, MSTATUS64_SXL); 712 break; 713 } 714 } 715 return xl; 716 } 717 #endif 718 719 #if defined(TARGET_RISCV32) 720 #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) 721 #else 722 static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) 723 { 724 #if !defined(CONFIG_USER_ONLY) 725 return cpu_get_xl(env, env->priv); 726 #else 727 return env->misa_mxl; 728 #endif 729 } 730 #endif 731 732 #if defined(TARGET_RISCV32) 733 #define cpu_address_xl(env) ((void)(env), MXL_RV32) 734 #else 735 static inline RISCVMXL cpu_address_xl(CPURISCVState *env) 736 { 737 #ifdef CONFIG_USER_ONLY 738 return env->xl; 739 #else 740 int mode = cpu_address_mode(env); 741 742 return cpu_get_xl(env, mode); 743 #endif 744 } 745 #endif 746 747 static inline int riscv_cpu_xlen(CPURISCVState *env) 748 { 749 return 16 << env->xl; 750 } 751 752 #ifdef TARGET_RISCV32 753 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) 754 #else 755 static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) 756 { 757 #ifdef CONFIG_USER_ONLY 758 return env->misa_mxl; 759 #else 760 if (env->misa_mxl != MXL_RV32) { 761 return get_field(env->mstatus, MSTATUS64_SXL); 762 } 763 #endif 764 return MXL_RV32; 765 } 766 #endif 767 768 static inline bool riscv_cpu_allow_16bit_insn(const RISCVCPUConfig *cfg, 769 target_long priv_ver, 770 uint32_t misa_ext) 771 { 772 /* In priv spec version 1.12 or newer, C always implies Zca */ 773 if (priv_ver >= PRIV_VERSION_1_12_0) { 774 return cfg->ext_zca; 775 } else { 776 return misa_ext & RVC; 777 } 778 } 779 780 /* 781 * Encode LMUL to lmul as follows: 782 * LMUL vlmul lmul 783 * 1 000 0 784 * 2 001 1 785 * 4 010 2 786 * 8 011 3 787 * - 100 - 788 * 1/8 101 -3 789 * 1/4 110 -2 790 * 1/2 111 -1 791 * 792 * then, we can calculate VLMAX = vlen >> (vsew + 3 - lmul) 793 * e.g. vlen = 256 bits, SEW = 16, LMUL = 1/8 794 * => VLMAX = vlen >> (1 + 3 - (-3)) 795 * = 256 >> 7 796 * = 2 797 */ 798 static inline uint32_t vext_get_vlmax(uint32_t vlenb, uint32_t vsew, 799 int8_t lmul) 800 { 801 uint32_t vlen = vlenb << 3; 802 803 /* 804 * We need to use 'vlen' instead of 'vlenb' to 805 * preserve the '+ 3' in the formula. Otherwise 806 * we risk a negative shift if vsew < lmul. 807 */ 808 return vlen >> (vsew + 3 - lmul); 809 } 810 811 void cpu_get_tb_cpu_state(CPURISCVState *env, vaddr *pc, 812 uint64_t *cs_base, uint32_t *pflags); 813 814 bool riscv_cpu_is_32bit(RISCVCPU *cpu); 815 816 bool riscv_cpu_virt_mem_enabled(CPURISCVState *env); 817 RISCVPmPmm riscv_pm_get_pmm(CPURISCVState *env); 818 RISCVPmPmm riscv_pm_get_virt_pmm(CPURISCVState *env); 819 uint32_t riscv_pm_get_pmlen(RISCVPmPmm pmm); 820 821 RISCVException riscv_csrr(CPURISCVState *env, int csrno, 822 target_ulong *ret_value); 823 824 RISCVException riscv_csrrw(CPURISCVState *env, int csrno, 825 target_ulong *ret_value, 826 target_ulong new_value, target_ulong write_mask); 827 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno, 828 target_ulong *ret_value, 829 target_ulong new_value, 830 target_ulong write_mask); 831 832 static inline void riscv_csr_write(CPURISCVState *env, int csrno, 833 target_ulong val) 834 { 835 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS)); 836 } 837 838 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) 839 { 840 target_ulong val = 0; 841 riscv_csrrw(env, csrno, &val, 0, 0); 842 return val; 843 } 844 845 typedef RISCVException (*riscv_csr_predicate_fn)(CPURISCVState *env, 846 int csrno); 847 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno, 848 target_ulong *ret_value); 849 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno, 850 target_ulong new_value); 851 typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState *env, int csrno, 852 target_ulong *ret_value, 853 target_ulong new_value, 854 target_ulong write_mask); 855 856 RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno, 857 Int128 *ret_value); 858 RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno, 859 Int128 *ret_value, 860 Int128 new_value, Int128 write_mask); 861 862 typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno, 863 Int128 *ret_value); 864 typedef RISCVException (*riscv_csr_write128_fn)(CPURISCVState *env, int csrno, 865 Int128 new_value); 866 867 typedef struct { 868 const char *name; 869 riscv_csr_predicate_fn predicate; 870 riscv_csr_read_fn read; 871 riscv_csr_write_fn write; 872 riscv_csr_op_fn op; 873 riscv_csr_read128_fn read128; 874 riscv_csr_write128_fn write128; 875 /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0) */ 876 uint32_t min_priv_ver; 877 } riscv_csr_operations; 878 879 /* CSR function table constants */ 880 enum { 881 CSR_TABLE_SIZE = 0x1000 882 }; 883 884 /* 885 * The event id are encoded based on the encoding specified in the 886 * SBI specification v0.3 887 */ 888 889 enum riscv_pmu_event_idx { 890 RISCV_PMU_EVENT_HW_CPU_CYCLES = 0x01, 891 RISCV_PMU_EVENT_HW_INSTRUCTIONS = 0x02, 892 RISCV_PMU_EVENT_CACHE_DTLB_READ_MISS = 0x10019, 893 RISCV_PMU_EVENT_CACHE_DTLB_WRITE_MISS = 0x1001B, 894 RISCV_PMU_EVENT_CACHE_ITLB_PREFETCH_MISS = 0x10021, 895 }; 896 897 /* used by tcg/tcg-cpu.c*/ 898 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en); 899 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset); 900 void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext); 901 bool riscv_cpu_is_vendor(Object *cpu_obj); 902 903 typedef struct RISCVCPUMultiExtConfig { 904 const char *name; 905 uint32_t offset; 906 bool enabled; 907 } RISCVCPUMultiExtConfig; 908 909 extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; 910 extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; 911 extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; 912 extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; 913 extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; 914 915 typedef struct isa_ext_data { 916 const char *name; 917 int min_version; 918 int ext_enable_offset; 919 } RISCVIsaExtData; 920 extern const RISCVIsaExtData isa_edata_arr[]; 921 char *riscv_cpu_get_name(RISCVCPU *cpu); 922 923 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp); 924 void riscv_add_satp_mode_properties(Object *obj); 925 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu); 926 927 /* CSR function table */ 928 extern riscv_csr_operations csr_ops[CSR_TABLE_SIZE]; 929 930 extern const bool valid_vm_1_10_32[], valid_vm_1_10_64[]; 931 932 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops); 933 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops); 934 935 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs); 936 937 target_ulong riscv_new_csr_seed(target_ulong new_value, 938 target_ulong write_mask); 939 940 uint8_t satp_mode_max_from_map(uint32_t map); 941 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit); 942 943 /* Implemented in th_csr.c */ 944 void th_register_custom_csrs(RISCVCPU *cpu); 945 946 const char *priv_spec_to_str(int priv_version); 947 #endif /* RISCV_CPU_H */ 948