1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "internals.h" 27 #include "exec/exec-all.h" 28 #include "qapi/error.h" 29 #include "qapi/visitor.h" 30 #include "qemu/error-report.h" 31 #include "hw/qdev-properties.h" 32 #include "migration/vmstate.h" 33 #include "fpu/softfloat-helpers.h" 34 #include "sysemu/kvm.h" 35 #include "sysemu/tcg.h" 36 #include "kvm/kvm_riscv.h" 37 #include "tcg/tcg.h" 38 39 /* RISC-V CPU definitions */ 40 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 41 42 struct isa_ext_data { 43 const char *name; 44 int min_version; 45 int ext_enable_offset; 46 }; 47 48 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ 49 {#_name, _min_ver, CPU_CFG_OFFSET(_prop)} 50 51 /* 52 * From vector_helper.c 53 * Note that vector data is stored in host-endian 64-bit chunks, 54 * so addressing bytes needs a host-endian fixup. 55 */ 56 #if HOST_BIG_ENDIAN 57 #define BYTE(x) ((x) ^ 7) 58 #else 59 #define BYTE(x) (x) 60 #endif 61 62 /* 63 * Here are the ordering rules of extension naming defined by RISC-V 64 * specification : 65 * 1. All extensions should be separated from other multi-letter extensions 66 * by an underscore. 67 * 2. The first letter following the 'Z' conventionally indicates the most 68 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 69 * If multiple 'Z' extensions are named, they should be ordered first 70 * by category, then alphabetically within a category. 71 * 3. Standard supervisor-level extensions (starts with 'S') should be 72 * listed after standard unprivileged extensions. If multiple 73 * supervisor-level extensions are listed, they should be ordered 74 * alphabetically. 75 * 4. Non-standard extensions (starts with 'X') must be listed after all 76 * standard extensions. They must be separated from other multi-letter 77 * extensions by an underscore. 78 * 79 * Single letter extensions are checked in riscv_cpu_validate_misa_priv() 80 * instead. 81 */ 82 static const struct isa_ext_data isa_edata_arr[] = { 83 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), 84 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), 85 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), 86 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), 87 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), 88 ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl), 89 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), 90 ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), 91 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), 92 ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), 93 ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin), 94 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), 95 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), 96 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), 97 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), 98 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), 99 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), 100 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), 101 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), 102 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), 103 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), 104 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), 105 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), 106 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), 107 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), 108 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), 109 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), 110 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), 111 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), 112 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), 113 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), 114 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), 115 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), 116 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), 117 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), 118 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), 119 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), 120 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), 121 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), 122 ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb), 123 ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), 124 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), 125 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), 126 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), 127 ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin), 128 ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), 129 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), 130 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), 131 ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg), 132 ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned), 133 ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), 134 ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), 135 ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), 136 ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), 137 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), 138 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), 139 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), 140 ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp), 141 ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), 142 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), 143 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), 144 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), 145 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), 146 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), 147 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), 148 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), 149 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), 150 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), 151 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), 152 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), 153 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 154 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 155 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), 156 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), 157 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 158 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), 159 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), 160 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 161 }; 162 163 /* Hash that stores user set extensions */ 164 static GHashTable *multi_ext_user_opts; 165 166 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) 167 { 168 bool *ext_enabled = (void *)&cpu->cfg + ext_offset; 169 170 return *ext_enabled; 171 } 172 173 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en) 174 { 175 bool *ext_enabled = (void *)&cpu->cfg + ext_offset; 176 177 *ext_enabled = en; 178 } 179 180 int cpu_cfg_ext_get_min_version(uint32_t ext_offset) 181 { 182 int i; 183 184 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 185 if (isa_edata_arr[i].ext_enable_offset != ext_offset) { 186 continue; 187 } 188 189 return isa_edata_arr[i].min_version; 190 } 191 192 g_assert_not_reached(); 193 } 194 195 bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) 196 { 197 return g_hash_table_contains(multi_ext_user_opts, 198 GUINT_TO_POINTER(ext_offset)); 199 } 200 201 const char * const riscv_int_regnames[] = { 202 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 203 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 204 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 205 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 206 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 207 }; 208 209 const char * const riscv_int_regnamesh[] = { 210 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 211 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 212 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 213 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 214 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 215 "x30h/t5h", "x31h/t6h" 216 }; 217 218 const char * const riscv_fpr_regnames[] = { 219 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 220 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 221 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 222 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 223 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 224 "f30/ft10", "f31/ft11" 225 }; 226 227 const char * const riscv_rvv_regnames[] = { 228 "v0", "v1", "v2", "v3", "v4", "v5", "v6", 229 "v7", "v8", "v9", "v10", "v11", "v12", "v13", 230 "v14", "v15", "v16", "v17", "v18", "v19", "v20", 231 "v21", "v22", "v23", "v24", "v25", "v26", "v27", 232 "v28", "v29", "v30", "v31" 233 }; 234 235 static const char * const riscv_excp_names[] = { 236 "misaligned_fetch", 237 "fault_fetch", 238 "illegal_instruction", 239 "breakpoint", 240 "misaligned_load", 241 "fault_load", 242 "misaligned_store", 243 "fault_store", 244 "user_ecall", 245 "supervisor_ecall", 246 "hypervisor_ecall", 247 "machine_ecall", 248 "exec_page_fault", 249 "load_page_fault", 250 "reserved", 251 "store_page_fault", 252 "reserved", 253 "reserved", 254 "reserved", 255 "reserved", 256 "guest_exec_page_fault", 257 "guest_load_page_fault", 258 "reserved", 259 "guest_store_page_fault", 260 }; 261 262 static const char * const riscv_intr_names[] = { 263 "u_software", 264 "s_software", 265 "vs_software", 266 "m_software", 267 "u_timer", 268 "s_timer", 269 "vs_timer", 270 "m_timer", 271 "u_external", 272 "s_external", 273 "vs_external", 274 "m_external", 275 "reserved", 276 "reserved", 277 "reserved", 278 "reserved" 279 }; 280 281 static void riscv_cpu_add_user_properties(Object *obj); 282 static void riscv_init_max_cpu_extensions(Object *obj); 283 284 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 285 { 286 if (async) { 287 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 288 riscv_intr_names[cause] : "(unknown)"; 289 } else { 290 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 291 riscv_excp_names[cause] : "(unknown)"; 292 } 293 } 294 295 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 296 { 297 env->misa_mxl_max = env->misa_mxl = mxl; 298 env->misa_ext_mask = env->misa_ext = ext; 299 } 300 301 #ifndef CONFIG_USER_ONLY 302 static uint8_t satp_mode_from_str(const char *satp_mode_str) 303 { 304 if (!strncmp(satp_mode_str, "mbare", 5)) { 305 return VM_1_10_MBARE; 306 } 307 308 if (!strncmp(satp_mode_str, "sv32", 4)) { 309 return VM_1_10_SV32; 310 } 311 312 if (!strncmp(satp_mode_str, "sv39", 4)) { 313 return VM_1_10_SV39; 314 } 315 316 if (!strncmp(satp_mode_str, "sv48", 4)) { 317 return VM_1_10_SV48; 318 } 319 320 if (!strncmp(satp_mode_str, "sv57", 4)) { 321 return VM_1_10_SV57; 322 } 323 324 if (!strncmp(satp_mode_str, "sv64", 4)) { 325 return VM_1_10_SV64; 326 } 327 328 g_assert_not_reached(); 329 } 330 331 uint8_t satp_mode_max_from_map(uint32_t map) 332 { 333 /* 334 * 'map = 0' will make us return (31 - 32), which C will 335 * happily overflow to UINT_MAX. There's no good result to 336 * return if 'map = 0' (e.g. returning 0 will be ambiguous 337 * with the result for 'map = 1'). 338 * 339 * Assert out if map = 0. Callers will have to deal with 340 * it outside of this function. 341 */ 342 g_assert(map > 0); 343 344 /* map here has at least one bit set, so no problem with clz */ 345 return 31 - __builtin_clz(map); 346 } 347 348 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) 349 { 350 if (is_32_bit) { 351 switch (satp_mode) { 352 case VM_1_10_SV32: 353 return "sv32"; 354 case VM_1_10_MBARE: 355 return "none"; 356 } 357 } else { 358 switch (satp_mode) { 359 case VM_1_10_SV64: 360 return "sv64"; 361 case VM_1_10_SV57: 362 return "sv57"; 363 case VM_1_10_SV48: 364 return "sv48"; 365 case VM_1_10_SV39: 366 return "sv39"; 367 case VM_1_10_MBARE: 368 return "none"; 369 } 370 } 371 372 g_assert_not_reached(); 373 } 374 375 static void set_satp_mode_max_supported(RISCVCPU *cpu, 376 uint8_t satp_mode) 377 { 378 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 379 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; 380 381 for (int i = 0; i <= satp_mode; ++i) { 382 if (valid_vm[i]) { 383 cpu->cfg.satp_mode.supported |= (1 << i); 384 } 385 } 386 } 387 388 /* Set the satp mode to the max supported */ 389 static void set_satp_mode_default_map(RISCVCPU *cpu) 390 { 391 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; 392 } 393 #endif 394 395 static void riscv_any_cpu_init(Object *obj) 396 { 397 RISCVCPU *cpu = RISCV_CPU(obj); 398 CPURISCVState *env = &cpu->env; 399 #if defined(TARGET_RISCV32) 400 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 401 #elif defined(TARGET_RISCV64) 402 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 403 #endif 404 405 #ifndef CONFIG_USER_ONLY 406 set_satp_mode_max_supported(RISCV_CPU(obj), 407 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? 408 VM_1_10_SV32 : VM_1_10_SV57); 409 #endif 410 411 env->priv_ver = PRIV_VERSION_LATEST; 412 413 /* inherited from parent obj via riscv_cpu_init() */ 414 cpu->cfg.ext_ifencei = true; 415 cpu->cfg.ext_icsr = true; 416 cpu->cfg.mmu = true; 417 cpu->cfg.pmp = true; 418 } 419 420 static void riscv_max_cpu_init(Object *obj) 421 { 422 RISCVCPU *cpu = RISCV_CPU(obj); 423 CPURISCVState *env = &cpu->env; 424 RISCVMXL mlx = MXL_RV64; 425 426 #ifdef TARGET_RISCV32 427 mlx = MXL_RV32; 428 #endif 429 set_misa(env, mlx, 0); 430 env->priv_ver = PRIV_VERSION_LATEST; 431 #ifndef CONFIG_USER_ONLY 432 set_satp_mode_max_supported(RISCV_CPU(obj), mlx == MXL_RV32 ? 433 VM_1_10_SV32 : VM_1_10_SV57); 434 #endif 435 } 436 437 #if defined(TARGET_RISCV64) 438 static void rv64_base_cpu_init(Object *obj) 439 { 440 CPURISCVState *env = &RISCV_CPU(obj)->env; 441 /* We set this in the realise function */ 442 set_misa(env, MXL_RV64, 0); 443 /* Set latest version of privileged specification */ 444 env->priv_ver = PRIV_VERSION_LATEST; 445 #ifndef CONFIG_USER_ONLY 446 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 447 #endif 448 } 449 450 static void rv64_sifive_u_cpu_init(Object *obj) 451 { 452 RISCVCPU *cpu = RISCV_CPU(obj); 453 CPURISCVState *env = &cpu->env; 454 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 455 env->priv_ver = PRIV_VERSION_1_10_0; 456 #ifndef CONFIG_USER_ONLY 457 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); 458 #endif 459 460 /* inherited from parent obj via riscv_cpu_init() */ 461 cpu->cfg.ext_ifencei = true; 462 cpu->cfg.ext_icsr = true; 463 cpu->cfg.mmu = true; 464 cpu->cfg.pmp = true; 465 } 466 467 static void rv64_sifive_e_cpu_init(Object *obj) 468 { 469 CPURISCVState *env = &RISCV_CPU(obj)->env; 470 RISCVCPU *cpu = RISCV_CPU(obj); 471 472 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 473 env->priv_ver = PRIV_VERSION_1_10_0; 474 #ifndef CONFIG_USER_ONLY 475 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 476 #endif 477 478 /* inherited from parent obj via riscv_cpu_init() */ 479 cpu->cfg.ext_ifencei = true; 480 cpu->cfg.ext_icsr = true; 481 cpu->cfg.pmp = true; 482 } 483 484 static void rv64_thead_c906_cpu_init(Object *obj) 485 { 486 CPURISCVState *env = &RISCV_CPU(obj)->env; 487 RISCVCPU *cpu = RISCV_CPU(obj); 488 489 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); 490 env->priv_ver = PRIV_VERSION_1_11_0; 491 492 cpu->cfg.ext_zfa = true; 493 cpu->cfg.ext_zfh = true; 494 cpu->cfg.mmu = true; 495 cpu->cfg.ext_xtheadba = true; 496 cpu->cfg.ext_xtheadbb = true; 497 cpu->cfg.ext_xtheadbs = true; 498 cpu->cfg.ext_xtheadcmo = true; 499 cpu->cfg.ext_xtheadcondmov = true; 500 cpu->cfg.ext_xtheadfmemidx = true; 501 cpu->cfg.ext_xtheadmac = true; 502 cpu->cfg.ext_xtheadmemidx = true; 503 cpu->cfg.ext_xtheadmempair = true; 504 cpu->cfg.ext_xtheadsync = true; 505 506 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 507 #ifndef CONFIG_USER_ONLY 508 set_satp_mode_max_supported(cpu, VM_1_10_SV39); 509 #endif 510 511 /* inherited from parent obj via riscv_cpu_init() */ 512 cpu->cfg.pmp = true; 513 } 514 515 static void rv64_veyron_v1_cpu_init(Object *obj) 516 { 517 CPURISCVState *env = &RISCV_CPU(obj)->env; 518 RISCVCPU *cpu = RISCV_CPU(obj); 519 520 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); 521 env->priv_ver = PRIV_VERSION_1_12_0; 522 523 /* Enable ISA extensions */ 524 cpu->cfg.mmu = true; 525 cpu->cfg.ext_ifencei = true; 526 cpu->cfg.ext_icsr = true; 527 cpu->cfg.pmp = true; 528 cpu->cfg.ext_icbom = true; 529 cpu->cfg.cbom_blocksize = 64; 530 cpu->cfg.cboz_blocksize = 64; 531 cpu->cfg.ext_icboz = true; 532 cpu->cfg.ext_smaia = true; 533 cpu->cfg.ext_ssaia = true; 534 cpu->cfg.ext_sscofpmf = true; 535 cpu->cfg.ext_sstc = true; 536 cpu->cfg.ext_svinval = true; 537 cpu->cfg.ext_svnapot = true; 538 cpu->cfg.ext_svpbmt = true; 539 cpu->cfg.ext_smstateen = true; 540 cpu->cfg.ext_zba = true; 541 cpu->cfg.ext_zbb = true; 542 cpu->cfg.ext_zbc = true; 543 cpu->cfg.ext_zbs = true; 544 cpu->cfg.ext_XVentanaCondOps = true; 545 546 cpu->cfg.mvendorid = VEYRON_V1_MVENDORID; 547 cpu->cfg.marchid = VEYRON_V1_MARCHID; 548 cpu->cfg.mimpid = VEYRON_V1_MIMPID; 549 550 #ifndef CONFIG_USER_ONLY 551 set_satp_mode_max_supported(cpu, VM_1_10_SV48); 552 #endif 553 } 554 555 static void rv128_base_cpu_init(Object *obj) 556 { 557 if (qemu_tcg_mttcg_enabled()) { 558 /* Missing 128-bit aligned atomics */ 559 error_report("128-bit RISC-V currently does not work with Multi " 560 "Threaded TCG. Please use: -accel tcg,thread=single"); 561 exit(EXIT_FAILURE); 562 } 563 CPURISCVState *env = &RISCV_CPU(obj)->env; 564 /* We set this in the realise function */ 565 set_misa(env, MXL_RV128, 0); 566 /* Set latest version of privileged specification */ 567 env->priv_ver = PRIV_VERSION_LATEST; 568 #ifndef CONFIG_USER_ONLY 569 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 570 #endif 571 } 572 #else 573 static void rv32_base_cpu_init(Object *obj) 574 { 575 CPURISCVState *env = &RISCV_CPU(obj)->env; 576 /* We set this in the realise function */ 577 set_misa(env, MXL_RV32, 0); 578 /* Set latest version of privileged specification */ 579 env->priv_ver = PRIV_VERSION_LATEST; 580 #ifndef CONFIG_USER_ONLY 581 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 582 #endif 583 } 584 585 static void rv32_sifive_u_cpu_init(Object *obj) 586 { 587 RISCVCPU *cpu = RISCV_CPU(obj); 588 CPURISCVState *env = &cpu->env; 589 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 590 env->priv_ver = PRIV_VERSION_1_10_0; 591 #ifndef CONFIG_USER_ONLY 592 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 593 #endif 594 595 /* inherited from parent obj via riscv_cpu_init() */ 596 cpu->cfg.ext_ifencei = true; 597 cpu->cfg.ext_icsr = true; 598 cpu->cfg.mmu = true; 599 cpu->cfg.pmp = true; 600 } 601 602 static void rv32_sifive_e_cpu_init(Object *obj) 603 { 604 CPURISCVState *env = &RISCV_CPU(obj)->env; 605 RISCVCPU *cpu = RISCV_CPU(obj); 606 607 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 608 env->priv_ver = PRIV_VERSION_1_10_0; 609 #ifndef CONFIG_USER_ONLY 610 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 611 #endif 612 613 /* inherited from parent obj via riscv_cpu_init() */ 614 cpu->cfg.ext_ifencei = true; 615 cpu->cfg.ext_icsr = true; 616 cpu->cfg.pmp = true; 617 } 618 619 static void rv32_ibex_cpu_init(Object *obj) 620 { 621 CPURISCVState *env = &RISCV_CPU(obj)->env; 622 RISCVCPU *cpu = RISCV_CPU(obj); 623 624 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 625 env->priv_ver = PRIV_VERSION_1_11_0; 626 #ifndef CONFIG_USER_ONLY 627 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 628 #endif 629 cpu->cfg.epmp = true; 630 631 /* inherited from parent obj via riscv_cpu_init() */ 632 cpu->cfg.ext_ifencei = true; 633 cpu->cfg.ext_icsr = true; 634 cpu->cfg.pmp = true; 635 } 636 637 static void rv32_imafcu_nommu_cpu_init(Object *obj) 638 { 639 CPURISCVState *env = &RISCV_CPU(obj)->env; 640 RISCVCPU *cpu = RISCV_CPU(obj); 641 642 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 643 env->priv_ver = PRIV_VERSION_1_10_0; 644 #ifndef CONFIG_USER_ONLY 645 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 646 #endif 647 648 /* inherited from parent obj via riscv_cpu_init() */ 649 cpu->cfg.ext_ifencei = true; 650 cpu->cfg.ext_icsr = true; 651 cpu->cfg.pmp = true; 652 } 653 #endif 654 655 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 656 { 657 ObjectClass *oc; 658 char *typename; 659 char **cpuname; 660 661 cpuname = g_strsplit(cpu_model, ",", 1); 662 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 663 oc = object_class_by_name(typename); 664 g_strfreev(cpuname); 665 g_free(typename); 666 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 667 object_class_is_abstract(oc)) { 668 return NULL; 669 } 670 return oc; 671 } 672 673 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 674 { 675 RISCVCPU *cpu = RISCV_CPU(cs); 676 CPURISCVState *env = &cpu->env; 677 int i, j; 678 uint8_t *p; 679 680 #if !defined(CONFIG_USER_ONLY) 681 if (riscv_has_ext(env, RVH)) { 682 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); 683 } 684 #endif 685 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 686 #ifndef CONFIG_USER_ONLY 687 { 688 static const int dump_csrs[] = { 689 CSR_MHARTID, 690 CSR_MSTATUS, 691 CSR_MSTATUSH, 692 /* 693 * CSR_SSTATUS is intentionally omitted here as its value 694 * can be figured out by looking at CSR_MSTATUS 695 */ 696 CSR_HSTATUS, 697 CSR_VSSTATUS, 698 CSR_MIP, 699 CSR_MIE, 700 CSR_MIDELEG, 701 CSR_HIDELEG, 702 CSR_MEDELEG, 703 CSR_HEDELEG, 704 CSR_MTVEC, 705 CSR_STVEC, 706 CSR_VSTVEC, 707 CSR_MEPC, 708 CSR_SEPC, 709 CSR_VSEPC, 710 CSR_MCAUSE, 711 CSR_SCAUSE, 712 CSR_VSCAUSE, 713 CSR_MTVAL, 714 CSR_STVAL, 715 CSR_HTVAL, 716 CSR_MTVAL2, 717 CSR_MSCRATCH, 718 CSR_SSCRATCH, 719 CSR_SATP, 720 CSR_MMTE, 721 CSR_UPMBASE, 722 CSR_UPMMASK, 723 CSR_SPMBASE, 724 CSR_SPMMASK, 725 CSR_MPMBASE, 726 CSR_MPMMASK, 727 }; 728 729 for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 730 int csrno = dump_csrs[i]; 731 target_ulong val = 0; 732 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 733 734 /* 735 * Rely on the smode, hmode, etc, predicates within csr.c 736 * to do the filtering of the registers that are present. 737 */ 738 if (res == RISCV_EXCP_NONE) { 739 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 740 csr_ops[csrno].name, val); 741 } 742 } 743 } 744 #endif 745 746 for (i = 0; i < 32; i++) { 747 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 748 riscv_int_regnames[i], env->gpr[i]); 749 if ((i & 3) == 3) { 750 qemu_fprintf(f, "\n"); 751 } 752 } 753 if (flags & CPU_DUMP_FPU) { 754 for (i = 0; i < 32; i++) { 755 qemu_fprintf(f, " %-8s %016" PRIx64, 756 riscv_fpr_regnames[i], env->fpr[i]); 757 if ((i & 3) == 3) { 758 qemu_fprintf(f, "\n"); 759 } 760 } 761 } 762 if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) { 763 static const int dump_rvv_csrs[] = { 764 CSR_VSTART, 765 CSR_VXSAT, 766 CSR_VXRM, 767 CSR_VCSR, 768 CSR_VL, 769 CSR_VTYPE, 770 CSR_VLENB, 771 }; 772 for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) { 773 int csrno = dump_rvv_csrs[i]; 774 target_ulong val = 0; 775 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 776 777 /* 778 * Rely on the smode, hmode, etc, predicates within csr.c 779 * to do the filtering of the registers that are present. 780 */ 781 if (res == RISCV_EXCP_NONE) { 782 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 783 csr_ops[csrno].name, val); 784 } 785 } 786 uint16_t vlenb = cpu->cfg.vlen >> 3; 787 788 for (i = 0; i < 32; i++) { 789 qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]); 790 p = (uint8_t *)env->vreg; 791 for (j = vlenb - 1 ; j >= 0; j--) { 792 qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j))); 793 } 794 qemu_fprintf(f, "\n"); 795 } 796 } 797 } 798 799 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 800 { 801 RISCVCPU *cpu = RISCV_CPU(cs); 802 CPURISCVState *env = &cpu->env; 803 804 if (env->xl == MXL_RV32) { 805 env->pc = (int32_t)value; 806 } else { 807 env->pc = value; 808 } 809 } 810 811 static vaddr riscv_cpu_get_pc(CPUState *cs) 812 { 813 RISCVCPU *cpu = RISCV_CPU(cs); 814 CPURISCVState *env = &cpu->env; 815 816 /* Match cpu_get_tb_cpu_state. */ 817 if (env->xl == MXL_RV32) { 818 return env->pc & UINT32_MAX; 819 } 820 return env->pc; 821 } 822 823 static bool riscv_cpu_has_work(CPUState *cs) 824 { 825 #ifndef CONFIG_USER_ONLY 826 RISCVCPU *cpu = RISCV_CPU(cs); 827 CPURISCVState *env = &cpu->env; 828 /* 829 * Definition of the WFI instruction requires it to ignore the privilege 830 * mode and delegation registers, but respect individual enables 831 */ 832 return riscv_cpu_all_pending(env) != 0; 833 #else 834 return true; 835 #endif 836 } 837 838 static void riscv_cpu_reset_hold(Object *obj) 839 { 840 #ifndef CONFIG_USER_ONLY 841 uint8_t iprio; 842 int i, irq, rdzero; 843 #endif 844 CPUState *cs = CPU(obj); 845 RISCVCPU *cpu = RISCV_CPU(cs); 846 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 847 CPURISCVState *env = &cpu->env; 848 849 if (mcc->parent_phases.hold) { 850 mcc->parent_phases.hold(obj); 851 } 852 #ifndef CONFIG_USER_ONLY 853 env->misa_mxl = env->misa_mxl_max; 854 env->priv = PRV_M; 855 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 856 if (env->misa_mxl > MXL_RV32) { 857 /* 858 * The reset status of SXL/UXL is undefined, but mstatus is WARL 859 * and we must ensure that the value after init is valid for read. 860 */ 861 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 862 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 863 if (riscv_has_ext(env, RVH)) { 864 env->vsstatus = set_field(env->vsstatus, 865 MSTATUS64_SXL, env->misa_mxl); 866 env->vsstatus = set_field(env->vsstatus, 867 MSTATUS64_UXL, env->misa_mxl); 868 env->mstatus_hs = set_field(env->mstatus_hs, 869 MSTATUS64_SXL, env->misa_mxl); 870 env->mstatus_hs = set_field(env->mstatus_hs, 871 MSTATUS64_UXL, env->misa_mxl); 872 } 873 } 874 env->mcause = 0; 875 env->miclaim = MIP_SGEIP; 876 env->pc = env->resetvec; 877 env->bins = 0; 878 env->two_stage_lookup = false; 879 880 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | 881 (cpu->cfg.ext_svadu ? MENVCFG_ADUE : 0); 882 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | 883 (cpu->cfg.ext_svadu ? HENVCFG_ADUE : 0); 884 885 /* Initialized default priorities of local interrupts. */ 886 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 887 iprio = riscv_cpu_default_priority(i); 888 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 889 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 890 env->hviprio[i] = 0; 891 } 892 i = 0; 893 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 894 if (!rdzero) { 895 env->hviprio[irq] = env->miprio[irq]; 896 } 897 i++; 898 } 899 /* mmte is supposed to have pm.current hardwired to 1 */ 900 env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); 901 #endif 902 env->xl = riscv_cpu_mxl(env); 903 riscv_cpu_update_mask(env); 904 cs->exception_index = RISCV_EXCP_NONE; 905 env->load_res = -1; 906 set_default_nan_mode(1, &env->fp_status); 907 908 #ifndef CONFIG_USER_ONLY 909 if (cpu->cfg.debug) { 910 riscv_trigger_reset_hold(env); 911 } 912 913 if (kvm_enabled()) { 914 kvm_riscv_reset_vcpu(cpu); 915 } 916 #endif 917 } 918 919 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 920 { 921 RISCVCPU *cpu = RISCV_CPU(s); 922 CPURISCVState *env = &cpu->env; 923 info->target_info = &cpu->cfg; 924 925 switch (env->xl) { 926 case MXL_RV32: 927 info->print_insn = print_insn_riscv32; 928 break; 929 case MXL_RV64: 930 info->print_insn = print_insn_riscv64; 931 break; 932 case MXL_RV128: 933 info->print_insn = print_insn_riscv128; 934 break; 935 default: 936 g_assert_not_reached(); 937 } 938 } 939 940 void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 941 { 942 CPURISCVState *env = &cpu->env; 943 int i; 944 945 /* Force disable extensions if priv spec version does not match */ 946 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 947 if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset) && 948 (env->priv_ver < isa_edata_arr[i].min_version)) { 949 isa_ext_update_enabled(cpu, isa_edata_arr[i].ext_enable_offset, 950 false); 951 #ifndef CONFIG_USER_ONLY 952 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 953 " because privilege spec version does not match", 954 isa_edata_arr[i].name, env->mhartid); 955 #else 956 warn_report("disabling %s extension because " 957 "privilege spec version does not match", 958 isa_edata_arr[i].name); 959 #endif 960 } 961 } 962 } 963 964 #ifndef CONFIG_USER_ONLY 965 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) 966 { 967 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 968 uint8_t satp_mode_map_max, satp_mode_supported_max; 969 970 /* The CPU wants the OS to decide which satp mode to use */ 971 if (cpu->cfg.satp_mode.supported == 0) { 972 return; 973 } 974 975 satp_mode_supported_max = 976 satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 977 978 if (cpu->cfg.satp_mode.map == 0) { 979 if (cpu->cfg.satp_mode.init == 0) { 980 /* If unset by the user, we fallback to the default satp mode. */ 981 set_satp_mode_default_map(cpu); 982 } else { 983 /* 984 * Find the lowest level that was disabled and then enable the 985 * first valid level below which can be found in 986 * valid_vm_1_10_32/64. 987 */ 988 for (int i = 1; i < 16; ++i) { 989 if ((cpu->cfg.satp_mode.init & (1 << i)) && 990 (cpu->cfg.satp_mode.supported & (1 << i))) { 991 for (int j = i - 1; j >= 0; --j) { 992 if (cpu->cfg.satp_mode.supported & (1 << j)) { 993 cpu->cfg.satp_mode.map |= (1 << j); 994 break; 995 } 996 } 997 break; 998 } 999 } 1000 } 1001 } 1002 1003 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 1004 1005 /* Make sure the user asked for a supported configuration (HW and qemu) */ 1006 if (satp_mode_map_max > satp_mode_supported_max) { 1007 error_setg(errp, "satp_mode %s is higher than hw max capability %s", 1008 satp_mode_str(satp_mode_map_max, rv32), 1009 satp_mode_str(satp_mode_supported_max, rv32)); 1010 return; 1011 } 1012 1013 /* 1014 * Make sure the user did not ask for an invalid configuration as per 1015 * the specification. 1016 */ 1017 if (!rv32) { 1018 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1019 if (!(cpu->cfg.satp_mode.map & (1 << i)) && 1020 (cpu->cfg.satp_mode.init & (1 << i)) && 1021 (cpu->cfg.satp_mode.supported & (1 << i))) { 1022 error_setg(errp, "cannot disable %s satp mode if %s " 1023 "is enabled", satp_mode_str(i, false), 1024 satp_mode_str(satp_mode_map_max, false)); 1025 return; 1026 } 1027 } 1028 } 1029 1030 /* Finally expand the map so that all valid modes are set */ 1031 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1032 if (cpu->cfg.satp_mode.supported & (1 << i)) { 1033 cpu->cfg.satp_mode.map |= (1 << i); 1034 } 1035 } 1036 } 1037 #endif 1038 1039 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1040 { 1041 #ifndef CONFIG_USER_ONLY 1042 Error *local_err = NULL; 1043 1044 riscv_cpu_satp_mode_finalize(cpu, &local_err); 1045 if (local_err != NULL) { 1046 error_propagate(errp, local_err); 1047 return; 1048 } 1049 #endif 1050 } 1051 1052 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 1053 { 1054 CPUState *cs = CPU(dev); 1055 RISCVCPU *cpu = RISCV_CPU(dev); 1056 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 1057 Error *local_err = NULL; 1058 1059 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_ANY) != NULL) { 1060 warn_report("The 'any' CPU is deprecated and will be " 1061 "removed in the future."); 1062 } 1063 1064 cpu_exec_realizefn(cs, &local_err); 1065 if (local_err != NULL) { 1066 error_propagate(errp, local_err); 1067 return; 1068 } 1069 1070 riscv_cpu_finalize_features(cpu, &local_err); 1071 if (local_err != NULL) { 1072 error_propagate(errp, local_err); 1073 return; 1074 } 1075 1076 riscv_cpu_register_gdb_regs_for_features(cs); 1077 1078 #ifndef CONFIG_USER_ONLY 1079 if (cpu->cfg.debug) { 1080 riscv_trigger_realize(&cpu->env); 1081 } 1082 #endif 1083 1084 qemu_init_vcpu(cs); 1085 cpu_reset(cs); 1086 1087 mcc->parent_realize(dev, errp); 1088 } 1089 1090 #ifndef CONFIG_USER_ONLY 1091 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, 1092 void *opaque, Error **errp) 1093 { 1094 RISCVSATPMap *satp_map = opaque; 1095 uint8_t satp = satp_mode_from_str(name); 1096 bool value; 1097 1098 value = satp_map->map & (1 << satp); 1099 1100 visit_type_bool(v, name, &value, errp); 1101 } 1102 1103 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, 1104 void *opaque, Error **errp) 1105 { 1106 RISCVSATPMap *satp_map = opaque; 1107 uint8_t satp = satp_mode_from_str(name); 1108 bool value; 1109 1110 if (!visit_type_bool(v, name, &value, errp)) { 1111 return; 1112 } 1113 1114 satp_map->map = deposit32(satp_map->map, satp, 1, value); 1115 satp_map->init |= 1 << satp; 1116 } 1117 1118 void riscv_add_satp_mode_properties(Object *obj) 1119 { 1120 RISCVCPU *cpu = RISCV_CPU(obj); 1121 1122 if (cpu->env.misa_mxl == MXL_RV32) { 1123 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, 1124 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1125 } else { 1126 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, 1127 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1128 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, 1129 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1130 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, 1131 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1132 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, 1133 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1134 } 1135 } 1136 1137 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1138 { 1139 RISCVCPU *cpu = RISCV_CPU(opaque); 1140 CPURISCVState *env = &cpu->env; 1141 1142 if (irq < IRQ_LOCAL_MAX) { 1143 switch (irq) { 1144 case IRQ_U_SOFT: 1145 case IRQ_S_SOFT: 1146 case IRQ_VS_SOFT: 1147 case IRQ_M_SOFT: 1148 case IRQ_U_TIMER: 1149 case IRQ_S_TIMER: 1150 case IRQ_VS_TIMER: 1151 case IRQ_M_TIMER: 1152 case IRQ_U_EXT: 1153 case IRQ_VS_EXT: 1154 case IRQ_M_EXT: 1155 if (kvm_enabled()) { 1156 kvm_riscv_set_irq(cpu, irq, level); 1157 } else { 1158 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); 1159 } 1160 break; 1161 case IRQ_S_EXT: 1162 if (kvm_enabled()) { 1163 kvm_riscv_set_irq(cpu, irq, level); 1164 } else { 1165 env->external_seip = level; 1166 riscv_cpu_update_mip(env, 1 << irq, 1167 BOOL_TO_MASK(level | env->software_seip)); 1168 } 1169 break; 1170 default: 1171 g_assert_not_reached(); 1172 } 1173 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1174 /* Require H-extension for handling guest local interrupts */ 1175 if (!riscv_has_ext(env, RVH)) { 1176 g_assert_not_reached(); 1177 } 1178 1179 /* Compute bit position in HGEIP CSR */ 1180 irq = irq - IRQ_LOCAL_MAX + 1; 1181 if (env->geilen < irq) { 1182 g_assert_not_reached(); 1183 } 1184 1185 /* Update HGEIP CSR */ 1186 env->hgeip &= ~((target_ulong)1 << irq); 1187 if (level) { 1188 env->hgeip |= (target_ulong)1 << irq; 1189 } 1190 1191 /* Update mip.SGEIP bit */ 1192 riscv_cpu_update_mip(env, MIP_SGEIP, 1193 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1194 } else { 1195 g_assert_not_reached(); 1196 } 1197 } 1198 #endif /* CONFIG_USER_ONLY */ 1199 1200 static bool riscv_cpu_is_dynamic(Object *cpu_obj) 1201 { 1202 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 1203 } 1204 1205 static bool riscv_cpu_has_max_extensions(Object *cpu_obj) 1206 { 1207 return object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_MAX) != NULL; 1208 } 1209 1210 static bool riscv_cpu_has_user_properties(Object *cpu_obj) 1211 { 1212 if (kvm_enabled() && 1213 object_dynamic_cast(cpu_obj, TYPE_RISCV_CPU_HOST) != NULL) { 1214 return true; 1215 } 1216 1217 return riscv_cpu_is_dynamic(cpu_obj); 1218 } 1219 1220 static void riscv_cpu_post_init(Object *obj) 1221 { 1222 accel_cpu_instance_init(CPU(obj)); 1223 1224 if (tcg_enabled() && riscv_cpu_has_user_properties(obj)) { 1225 riscv_cpu_add_user_properties(obj); 1226 } 1227 1228 if (riscv_cpu_has_max_extensions(obj)) { 1229 riscv_init_max_cpu_extensions(obj); 1230 } 1231 } 1232 1233 static void riscv_cpu_init(Object *obj) 1234 { 1235 #ifndef CONFIG_USER_ONLY 1236 qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq, 1237 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1238 #endif /* CONFIG_USER_ONLY */ 1239 1240 multi_ext_user_opts = g_hash_table_new(NULL, g_direct_equal); 1241 } 1242 1243 typedef struct RISCVCPUMisaExtConfig { 1244 const char *name; 1245 const char *description; 1246 target_ulong misa_bit; 1247 bool enabled; 1248 } RISCVCPUMisaExtConfig; 1249 1250 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1251 void *opaque, Error **errp) 1252 { 1253 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1254 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1255 RISCVCPU *cpu = RISCV_CPU(obj); 1256 CPURISCVState *env = &cpu->env; 1257 bool value; 1258 1259 if (!visit_type_bool(v, name, &value, errp)) { 1260 return; 1261 } 1262 1263 if (value) { 1264 env->misa_ext |= misa_bit; 1265 env->misa_ext_mask |= misa_bit; 1266 } else { 1267 env->misa_ext &= ~misa_bit; 1268 env->misa_ext_mask &= ~misa_bit; 1269 } 1270 } 1271 1272 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1273 void *opaque, Error **errp) 1274 { 1275 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1276 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1277 RISCVCPU *cpu = RISCV_CPU(obj); 1278 CPURISCVState *env = &cpu->env; 1279 bool value; 1280 1281 value = env->misa_ext & misa_bit; 1282 1283 visit_type_bool(v, name, &value, errp); 1284 } 1285 1286 typedef struct misa_ext_info { 1287 const char *name; 1288 const char *description; 1289 } MISAExtInfo; 1290 1291 #define MISA_INFO_IDX(_bit) \ 1292 __builtin_ctz(_bit) 1293 1294 #define MISA_EXT_INFO(_bit, _propname, _descr) \ 1295 [MISA_INFO_IDX(_bit)] = {.name = _propname, .description = _descr} 1296 1297 static const MISAExtInfo misa_ext_info_arr[] = { 1298 MISA_EXT_INFO(RVA, "a", "Atomic instructions"), 1299 MISA_EXT_INFO(RVC, "c", "Compressed instructions"), 1300 MISA_EXT_INFO(RVD, "d", "Double-precision float point"), 1301 MISA_EXT_INFO(RVF, "f", "Single-precision float point"), 1302 MISA_EXT_INFO(RVI, "i", "Base integer instruction set"), 1303 MISA_EXT_INFO(RVE, "e", "Base integer instruction set (embedded)"), 1304 MISA_EXT_INFO(RVM, "m", "Integer multiplication and division"), 1305 MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"), 1306 MISA_EXT_INFO(RVU, "u", "User-level instructions"), 1307 MISA_EXT_INFO(RVH, "h", "Hypervisor"), 1308 MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), 1309 MISA_EXT_INFO(RVV, "v", "Vector operations"), 1310 MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), 1311 }; 1312 1313 static int riscv_validate_misa_info_idx(uint32_t bit) 1314 { 1315 int idx; 1316 1317 /* 1318 * Our lowest valid input (RVA) is 1 and 1319 * __builtin_ctz() is UB with zero. 1320 */ 1321 g_assert(bit != 0); 1322 idx = MISA_INFO_IDX(bit); 1323 1324 g_assert(idx < ARRAY_SIZE(misa_ext_info_arr)); 1325 return idx; 1326 } 1327 1328 const char *riscv_get_misa_ext_name(uint32_t bit) 1329 { 1330 int idx = riscv_validate_misa_info_idx(bit); 1331 const char *val = misa_ext_info_arr[idx].name; 1332 1333 g_assert(val != NULL); 1334 return val; 1335 } 1336 1337 const char *riscv_get_misa_ext_description(uint32_t bit) 1338 { 1339 int idx = riscv_validate_misa_info_idx(bit); 1340 const char *val = misa_ext_info_arr[idx].description; 1341 1342 g_assert(val != NULL); 1343 return val; 1344 } 1345 1346 #define MISA_CFG(_bit, _enabled) \ 1347 {.misa_bit = _bit, .enabled = _enabled} 1348 1349 static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1350 MISA_CFG(RVA, true), 1351 MISA_CFG(RVC, true), 1352 MISA_CFG(RVD, true), 1353 MISA_CFG(RVF, true), 1354 MISA_CFG(RVI, true), 1355 MISA_CFG(RVE, false), 1356 MISA_CFG(RVM, true), 1357 MISA_CFG(RVS, true), 1358 MISA_CFG(RVU, true), 1359 MISA_CFG(RVH, true), 1360 MISA_CFG(RVJ, false), 1361 MISA_CFG(RVV, false), 1362 MISA_CFG(RVG, false), 1363 }; 1364 1365 /* 1366 * We do not support user choice tracking for MISA 1367 * extensions yet because, so far, we do not silently 1368 * change MISA bits during realize() (RVG enables MISA 1369 * bits but the user is warned about it). 1370 */ 1371 void riscv_cpu_add_misa_properties(Object *cpu_obj) 1372 { 1373 int i; 1374 1375 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1376 RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1377 int bit = misa_cfg->misa_bit; 1378 1379 misa_cfg->name = riscv_get_misa_ext_name(bit); 1380 misa_cfg->description = riscv_get_misa_ext_description(bit); 1381 1382 /* Check if KVM already created the property */ 1383 if (object_property_find(cpu_obj, misa_cfg->name)) { 1384 continue; 1385 } 1386 1387 object_property_add(cpu_obj, misa_cfg->name, "bool", 1388 cpu_get_misa_ext_cfg, 1389 cpu_set_misa_ext_cfg, 1390 NULL, (void *)misa_cfg); 1391 object_property_set_description(cpu_obj, misa_cfg->name, 1392 misa_cfg->description); 1393 object_property_set_bool(cpu_obj, misa_cfg->name, 1394 misa_cfg->enabled, NULL); 1395 } 1396 } 1397 1398 #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \ 1399 {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \ 1400 .enabled = _defval} 1401 1402 const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { 1403 /* Defaults for standard extensions */ 1404 MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), 1405 MULTI_EXT_CFG_BOOL("Zifencei", ext_ifencei, true), 1406 MULTI_EXT_CFG_BOOL("Zicsr", ext_icsr, true), 1407 MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true), 1408 MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true), 1409 MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true), 1410 MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true), 1411 MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false), 1412 MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false), 1413 MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false), 1414 MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false), 1415 MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false), 1416 MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true), 1417 1418 MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false), 1419 MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true), 1420 MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false), 1421 MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false), 1422 MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false), 1423 1424 MULTI_EXT_CFG_BOOL("zba", ext_zba, true), 1425 MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true), 1426 MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true), 1427 MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false), 1428 MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false), 1429 MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false), 1430 MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true), 1431 MULTI_EXT_CFG_BOOL("zk", ext_zk, false), 1432 MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false), 1433 MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false), 1434 MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false), 1435 MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false), 1436 MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false), 1437 MULTI_EXT_CFG_BOOL("zks", ext_zks, false), 1438 MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false), 1439 MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false), 1440 MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false), 1441 1442 MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false), 1443 MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false), 1444 MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false), 1445 MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false), 1446 1447 MULTI_EXT_CFG_BOOL("zicbom", ext_icbom, true), 1448 MULTI_EXT_CFG_BOOL("zicboz", ext_icboz, true), 1449 1450 MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false), 1451 1452 MULTI_EXT_CFG_BOOL("zca", ext_zca, false), 1453 MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false), 1454 MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false), 1455 MULTI_EXT_CFG_BOOL("zce", ext_zce, false), 1456 MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false), 1457 MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false), 1458 MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false), 1459 MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false), 1460 1461 DEFINE_PROP_END_OF_LIST(), 1462 }; 1463 1464 const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { 1465 MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false), 1466 MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false), 1467 MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false), 1468 MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false), 1469 MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false), 1470 MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false), 1471 MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false), 1472 MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false), 1473 MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false), 1474 MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false), 1475 MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false), 1476 MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), 1477 1478 DEFINE_PROP_END_OF_LIST(), 1479 }; 1480 1481 /* These are experimental so mark with 'x-' */ 1482 const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { 1483 /* ePMP 0.9.3 */ 1484 MULTI_EXT_CFG_BOOL("x-epmp", epmp, false), 1485 MULTI_EXT_CFG_BOOL("x-smaia", ext_smaia, false), 1486 MULTI_EXT_CFG_BOOL("x-ssaia", ext_ssaia, false), 1487 1488 MULTI_EXT_CFG_BOOL("x-zvfh", ext_zvfh, false), 1489 MULTI_EXT_CFG_BOOL("x-zvfhmin", ext_zvfhmin, false), 1490 1491 MULTI_EXT_CFG_BOOL("x-zfbfmin", ext_zfbfmin, false), 1492 MULTI_EXT_CFG_BOOL("x-zvfbfmin", ext_zvfbfmin, false), 1493 MULTI_EXT_CFG_BOOL("x-zvfbfwma", ext_zvfbfwma, false), 1494 1495 /* Vector cryptography extensions */ 1496 MULTI_EXT_CFG_BOOL("x-zvbb", ext_zvbb, false), 1497 MULTI_EXT_CFG_BOOL("x-zvbc", ext_zvbc, false), 1498 MULTI_EXT_CFG_BOOL("x-zvkg", ext_zvkg, false), 1499 MULTI_EXT_CFG_BOOL("x-zvkned", ext_zvkned, false), 1500 MULTI_EXT_CFG_BOOL("x-zvknha", ext_zvknha, false), 1501 MULTI_EXT_CFG_BOOL("x-zvknhb", ext_zvknhb, false), 1502 MULTI_EXT_CFG_BOOL("x-zvksed", ext_zvksed, false), 1503 MULTI_EXT_CFG_BOOL("x-zvksh", ext_zvksh, false), 1504 1505 DEFINE_PROP_END_OF_LIST(), 1506 }; 1507 1508 Property riscv_cpu_options[] = { 1509 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1510 1511 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1512 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1513 1514 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1515 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1516 1517 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1518 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1519 1520 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), 1521 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), 1522 1523 DEFINE_PROP_END_OF_LIST(), 1524 }; 1525 1526 static void cpu_set_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1527 void *opaque, Error **errp) 1528 { 1529 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1530 bool value; 1531 1532 if (!visit_type_bool(v, name, &value, errp)) { 1533 return; 1534 } 1535 1536 isa_ext_update_enabled(RISCV_CPU(obj), multi_ext_cfg->offset, value); 1537 1538 g_hash_table_insert(multi_ext_user_opts, 1539 GUINT_TO_POINTER(multi_ext_cfg->offset), 1540 (gpointer)value); 1541 } 1542 1543 static void cpu_get_multi_ext_cfg(Object *obj, Visitor *v, const char *name, 1544 void *opaque, Error **errp) 1545 { 1546 const RISCVCPUMultiExtConfig *multi_ext_cfg = opaque; 1547 bool value = isa_ext_is_enabled(RISCV_CPU(obj), multi_ext_cfg->offset); 1548 1549 visit_type_bool(v, name, &value, errp); 1550 } 1551 1552 static void cpu_add_multi_ext_prop(Object *cpu_obj, 1553 const RISCVCPUMultiExtConfig *multi_cfg) 1554 { 1555 object_property_add(cpu_obj, multi_cfg->name, "bool", 1556 cpu_get_multi_ext_cfg, 1557 cpu_set_multi_ext_cfg, 1558 NULL, (void *)multi_cfg); 1559 1560 /* 1561 * Set def val directly instead of using 1562 * object_property_set_bool() to save the set() 1563 * callback hash for user inputs. 1564 */ 1565 isa_ext_update_enabled(RISCV_CPU(cpu_obj), multi_cfg->offset, 1566 multi_cfg->enabled); 1567 } 1568 1569 static void riscv_cpu_add_multiext_prop_array(Object *obj, 1570 const RISCVCPUMultiExtConfig *array) 1571 { 1572 const RISCVCPUMultiExtConfig *prop; 1573 1574 g_assert(array); 1575 1576 for (prop = array; prop && prop->name; prop++) { 1577 cpu_add_multi_ext_prop(obj, prop); 1578 } 1579 } 1580 1581 /* 1582 * Add CPU properties with user-facing flags. 1583 * 1584 * This will overwrite existing env->misa_ext values with the 1585 * defaults set via riscv_cpu_add_misa_properties(). 1586 */ 1587 static void riscv_cpu_add_user_properties(Object *obj) 1588 { 1589 #ifndef CONFIG_USER_ONLY 1590 riscv_add_satp_mode_properties(obj); 1591 #endif 1592 1593 riscv_cpu_add_misa_properties(obj); 1594 1595 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_extensions); 1596 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_vendor_exts); 1597 riscv_cpu_add_multiext_prop_array(obj, riscv_cpu_experimental_exts); 1598 1599 for (Property *prop = riscv_cpu_options; prop && prop->name; prop++) { 1600 qdev_property_add_static(DEVICE(obj), prop); 1601 } 1602 } 1603 1604 /* 1605 * The 'max' type CPU will have all possible ratified 1606 * non-vendor extensions enabled. 1607 */ 1608 static void riscv_init_max_cpu_extensions(Object *obj) 1609 { 1610 RISCVCPU *cpu = RISCV_CPU(obj); 1611 CPURISCVState *env = &cpu->env; 1612 const RISCVCPUMultiExtConfig *prop; 1613 1614 /* Enable RVG, RVJ and RVV that are disabled by default */ 1615 set_misa(env, env->misa_mxl, env->misa_ext | RVG | RVJ | RVV); 1616 1617 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1618 isa_ext_update_enabled(cpu, prop->offset, true); 1619 } 1620 1621 /* set vector version */ 1622 env->vext_ver = VEXT_VERSION_1_00_0; 1623 1624 /* Zfinx is not compatible with F. Disable it */ 1625 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zfinx), false); 1626 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zdinx), false); 1627 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinx), false); 1628 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zhinxmin), false); 1629 1630 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zce), false); 1631 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmp), false); 1632 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcmt), false); 1633 1634 if (env->misa_mxl != MXL_RV32) { 1635 isa_ext_update_enabled(cpu, CPU_CFG_OFFSET(ext_zcf), false); 1636 } 1637 } 1638 1639 static Property riscv_cpu_properties[] = { 1640 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1641 1642 #ifndef CONFIG_USER_ONLY 1643 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1644 #endif 1645 1646 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1647 1648 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1649 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1650 1651 /* 1652 * write_misa() is marked as experimental for now so mark 1653 * it with -x and default to 'false'. 1654 */ 1655 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1656 DEFINE_PROP_END_OF_LIST(), 1657 }; 1658 1659 static const gchar *riscv_gdb_arch_name(CPUState *cs) 1660 { 1661 RISCVCPU *cpu = RISCV_CPU(cs); 1662 CPURISCVState *env = &cpu->env; 1663 1664 switch (riscv_cpu_mxl(env)) { 1665 case MXL_RV32: 1666 return "riscv:rv32"; 1667 case MXL_RV64: 1668 case MXL_RV128: 1669 return "riscv:rv64"; 1670 default: 1671 g_assert_not_reached(); 1672 } 1673 } 1674 1675 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1676 { 1677 RISCVCPU *cpu = RISCV_CPU(cs); 1678 1679 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1680 return cpu->dyn_csr_xml; 1681 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1682 return cpu->dyn_vreg_xml; 1683 } 1684 1685 return NULL; 1686 } 1687 1688 #ifndef CONFIG_USER_ONLY 1689 static int64_t riscv_get_arch_id(CPUState *cs) 1690 { 1691 RISCVCPU *cpu = RISCV_CPU(cs); 1692 1693 return cpu->env.mhartid; 1694 } 1695 1696 #include "hw/core/sysemu-cpu-ops.h" 1697 1698 static const struct SysemuCPUOps riscv_sysemu_ops = { 1699 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1700 .write_elf64_note = riscv_cpu_write_elf64_note, 1701 .write_elf32_note = riscv_cpu_write_elf32_note, 1702 .legacy_vmsd = &vmstate_riscv_cpu, 1703 }; 1704 #endif 1705 1706 static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name, 1707 void *opaque, Error **errp) 1708 { 1709 bool dynamic_cpu = riscv_cpu_is_dynamic(obj); 1710 RISCVCPU *cpu = RISCV_CPU(obj); 1711 uint32_t prev_val = cpu->cfg.mvendorid; 1712 uint32_t value; 1713 1714 if (!visit_type_uint32(v, name, &value, errp)) { 1715 return; 1716 } 1717 1718 if (!dynamic_cpu && prev_val != value) { 1719 error_setg(errp, "Unable to change %s mvendorid (0x%x)", 1720 object_get_typename(obj), prev_val); 1721 return; 1722 } 1723 1724 cpu->cfg.mvendorid = value; 1725 } 1726 1727 static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name, 1728 void *opaque, Error **errp) 1729 { 1730 bool value = RISCV_CPU(obj)->cfg.mvendorid; 1731 1732 visit_type_bool(v, name, &value, errp); 1733 } 1734 1735 static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, 1736 void *opaque, Error **errp) 1737 { 1738 bool dynamic_cpu = riscv_cpu_is_dynamic(obj); 1739 RISCVCPU *cpu = RISCV_CPU(obj); 1740 uint64_t prev_val = cpu->cfg.mimpid; 1741 uint64_t value; 1742 1743 if (!visit_type_uint64(v, name, &value, errp)) { 1744 return; 1745 } 1746 1747 if (!dynamic_cpu && prev_val != value) { 1748 error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")", 1749 object_get_typename(obj), prev_val); 1750 return; 1751 } 1752 1753 cpu->cfg.mimpid = value; 1754 } 1755 1756 static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, 1757 void *opaque, Error **errp) 1758 { 1759 bool value = RISCV_CPU(obj)->cfg.mimpid; 1760 1761 visit_type_bool(v, name, &value, errp); 1762 } 1763 1764 static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, 1765 void *opaque, Error **errp) 1766 { 1767 bool dynamic_cpu = riscv_cpu_is_dynamic(obj); 1768 RISCVCPU *cpu = RISCV_CPU(obj); 1769 uint64_t prev_val = cpu->cfg.marchid; 1770 uint64_t value, invalid_val; 1771 uint32_t mxlen = 0; 1772 1773 if (!visit_type_uint64(v, name, &value, errp)) { 1774 return; 1775 } 1776 1777 if (!dynamic_cpu && prev_val != value) { 1778 error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", 1779 object_get_typename(obj), prev_val); 1780 return; 1781 } 1782 1783 switch (riscv_cpu_mxl(&cpu->env)) { 1784 case MXL_RV32: 1785 mxlen = 32; 1786 break; 1787 case MXL_RV64: 1788 case MXL_RV128: 1789 mxlen = 64; 1790 break; 1791 default: 1792 g_assert_not_reached(); 1793 } 1794 1795 invalid_val = 1LL << (mxlen - 1); 1796 1797 if (value == invalid_val) { 1798 error_setg(errp, "Unable to set marchid with MSB (%u) bit set " 1799 "and the remaining bits zero", mxlen); 1800 return; 1801 } 1802 1803 cpu->cfg.marchid = value; 1804 } 1805 1806 static void cpu_get_marchid(Object *obj, Visitor *v, const char *name, 1807 void *opaque, Error **errp) 1808 { 1809 bool value = RISCV_CPU(obj)->cfg.marchid; 1810 1811 visit_type_bool(v, name, &value, errp); 1812 } 1813 1814 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1815 { 1816 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1817 CPUClass *cc = CPU_CLASS(c); 1818 DeviceClass *dc = DEVICE_CLASS(c); 1819 ResettableClass *rc = RESETTABLE_CLASS(c); 1820 1821 device_class_set_parent_realize(dc, riscv_cpu_realize, 1822 &mcc->parent_realize); 1823 1824 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1825 &mcc->parent_phases); 1826 1827 cc->class_by_name = riscv_cpu_class_by_name; 1828 cc->has_work = riscv_cpu_has_work; 1829 cc->dump_state = riscv_cpu_dump_state; 1830 cc->set_pc = riscv_cpu_set_pc; 1831 cc->get_pc = riscv_cpu_get_pc; 1832 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1833 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1834 cc->gdb_num_core_regs = 33; 1835 cc->gdb_stop_before_watchpoint = true; 1836 cc->disas_set_info = riscv_cpu_disas_set_info; 1837 #ifndef CONFIG_USER_ONLY 1838 cc->sysemu_ops = &riscv_sysemu_ops; 1839 cc->get_arch_id = riscv_get_arch_id; 1840 #endif 1841 cc->gdb_arch_name = riscv_gdb_arch_name; 1842 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1843 1844 object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, 1845 cpu_set_mvendorid, NULL, NULL); 1846 1847 object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, 1848 cpu_set_mimpid, NULL, NULL); 1849 1850 object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, 1851 cpu_set_marchid, NULL, NULL); 1852 1853 device_class_set_props(dc, riscv_cpu_properties); 1854 } 1855 1856 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, 1857 int max_str_len) 1858 { 1859 char *old = *isa_str; 1860 char *new = *isa_str; 1861 int i; 1862 1863 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1864 if (isa_ext_is_enabled(cpu, isa_edata_arr[i].ext_enable_offset)) { 1865 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1866 g_free(old); 1867 old = new; 1868 } 1869 } 1870 1871 *isa_str = new; 1872 } 1873 1874 char *riscv_isa_string(RISCVCPU *cpu) 1875 { 1876 int i; 1877 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1878 char *isa_str = g_new(char, maxlen); 1879 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1880 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1881 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1882 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1883 } 1884 } 1885 *p = '\0'; 1886 if (!cpu->cfg.short_isa_string) { 1887 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1888 } 1889 return isa_str; 1890 } 1891 1892 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1893 { 1894 ObjectClass *class_a = (ObjectClass *)a; 1895 ObjectClass *class_b = (ObjectClass *)b; 1896 const char *name_a, *name_b; 1897 1898 name_a = object_class_get_name(class_a); 1899 name_b = object_class_get_name(class_b); 1900 return strcmp(name_a, name_b); 1901 } 1902 1903 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1904 { 1905 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1906 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1907 1908 qemu_printf("%.*s\n", len, typename); 1909 } 1910 1911 void riscv_cpu_list(void) 1912 { 1913 GSList *list; 1914 1915 list = object_class_get_list(TYPE_RISCV_CPU, false); 1916 list = g_slist_sort(list, riscv_cpu_list_compare); 1917 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1918 g_slist_free(list); 1919 } 1920 1921 #define DEFINE_CPU(type_name, initfn) \ 1922 { \ 1923 .name = type_name, \ 1924 .parent = TYPE_RISCV_CPU, \ 1925 .instance_init = initfn \ 1926 } 1927 1928 #define DEFINE_DYNAMIC_CPU(type_name, initfn) \ 1929 { \ 1930 .name = type_name, \ 1931 .parent = TYPE_RISCV_DYNAMIC_CPU, \ 1932 .instance_init = initfn \ 1933 } 1934 1935 static const TypeInfo riscv_cpu_type_infos[] = { 1936 { 1937 .name = TYPE_RISCV_CPU, 1938 .parent = TYPE_CPU, 1939 .instance_size = sizeof(RISCVCPU), 1940 .instance_align = __alignof(RISCVCPU), 1941 .instance_init = riscv_cpu_init, 1942 .instance_post_init = riscv_cpu_post_init, 1943 .abstract = true, 1944 .class_size = sizeof(RISCVCPUClass), 1945 .class_init = riscv_cpu_class_init, 1946 }, 1947 { 1948 .name = TYPE_RISCV_DYNAMIC_CPU, 1949 .parent = TYPE_RISCV_CPU, 1950 .abstract = true, 1951 }, 1952 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1953 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX, riscv_max_cpu_init), 1954 #if defined(TARGET_RISCV32) 1955 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1956 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1957 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1958 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1959 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1960 #elif defined(TARGET_RISCV64) 1961 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1962 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1963 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1964 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1965 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1966 DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), 1967 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1968 #endif 1969 }; 1970 1971 DEFINE_TYPES(riscv_cpu_type_infos) 1972