1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "pmu.h" 26 #include "internals.h" 27 #include "time_helper.h" 28 #include "exec/exec-all.h" 29 #include "qapi/error.h" 30 #include "qemu/error-report.h" 31 #include "hw/qdev-properties.h" 32 #include "migration/vmstate.h" 33 #include "fpu/softfloat-helpers.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_riscv.h" 36 37 /* RISC-V CPU definitions */ 38 39 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 40 (QEMU_VERSION_MINOR << 8) | \ 41 (QEMU_VERSION_MICRO)) 42 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 43 44 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 45 46 struct isa_ext_data { 47 const char *name; 48 bool multi_letter; 49 int min_version; 50 int ext_enable_offset; 51 }; 52 53 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ 54 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 55 56 /** 57 * Here are the ordering rules of extension naming defined by RISC-V 58 * specification : 59 * 1. All extensions should be separated from other multi-letter extensions 60 * by an underscore. 61 * 2. The first letter following the 'Z' conventionally indicates the most 62 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 63 * If multiple 'Z' extensions are named, they should be ordered first 64 * by category, then alphabetically within a category. 65 * 3. Standard supervisor-level extensions (starts with 'S') should be 66 * listed after standard unprivileged extensions. If multiple 67 * supervisor-level extensions are listed, they should be ordered 68 * alphabetically. 69 * 4. Non-standard extensions (starts with 'X') must be listed after all 70 * standard extensions. They must be separated from other multi-letter 71 * extensions by an underscore. 72 */ 73 static const struct isa_ext_data isa_edata_arr[] = { 74 ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), 75 ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), 76 ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), 77 ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), 78 ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), 79 ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), 80 ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), 81 ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), 82 ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), 83 ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), 84 ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), 85 ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), 86 ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), 87 ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), 88 ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), 89 ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), 90 ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), 91 ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), 92 ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), 93 ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), 94 ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), 95 ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), 96 ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), 97 ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), 98 ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), 99 ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), 100 ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), 101 ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), 102 ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), 103 ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), 104 ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), 105 ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), 106 ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), 107 ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), 108 ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), 109 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), 110 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), 111 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), 112 ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), 113 ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), 114 ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), 115 ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), 116 ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), 117 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 118 }; 119 120 static bool isa_ext_is_enabled(RISCVCPU *cpu, 121 const struct isa_ext_data *edata) 122 { 123 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 124 125 return *ext_enabled; 126 } 127 128 static void isa_ext_update_enabled(RISCVCPU *cpu, 129 const struct isa_ext_data *edata, bool en) 130 { 131 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 132 133 *ext_enabled = en; 134 } 135 136 const char * const riscv_int_regnames[] = { 137 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 138 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 139 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 140 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 141 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 142 }; 143 144 const char * const riscv_int_regnamesh[] = { 145 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 146 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 147 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 148 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 149 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 150 "x30h/t5h", "x31h/t6h" 151 }; 152 153 const char * const riscv_fpr_regnames[] = { 154 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 155 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 156 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 157 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 158 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 159 "f30/ft10", "f31/ft11" 160 }; 161 162 static const char * const riscv_excp_names[] = { 163 "misaligned_fetch", 164 "fault_fetch", 165 "illegal_instruction", 166 "breakpoint", 167 "misaligned_load", 168 "fault_load", 169 "misaligned_store", 170 "fault_store", 171 "user_ecall", 172 "supervisor_ecall", 173 "hypervisor_ecall", 174 "machine_ecall", 175 "exec_page_fault", 176 "load_page_fault", 177 "reserved", 178 "store_page_fault", 179 "reserved", 180 "reserved", 181 "reserved", 182 "reserved", 183 "guest_exec_page_fault", 184 "guest_load_page_fault", 185 "reserved", 186 "guest_store_page_fault", 187 }; 188 189 static const char * const riscv_intr_names[] = { 190 "u_software", 191 "s_software", 192 "vs_software", 193 "m_software", 194 "u_timer", 195 "s_timer", 196 "vs_timer", 197 "m_timer", 198 "u_external", 199 "s_external", 200 "vs_external", 201 "m_external", 202 "reserved", 203 "reserved", 204 "reserved", 205 "reserved" 206 }; 207 208 static void register_cpu_props(DeviceState *dev); 209 210 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 211 { 212 if (async) { 213 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 214 riscv_intr_names[cause] : "(unknown)"; 215 } else { 216 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 217 riscv_excp_names[cause] : "(unknown)"; 218 } 219 } 220 221 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 222 { 223 env->misa_mxl_max = env->misa_mxl = mxl; 224 env->misa_ext_mask = env->misa_ext = ext; 225 } 226 227 static void set_priv_version(CPURISCVState *env, int priv_ver) 228 { 229 env->priv_ver = priv_ver; 230 } 231 232 static void set_vext_version(CPURISCVState *env, int vext_ver) 233 { 234 env->vext_ver = vext_ver; 235 } 236 237 static void riscv_any_cpu_init(Object *obj) 238 { 239 CPURISCVState *env = &RISCV_CPU(obj)->env; 240 #if defined(TARGET_RISCV32) 241 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 242 #elif defined(TARGET_RISCV64) 243 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 244 #endif 245 set_priv_version(env, PRIV_VERSION_1_12_0); 246 register_cpu_props(DEVICE(obj)); 247 } 248 249 #if defined(TARGET_RISCV64) 250 static void rv64_base_cpu_init(Object *obj) 251 { 252 CPURISCVState *env = &RISCV_CPU(obj)->env; 253 /* We set this in the realise function */ 254 set_misa(env, MXL_RV64, 0); 255 register_cpu_props(DEVICE(obj)); 256 /* Set latest version of privileged specification */ 257 set_priv_version(env, PRIV_VERSION_1_12_0); 258 } 259 260 static void rv64_sifive_u_cpu_init(Object *obj) 261 { 262 CPURISCVState *env = &RISCV_CPU(obj)->env; 263 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 264 register_cpu_props(DEVICE(obj)); 265 set_priv_version(env, PRIV_VERSION_1_10_0); 266 } 267 268 static void rv64_sifive_e_cpu_init(Object *obj) 269 { 270 CPURISCVState *env = &RISCV_CPU(obj)->env; 271 RISCVCPU *cpu = RISCV_CPU(obj); 272 273 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 274 register_cpu_props(DEVICE(obj)); 275 set_priv_version(env, PRIV_VERSION_1_10_0); 276 cpu->cfg.mmu = false; 277 } 278 279 static void rv128_base_cpu_init(Object *obj) 280 { 281 if (qemu_tcg_mttcg_enabled()) { 282 /* Missing 128-bit aligned atomics */ 283 error_report("128-bit RISC-V currently does not work with Multi " 284 "Threaded TCG. Please use: -accel tcg,thread=single"); 285 exit(EXIT_FAILURE); 286 } 287 CPURISCVState *env = &RISCV_CPU(obj)->env; 288 /* We set this in the realise function */ 289 set_misa(env, MXL_RV128, 0); 290 register_cpu_props(DEVICE(obj)); 291 /* Set latest version of privileged specification */ 292 set_priv_version(env, PRIV_VERSION_1_12_0); 293 } 294 #else 295 static void rv32_base_cpu_init(Object *obj) 296 { 297 CPURISCVState *env = &RISCV_CPU(obj)->env; 298 /* We set this in the realise function */ 299 set_misa(env, MXL_RV32, 0); 300 register_cpu_props(DEVICE(obj)); 301 /* Set latest version of privileged specification */ 302 set_priv_version(env, PRIV_VERSION_1_12_0); 303 } 304 305 static void rv32_sifive_u_cpu_init(Object *obj) 306 { 307 CPURISCVState *env = &RISCV_CPU(obj)->env; 308 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 309 register_cpu_props(DEVICE(obj)); 310 set_priv_version(env, PRIV_VERSION_1_10_0); 311 } 312 313 static void rv32_sifive_e_cpu_init(Object *obj) 314 { 315 CPURISCVState *env = &RISCV_CPU(obj)->env; 316 RISCVCPU *cpu = RISCV_CPU(obj); 317 318 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 319 register_cpu_props(DEVICE(obj)); 320 set_priv_version(env, PRIV_VERSION_1_10_0); 321 cpu->cfg.mmu = false; 322 } 323 324 static void rv32_ibex_cpu_init(Object *obj) 325 { 326 CPURISCVState *env = &RISCV_CPU(obj)->env; 327 RISCVCPU *cpu = RISCV_CPU(obj); 328 329 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 330 register_cpu_props(DEVICE(obj)); 331 set_priv_version(env, PRIV_VERSION_1_11_0); 332 cpu->cfg.mmu = false; 333 cpu->cfg.epmp = true; 334 } 335 336 static void rv32_imafcu_nommu_cpu_init(Object *obj) 337 { 338 CPURISCVState *env = &RISCV_CPU(obj)->env; 339 RISCVCPU *cpu = RISCV_CPU(obj); 340 341 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 342 register_cpu_props(DEVICE(obj)); 343 set_priv_version(env, PRIV_VERSION_1_10_0); 344 cpu->cfg.mmu = false; 345 } 346 #endif 347 348 #if defined(CONFIG_KVM) 349 static void riscv_host_cpu_init(Object *obj) 350 { 351 CPURISCVState *env = &RISCV_CPU(obj)->env; 352 #if defined(TARGET_RISCV32) 353 set_misa(env, MXL_RV32, 0); 354 #elif defined(TARGET_RISCV64) 355 set_misa(env, MXL_RV64, 0); 356 #endif 357 register_cpu_props(DEVICE(obj)); 358 } 359 #endif 360 361 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 362 { 363 ObjectClass *oc; 364 char *typename; 365 char **cpuname; 366 367 cpuname = g_strsplit(cpu_model, ",", 1); 368 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 369 oc = object_class_by_name(typename); 370 g_strfreev(cpuname); 371 g_free(typename); 372 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 373 object_class_is_abstract(oc)) { 374 return NULL; 375 } 376 return oc; 377 } 378 379 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 380 { 381 RISCVCPU *cpu = RISCV_CPU(cs); 382 CPURISCVState *env = &cpu->env; 383 int i; 384 385 #if !defined(CONFIG_USER_ONLY) 386 if (riscv_has_ext(env, RVH)) { 387 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 388 } 389 #endif 390 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 391 #ifndef CONFIG_USER_ONLY 392 { 393 static const int dump_csrs[] = { 394 CSR_MHARTID, 395 CSR_MSTATUS, 396 CSR_MSTATUSH, 397 /* 398 * CSR_SSTATUS is intentionally omitted here as its value 399 * can be figured out by looking at CSR_MSTATUS 400 */ 401 CSR_HSTATUS, 402 CSR_VSSTATUS, 403 CSR_MIP, 404 CSR_MIE, 405 CSR_MIDELEG, 406 CSR_HIDELEG, 407 CSR_MEDELEG, 408 CSR_HEDELEG, 409 CSR_MTVEC, 410 CSR_STVEC, 411 CSR_VSTVEC, 412 CSR_MEPC, 413 CSR_SEPC, 414 CSR_VSEPC, 415 CSR_MCAUSE, 416 CSR_SCAUSE, 417 CSR_VSCAUSE, 418 CSR_MTVAL, 419 CSR_STVAL, 420 CSR_HTVAL, 421 CSR_MTVAL2, 422 CSR_MSCRATCH, 423 CSR_SSCRATCH, 424 CSR_SATP, 425 CSR_MMTE, 426 CSR_UPMBASE, 427 CSR_UPMMASK, 428 CSR_SPMBASE, 429 CSR_SPMMASK, 430 CSR_MPMBASE, 431 CSR_MPMMASK, 432 }; 433 434 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 435 int csrno = dump_csrs[i]; 436 target_ulong val = 0; 437 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 438 439 /* 440 * Rely on the smode, hmode, etc, predicates within csr.c 441 * to do the filtering of the registers that are present. 442 */ 443 if (res == RISCV_EXCP_NONE) { 444 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 445 csr_ops[csrno].name, val); 446 } 447 } 448 } 449 #endif 450 451 for (i = 0; i < 32; i++) { 452 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 453 riscv_int_regnames[i], env->gpr[i]); 454 if ((i & 3) == 3) { 455 qemu_fprintf(f, "\n"); 456 } 457 } 458 if (flags & CPU_DUMP_FPU) { 459 for (i = 0; i < 32; i++) { 460 qemu_fprintf(f, " %-8s %016" PRIx64, 461 riscv_fpr_regnames[i], env->fpr[i]); 462 if ((i & 3) == 3) { 463 qemu_fprintf(f, "\n"); 464 } 465 } 466 } 467 } 468 469 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 470 { 471 RISCVCPU *cpu = RISCV_CPU(cs); 472 CPURISCVState *env = &cpu->env; 473 474 if (env->xl == MXL_RV32) { 475 env->pc = (int32_t)value; 476 } else { 477 env->pc = value; 478 } 479 } 480 481 static vaddr riscv_cpu_get_pc(CPUState *cs) 482 { 483 RISCVCPU *cpu = RISCV_CPU(cs); 484 CPURISCVState *env = &cpu->env; 485 486 /* Match cpu_get_tb_cpu_state. */ 487 if (env->xl == MXL_RV32) { 488 return env->pc & UINT32_MAX; 489 } 490 return env->pc; 491 } 492 493 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 494 const TranslationBlock *tb) 495 { 496 RISCVCPU *cpu = RISCV_CPU(cs); 497 CPURISCVState *env = &cpu->env; 498 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 499 500 if (xl == MXL_RV32) { 501 env->pc = (int32_t)tb_pc(tb); 502 } else { 503 env->pc = tb_pc(tb); 504 } 505 } 506 507 static bool riscv_cpu_has_work(CPUState *cs) 508 { 509 #ifndef CONFIG_USER_ONLY 510 RISCVCPU *cpu = RISCV_CPU(cs); 511 CPURISCVState *env = &cpu->env; 512 /* 513 * Definition of the WFI instruction requires it to ignore the privilege 514 * mode and delegation registers, but respect individual enables 515 */ 516 return riscv_cpu_all_pending(env) != 0; 517 #else 518 return true; 519 #endif 520 } 521 522 static void riscv_restore_state_to_opc(CPUState *cs, 523 const TranslationBlock *tb, 524 const uint64_t *data) 525 { 526 RISCVCPU *cpu = RISCV_CPU(cs); 527 CPURISCVState *env = &cpu->env; 528 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 529 530 if (xl == MXL_RV32) { 531 env->pc = (int32_t)data[0]; 532 } else { 533 env->pc = data[0]; 534 } 535 env->bins = data[1]; 536 } 537 538 static void riscv_cpu_reset_hold(Object *obj) 539 { 540 #ifndef CONFIG_USER_ONLY 541 uint8_t iprio; 542 int i, irq, rdzero; 543 #endif 544 CPUState *cs = CPU(obj); 545 RISCVCPU *cpu = RISCV_CPU(cs); 546 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 547 CPURISCVState *env = &cpu->env; 548 549 if (mcc->parent_phases.hold) { 550 mcc->parent_phases.hold(obj); 551 } 552 #ifndef CONFIG_USER_ONLY 553 env->misa_mxl = env->misa_mxl_max; 554 env->priv = PRV_M; 555 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 556 if (env->misa_mxl > MXL_RV32) { 557 /* 558 * The reset status of SXL/UXL is undefined, but mstatus is WARL 559 * and we must ensure that the value after init is valid for read. 560 */ 561 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 562 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 563 if (riscv_has_ext(env, RVH)) { 564 env->vsstatus = set_field(env->vsstatus, 565 MSTATUS64_SXL, env->misa_mxl); 566 env->vsstatus = set_field(env->vsstatus, 567 MSTATUS64_UXL, env->misa_mxl); 568 env->mstatus_hs = set_field(env->mstatus_hs, 569 MSTATUS64_SXL, env->misa_mxl); 570 env->mstatus_hs = set_field(env->mstatus_hs, 571 MSTATUS64_UXL, env->misa_mxl); 572 } 573 } 574 env->mcause = 0; 575 env->miclaim = MIP_SGEIP; 576 env->pc = env->resetvec; 577 env->bins = 0; 578 env->two_stage_lookup = false; 579 580 /* Initialized default priorities of local interrupts. */ 581 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 582 iprio = riscv_cpu_default_priority(i); 583 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 584 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 585 env->hviprio[i] = 0; 586 } 587 i = 0; 588 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 589 if (!rdzero) { 590 env->hviprio[irq] = env->miprio[irq]; 591 } 592 i++; 593 } 594 /* mmte is supposed to have pm.current hardwired to 1 */ 595 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 596 #endif 597 env->xl = riscv_cpu_mxl(env); 598 riscv_cpu_update_mask(env); 599 cs->exception_index = RISCV_EXCP_NONE; 600 env->load_res = -1; 601 set_default_nan_mode(1, &env->fp_status); 602 603 #ifndef CONFIG_USER_ONLY 604 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 605 riscv_trigger_init(env); 606 } 607 608 if (kvm_enabled()) { 609 kvm_riscv_reset_vcpu(cpu); 610 } 611 #endif 612 } 613 614 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 615 { 616 RISCVCPU *cpu = RISCV_CPU(s); 617 618 switch (riscv_cpu_mxl(&cpu->env)) { 619 case MXL_RV32: 620 info->print_insn = print_insn_riscv32; 621 break; 622 case MXL_RV64: 623 info->print_insn = print_insn_riscv64; 624 break; 625 case MXL_RV128: 626 info->print_insn = print_insn_riscv128; 627 break; 628 default: 629 g_assert_not_reached(); 630 } 631 } 632 633 /* 634 * Check consistency between chosen extensions while setting 635 * cpu->cfg accordingly, doing a set_misa() in the end. 636 */ 637 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 638 { 639 CPURISCVState *env = &cpu->env; 640 uint32_t ext = 0; 641 642 /* Do some ISA extension error checking */ 643 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 644 cpu->cfg.ext_a && cpu->cfg.ext_f && 645 cpu->cfg.ext_d && 646 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 647 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 648 cpu->cfg.ext_i = true; 649 cpu->cfg.ext_m = true; 650 cpu->cfg.ext_a = true; 651 cpu->cfg.ext_f = true; 652 cpu->cfg.ext_d = true; 653 cpu->cfg.ext_icsr = true; 654 cpu->cfg.ext_ifencei = true; 655 } 656 657 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 658 error_setg(errp, 659 "I and E extensions are incompatible"); 660 return; 661 } 662 663 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 664 error_setg(errp, 665 "Either I or E extension must be set"); 666 return; 667 } 668 669 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 670 error_setg(errp, 671 "Setting S extension without U extension is illegal"); 672 return; 673 } 674 675 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { 676 error_setg(errp, 677 "H depends on an I base integer ISA with 32 x registers"); 678 return; 679 } 680 681 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 682 error_setg(errp, "H extension implicitly requires S-mode"); 683 return; 684 } 685 686 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 687 error_setg(errp, "F extension requires Zicsr"); 688 return; 689 } 690 691 if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { 692 error_setg(errp, "Zawrs extension requires A extension"); 693 return; 694 } 695 696 if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { 697 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 698 return; 699 } 700 701 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 702 error_setg(errp, "D extension requires F extension"); 703 return; 704 } 705 706 if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { 707 error_setg(errp, "V extension requires D extension"); 708 return; 709 } 710 711 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 712 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 713 return; 714 } 715 716 /* Set the ISA extensions, checks should have happened above */ 717 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || 718 cpu->cfg.ext_zhinxmin) { 719 cpu->cfg.ext_zfinx = true; 720 } 721 722 if (cpu->cfg.ext_zfinx) { 723 if (!cpu->cfg.ext_icsr) { 724 error_setg(errp, "Zfinx extension requires Zicsr"); 725 return; 726 } 727 if (cpu->cfg.ext_f) { 728 error_setg(errp, 729 "Zfinx cannot be supported together with F extension"); 730 return; 731 } 732 } 733 734 if (cpu->cfg.ext_zk) { 735 cpu->cfg.ext_zkn = true; 736 cpu->cfg.ext_zkr = true; 737 cpu->cfg.ext_zkt = true; 738 } 739 740 if (cpu->cfg.ext_zkn) { 741 cpu->cfg.ext_zbkb = true; 742 cpu->cfg.ext_zbkc = true; 743 cpu->cfg.ext_zbkx = true; 744 cpu->cfg.ext_zkne = true; 745 cpu->cfg.ext_zknd = true; 746 cpu->cfg.ext_zknh = true; 747 } 748 749 if (cpu->cfg.ext_zks) { 750 cpu->cfg.ext_zbkb = true; 751 cpu->cfg.ext_zbkc = true; 752 cpu->cfg.ext_zbkx = true; 753 cpu->cfg.ext_zksed = true; 754 cpu->cfg.ext_zksh = true; 755 } 756 757 if (cpu->cfg.ext_i) { 758 ext |= RVI; 759 } 760 if (cpu->cfg.ext_e) { 761 ext |= RVE; 762 } 763 if (cpu->cfg.ext_m) { 764 ext |= RVM; 765 } 766 if (cpu->cfg.ext_a) { 767 ext |= RVA; 768 } 769 if (cpu->cfg.ext_f) { 770 ext |= RVF; 771 } 772 if (cpu->cfg.ext_d) { 773 ext |= RVD; 774 } 775 if (cpu->cfg.ext_c) { 776 ext |= RVC; 777 } 778 if (cpu->cfg.ext_s) { 779 ext |= RVS; 780 } 781 if (cpu->cfg.ext_u) { 782 ext |= RVU; 783 } 784 if (cpu->cfg.ext_h) { 785 ext |= RVH; 786 } 787 if (cpu->cfg.ext_v) { 788 int vext_version = VEXT_VERSION_1_00_0; 789 ext |= RVV; 790 if (!is_power_of_2(cpu->cfg.vlen)) { 791 error_setg(errp, 792 "Vector extension VLEN must be power of 2"); 793 return; 794 } 795 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 796 error_setg(errp, 797 "Vector extension implementation only supports VLEN " 798 "in the range [128, %d]", RV_VLEN_MAX); 799 return; 800 } 801 if (!is_power_of_2(cpu->cfg.elen)) { 802 error_setg(errp, 803 "Vector extension ELEN must be power of 2"); 804 return; 805 } 806 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 807 error_setg(errp, 808 "Vector extension implementation only supports ELEN " 809 "in the range [8, 64]"); 810 return; 811 } 812 if (cpu->cfg.vext_spec) { 813 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 814 vext_version = VEXT_VERSION_1_00_0; 815 } else { 816 error_setg(errp, 817 "Unsupported vector spec version '%s'", 818 cpu->cfg.vext_spec); 819 return; 820 } 821 } else { 822 qemu_log("vector version is not specified, " 823 "use the default value v1.0\n"); 824 } 825 set_vext_version(env, vext_version); 826 } 827 if (cpu->cfg.ext_j) { 828 ext |= RVJ; 829 } 830 831 set_misa(env, env->misa_mxl, ext); 832 } 833 834 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 835 { 836 CPUState *cs = CPU(dev); 837 RISCVCPU *cpu = RISCV_CPU(dev); 838 CPURISCVState *env = &cpu->env; 839 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 840 CPUClass *cc = CPU_CLASS(mcc); 841 int i, priv_version = -1; 842 Error *local_err = NULL; 843 844 cpu_exec_realizefn(cs, &local_err); 845 if (local_err != NULL) { 846 error_propagate(errp, local_err); 847 return; 848 } 849 850 if (cpu->cfg.priv_spec) { 851 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 852 priv_version = PRIV_VERSION_1_12_0; 853 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 854 priv_version = PRIV_VERSION_1_11_0; 855 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 856 priv_version = PRIV_VERSION_1_10_0; 857 } else { 858 error_setg(errp, 859 "Unsupported privilege spec version '%s'", 860 cpu->cfg.priv_spec); 861 return; 862 } 863 } 864 865 if (priv_version >= PRIV_VERSION_1_10_0) { 866 set_priv_version(env, priv_version); 867 } 868 869 /* Force disable extensions if priv spec version does not match */ 870 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 871 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 872 (env->priv_ver < isa_edata_arr[i].min_version)) { 873 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 874 #ifndef CONFIG_USER_ONLY 875 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 876 " because privilege spec version does not match", 877 isa_edata_arr[i].name, env->mhartid); 878 #else 879 warn_report("disabling %s extension because " 880 "privilege spec version does not match", 881 isa_edata_arr[i].name); 882 #endif 883 } 884 } 885 886 if (cpu->cfg.mmu) { 887 riscv_set_feature(env, RISCV_FEATURE_MMU); 888 } 889 890 if (cpu->cfg.pmp) { 891 riscv_set_feature(env, RISCV_FEATURE_PMP); 892 893 /* 894 * Enhanced PMP should only be available 895 * on harts with PMP support 896 */ 897 if (cpu->cfg.epmp) { 898 riscv_set_feature(env, RISCV_FEATURE_EPMP); 899 } 900 } 901 902 if (cpu->cfg.debug) { 903 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 904 } 905 906 907 #ifndef CONFIG_USER_ONLY 908 if (cpu->cfg.ext_sstc) { 909 riscv_timer_init(cpu); 910 } 911 #endif /* CONFIG_USER_ONLY */ 912 913 /* Validate that MISA_MXL is set properly. */ 914 switch (env->misa_mxl_max) { 915 #ifdef TARGET_RISCV64 916 case MXL_RV64: 917 case MXL_RV128: 918 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 919 break; 920 #endif 921 case MXL_RV32: 922 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 923 break; 924 default: 925 g_assert_not_reached(); 926 } 927 assert(env->misa_mxl_max == env->misa_mxl); 928 929 riscv_cpu_validate_set_extensions(cpu, &local_err); 930 if (local_err != NULL) { 931 error_propagate(errp, local_err); 932 return; 933 } 934 935 #ifndef CONFIG_USER_ONLY 936 if (cpu->cfg.pmu_num) { 937 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 938 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 939 riscv_pmu_timer_cb, cpu); 940 } 941 } 942 #endif 943 944 riscv_cpu_register_gdb_regs_for_features(cs); 945 946 qemu_init_vcpu(cs); 947 cpu_reset(cs); 948 949 mcc->parent_realize(dev, errp); 950 } 951 952 #ifndef CONFIG_USER_ONLY 953 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 954 { 955 RISCVCPU *cpu = RISCV_CPU(opaque); 956 CPURISCVState *env = &cpu->env; 957 958 if (irq < IRQ_LOCAL_MAX) { 959 switch (irq) { 960 case IRQ_U_SOFT: 961 case IRQ_S_SOFT: 962 case IRQ_VS_SOFT: 963 case IRQ_M_SOFT: 964 case IRQ_U_TIMER: 965 case IRQ_S_TIMER: 966 case IRQ_VS_TIMER: 967 case IRQ_M_TIMER: 968 case IRQ_U_EXT: 969 case IRQ_VS_EXT: 970 case IRQ_M_EXT: 971 if (kvm_enabled()) { 972 kvm_riscv_set_irq(cpu, irq, level); 973 } else { 974 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 975 } 976 break; 977 case IRQ_S_EXT: 978 if (kvm_enabled()) { 979 kvm_riscv_set_irq(cpu, irq, level); 980 } else { 981 env->external_seip = level; 982 riscv_cpu_update_mip(cpu, 1 << irq, 983 BOOL_TO_MASK(level | env->software_seip)); 984 } 985 break; 986 default: 987 g_assert_not_reached(); 988 } 989 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 990 /* Require H-extension for handling guest local interrupts */ 991 if (!riscv_has_ext(env, RVH)) { 992 g_assert_not_reached(); 993 } 994 995 /* Compute bit position in HGEIP CSR */ 996 irq = irq - IRQ_LOCAL_MAX + 1; 997 if (env->geilen < irq) { 998 g_assert_not_reached(); 999 } 1000 1001 /* Update HGEIP CSR */ 1002 env->hgeip &= ~((target_ulong)1 << irq); 1003 if (level) { 1004 env->hgeip |= (target_ulong)1 << irq; 1005 } 1006 1007 /* Update mip.SGEIP bit */ 1008 riscv_cpu_update_mip(cpu, MIP_SGEIP, 1009 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1010 } else { 1011 g_assert_not_reached(); 1012 } 1013 } 1014 #endif /* CONFIG_USER_ONLY */ 1015 1016 static void riscv_cpu_init(Object *obj) 1017 { 1018 RISCVCPU *cpu = RISCV_CPU(obj); 1019 1020 cpu->cfg.ext_ifencei = true; 1021 cpu->cfg.ext_icsr = true; 1022 cpu->cfg.mmu = true; 1023 cpu->cfg.pmp = true; 1024 1025 cpu_set_cpustate_pointers(cpu); 1026 1027 #ifndef CONFIG_USER_ONLY 1028 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1029 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1030 #endif /* CONFIG_USER_ONLY */ 1031 } 1032 1033 static Property riscv_cpu_extensions[] = { 1034 /* Defaults for standard extensions */ 1035 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 1036 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 1037 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1038 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 1039 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 1040 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 1041 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 1042 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 1043 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 1044 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1045 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1046 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1047 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1048 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1049 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1050 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1051 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1052 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1053 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1054 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1055 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1056 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1057 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1058 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1059 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1060 1061 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1062 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1063 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1064 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1065 1066 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1067 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1068 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1069 1070 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1071 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1072 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1073 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1074 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1075 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1076 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1077 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1078 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1079 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1080 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1081 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1082 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1083 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1084 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1085 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1086 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1087 1088 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1089 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1090 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1091 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1092 1093 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1094 1095 /* Vendor-specific custom extensions */ 1096 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1097 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1098 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1099 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1100 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1101 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1102 1103 /* These are experimental so mark with 'x-' */ 1104 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1105 /* ePMP 0.9.3 */ 1106 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1107 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1108 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1109 1110 DEFINE_PROP_END_OF_LIST(), 1111 }; 1112 1113 /* 1114 * Register CPU props based on env.misa_ext. If a non-zero 1115 * value was set, register only the required cpu->cfg.ext_* 1116 * properties and leave. env.misa_ext = 0 means that we want 1117 * all the default properties to be registered. 1118 */ 1119 static void register_cpu_props(DeviceState *dev) 1120 { 1121 RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); 1122 uint32_t misa_ext = cpu->env.misa_ext; 1123 Property *prop; 1124 1125 /* 1126 * If misa_ext is not zero, set cfg properties now to 1127 * allow them to be read during riscv_cpu_realize() 1128 * later on. 1129 */ 1130 if (cpu->env.misa_ext != 0) { 1131 cpu->cfg.ext_i = misa_ext & RVI; 1132 cpu->cfg.ext_e = misa_ext & RVE; 1133 cpu->cfg.ext_m = misa_ext & RVM; 1134 cpu->cfg.ext_a = misa_ext & RVA; 1135 cpu->cfg.ext_f = misa_ext & RVF; 1136 cpu->cfg.ext_d = misa_ext & RVD; 1137 cpu->cfg.ext_v = misa_ext & RVV; 1138 cpu->cfg.ext_c = misa_ext & RVC; 1139 cpu->cfg.ext_s = misa_ext & RVS; 1140 cpu->cfg.ext_u = misa_ext & RVU; 1141 cpu->cfg.ext_h = misa_ext & RVH; 1142 cpu->cfg.ext_j = misa_ext & RVJ; 1143 1144 /* 1145 * We don't want to set the default riscv_cpu_extensions 1146 * in this case. 1147 */ 1148 return; 1149 } 1150 1151 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1152 qdev_property_add_static(dev, prop); 1153 } 1154 } 1155 1156 static Property riscv_cpu_properties[] = { 1157 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1158 1159 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1160 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1161 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1162 1163 #ifndef CONFIG_USER_ONLY 1164 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1165 #endif 1166 1167 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1168 1169 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1170 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1171 DEFINE_PROP_END_OF_LIST(), 1172 }; 1173 1174 static gchar *riscv_gdb_arch_name(CPUState *cs) 1175 { 1176 RISCVCPU *cpu = RISCV_CPU(cs); 1177 CPURISCVState *env = &cpu->env; 1178 1179 switch (riscv_cpu_mxl(env)) { 1180 case MXL_RV32: 1181 return g_strdup("riscv:rv32"); 1182 case MXL_RV64: 1183 case MXL_RV128: 1184 return g_strdup("riscv:rv64"); 1185 default: 1186 g_assert_not_reached(); 1187 } 1188 } 1189 1190 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1191 { 1192 RISCVCPU *cpu = RISCV_CPU(cs); 1193 1194 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1195 return cpu->dyn_csr_xml; 1196 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1197 return cpu->dyn_vreg_xml; 1198 } 1199 1200 return NULL; 1201 } 1202 1203 #ifndef CONFIG_USER_ONLY 1204 #include "hw/core/sysemu-cpu-ops.h" 1205 1206 static const struct SysemuCPUOps riscv_sysemu_ops = { 1207 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1208 .write_elf64_note = riscv_cpu_write_elf64_note, 1209 .write_elf32_note = riscv_cpu_write_elf32_note, 1210 .legacy_vmsd = &vmstate_riscv_cpu, 1211 }; 1212 #endif 1213 1214 #include "hw/core/tcg-cpu-ops.h" 1215 1216 static const struct TCGCPUOps riscv_tcg_ops = { 1217 .initialize = riscv_translate_init, 1218 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1219 .restore_state_to_opc = riscv_restore_state_to_opc, 1220 1221 #ifndef CONFIG_USER_ONLY 1222 .tlb_fill = riscv_cpu_tlb_fill, 1223 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1224 .do_interrupt = riscv_cpu_do_interrupt, 1225 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1226 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1227 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1228 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1229 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1230 #endif /* !CONFIG_USER_ONLY */ 1231 }; 1232 1233 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1234 { 1235 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1236 CPUClass *cc = CPU_CLASS(c); 1237 DeviceClass *dc = DEVICE_CLASS(c); 1238 ResettableClass *rc = RESETTABLE_CLASS(c); 1239 1240 device_class_set_parent_realize(dc, riscv_cpu_realize, 1241 &mcc->parent_realize); 1242 1243 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1244 &mcc->parent_phases); 1245 1246 cc->class_by_name = riscv_cpu_class_by_name; 1247 cc->has_work = riscv_cpu_has_work; 1248 cc->dump_state = riscv_cpu_dump_state; 1249 cc->set_pc = riscv_cpu_set_pc; 1250 cc->get_pc = riscv_cpu_get_pc; 1251 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1252 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1253 cc->gdb_num_core_regs = 33; 1254 cc->gdb_stop_before_watchpoint = true; 1255 cc->disas_set_info = riscv_cpu_disas_set_info; 1256 #ifndef CONFIG_USER_ONLY 1257 cc->sysemu_ops = &riscv_sysemu_ops; 1258 #endif 1259 cc->gdb_arch_name = riscv_gdb_arch_name; 1260 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1261 cc->tcg_ops = &riscv_tcg_ops; 1262 1263 device_class_set_props(dc, riscv_cpu_properties); 1264 } 1265 1266 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1267 { 1268 char *old = *isa_str; 1269 char *new = *isa_str; 1270 int i; 1271 1272 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1273 if (isa_edata_arr[i].multi_letter && 1274 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1275 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1276 g_free(old); 1277 old = new; 1278 } 1279 } 1280 1281 *isa_str = new; 1282 } 1283 1284 char *riscv_isa_string(RISCVCPU *cpu) 1285 { 1286 int i; 1287 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1288 char *isa_str = g_new(char, maxlen); 1289 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1290 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1291 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1292 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1293 } 1294 } 1295 *p = '\0'; 1296 if (!cpu->cfg.short_isa_string) { 1297 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1298 } 1299 return isa_str; 1300 } 1301 1302 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1303 { 1304 ObjectClass *class_a = (ObjectClass *)a; 1305 ObjectClass *class_b = (ObjectClass *)b; 1306 const char *name_a, *name_b; 1307 1308 name_a = object_class_get_name(class_a); 1309 name_b = object_class_get_name(class_b); 1310 return strcmp(name_a, name_b); 1311 } 1312 1313 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1314 { 1315 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1316 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1317 1318 qemu_printf("%.*s\n", len, typename); 1319 } 1320 1321 void riscv_cpu_list(void) 1322 { 1323 GSList *list; 1324 1325 list = object_class_get_list(TYPE_RISCV_CPU, false); 1326 list = g_slist_sort(list, riscv_cpu_list_compare); 1327 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1328 g_slist_free(list); 1329 } 1330 1331 #define DEFINE_CPU(type_name, initfn) \ 1332 { \ 1333 .name = type_name, \ 1334 .parent = TYPE_RISCV_CPU, \ 1335 .instance_init = initfn \ 1336 } 1337 1338 static const TypeInfo riscv_cpu_type_infos[] = { 1339 { 1340 .name = TYPE_RISCV_CPU, 1341 .parent = TYPE_CPU, 1342 .instance_size = sizeof(RISCVCPU), 1343 .instance_align = __alignof__(RISCVCPU), 1344 .instance_init = riscv_cpu_init, 1345 .abstract = true, 1346 .class_size = sizeof(RISCVCPUClass), 1347 .class_init = riscv_cpu_class_init, 1348 }, 1349 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1350 #if defined(CONFIG_KVM) 1351 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1352 #endif 1353 #if defined(TARGET_RISCV32) 1354 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1355 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1356 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1357 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1358 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1359 #elif defined(TARGET_RISCV64) 1360 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1361 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1362 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1363 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1364 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1365 #endif 1366 }; 1367 1368 DEFINE_TYPES(riscv_cpu_type_infos) 1369