1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "exec/exec-all.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 #include "fpu/softfloat-helpers.h" 31 32 /* RISC-V CPU definitions */ 33 34 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 35 36 const char * const riscv_int_regnames[] = { 37 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 38 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 39 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 40 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 41 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 42 }; 43 44 const char * const riscv_fpr_regnames[] = { 45 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 46 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 47 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 48 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 49 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 50 "f30/ft10", "f31/ft11" 51 }; 52 53 const char * const riscv_excp_names[] = { 54 "misaligned_fetch", 55 "fault_fetch", 56 "illegal_instruction", 57 "breakpoint", 58 "misaligned_load", 59 "fault_load", 60 "misaligned_store", 61 "fault_store", 62 "user_ecall", 63 "supervisor_ecall", 64 "hypervisor_ecall", 65 "machine_ecall", 66 "exec_page_fault", 67 "load_page_fault", 68 "reserved", 69 "store_page_fault", 70 "reserved", 71 "reserved", 72 "reserved", 73 "reserved", 74 "guest_exec_page_fault", 75 "guest_load_page_fault", 76 "reserved", 77 "guest_store_page_fault", 78 }; 79 80 const char * const riscv_intr_names[] = { 81 "u_software", 82 "s_software", 83 "vs_software", 84 "m_software", 85 "u_timer", 86 "s_timer", 87 "vs_timer", 88 "m_timer", 89 "u_external", 90 "vs_external", 91 "h_external", 92 "m_external", 93 "reserved", 94 "reserved", 95 "reserved", 96 "reserved" 97 }; 98 99 static void set_misa(CPURISCVState *env, target_ulong misa) 100 { 101 env->misa_mask = env->misa = misa; 102 } 103 104 static void set_priv_version(CPURISCVState *env, int priv_ver) 105 { 106 env->priv_ver = priv_ver; 107 } 108 109 static void set_feature(CPURISCVState *env, int feature) 110 { 111 env->features |= (1ULL << feature); 112 } 113 114 static void set_resetvec(CPURISCVState *env, int resetvec) 115 { 116 #ifndef CONFIG_USER_ONLY 117 env->resetvec = resetvec; 118 #endif 119 } 120 121 static void riscv_any_cpu_init(Object *obj) 122 { 123 CPURISCVState *env = &RISCV_CPU(obj)->env; 124 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); 125 set_priv_version(env, PRIV_VERSION_1_11_0); 126 set_resetvec(env, DEFAULT_RSTVEC); 127 } 128 129 static void riscv_base_cpu_init(Object *obj) 130 { 131 CPURISCVState *env = &RISCV_CPU(obj)->env; 132 /* We set this in the realise function */ 133 set_misa(env, 0); 134 set_resetvec(env, DEFAULT_RSTVEC); 135 } 136 137 static void rvxx_sifive_u_cpu_init(Object *obj) 138 { 139 CPURISCVState *env = &RISCV_CPU(obj)->env; 140 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 141 set_priv_version(env, PRIV_VERSION_1_10_0); 142 set_resetvec(env, 0x1004); 143 } 144 145 static void rvxx_sifive_e_cpu_init(Object *obj) 146 { 147 CPURISCVState *env = &RISCV_CPU(obj)->env; 148 set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU); 149 set_priv_version(env, PRIV_VERSION_1_10_0); 150 set_resetvec(env, 0x1004); 151 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 152 } 153 154 #if defined(TARGET_RISCV32) 155 156 static void rv32_ibex_cpu_init(Object *obj) 157 { 158 CPURISCVState *env = &RISCV_CPU(obj)->env; 159 set_misa(env, RV32 | RVI | RVM | RVC | RVU); 160 set_priv_version(env, PRIV_VERSION_1_10_0); 161 set_resetvec(env, 0x8090); 162 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 163 } 164 165 static void rv32_imafcu_nommu_cpu_init(Object *obj) 166 { 167 CPURISCVState *env = &RISCV_CPU(obj)->env; 168 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); 169 set_priv_version(env, PRIV_VERSION_1_10_0); 170 set_resetvec(env, DEFAULT_RSTVEC); 171 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 172 } 173 174 #endif 175 176 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 177 { 178 ObjectClass *oc; 179 char *typename; 180 char **cpuname; 181 182 cpuname = g_strsplit(cpu_model, ",", 1); 183 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 184 oc = object_class_by_name(typename); 185 g_strfreev(cpuname); 186 g_free(typename); 187 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 188 object_class_is_abstract(oc)) { 189 return NULL; 190 } 191 return oc; 192 } 193 194 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 195 { 196 RISCVCPU *cpu = RISCV_CPU(cs); 197 CPURISCVState *env = &cpu->env; 198 int i; 199 200 #if !defined(CONFIG_USER_ONLY) 201 if (riscv_has_ext(env, RVH)) { 202 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 203 } 204 #endif 205 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 206 #ifndef CONFIG_USER_ONLY 207 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); 208 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); 209 #ifdef TARGET_RISCV32 210 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush); 211 #endif 212 if (riscv_has_ext(env, RVH)) { 213 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); 214 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus); 215 } 216 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); 217 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); 218 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); 219 if (riscv_has_ext(env, RVH)) { 220 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); 221 } 222 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); 223 if (riscv_has_ext(env, RVH)) { 224 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); 225 } 226 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); 227 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); 228 if (riscv_has_ext(env, RVH)) { 229 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); 230 } 231 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); 232 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); 233 if (riscv_has_ext(env, RVH)) { 234 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); 235 } 236 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); 237 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); 238 if (riscv_has_ext(env, RVH)) { 239 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); 240 } 241 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); 242 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr); 243 if (riscv_has_ext(env, RVH)) { 244 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); 245 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); 246 } 247 #endif 248 249 for (i = 0; i < 32; i++) { 250 qemu_fprintf(f, " %s " TARGET_FMT_lx, 251 riscv_int_regnames[i], env->gpr[i]); 252 if ((i & 3) == 3) { 253 qemu_fprintf(f, "\n"); 254 } 255 } 256 if (flags & CPU_DUMP_FPU) { 257 for (i = 0; i < 32; i++) { 258 qemu_fprintf(f, " %s %016" PRIx64, 259 riscv_fpr_regnames[i], env->fpr[i]); 260 if ((i & 3) == 3) { 261 qemu_fprintf(f, "\n"); 262 } 263 } 264 } 265 } 266 267 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 268 { 269 RISCVCPU *cpu = RISCV_CPU(cs); 270 CPURISCVState *env = &cpu->env; 271 env->pc = value; 272 } 273 274 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 275 { 276 RISCVCPU *cpu = RISCV_CPU(cs); 277 CPURISCVState *env = &cpu->env; 278 env->pc = tb->pc; 279 } 280 281 static bool riscv_cpu_has_work(CPUState *cs) 282 { 283 #ifndef CONFIG_USER_ONLY 284 RISCVCPU *cpu = RISCV_CPU(cs); 285 CPURISCVState *env = &cpu->env; 286 /* 287 * Definition of the WFI instruction requires it to ignore the privilege 288 * mode and delegation registers, but respect individual enables 289 */ 290 return (env->mip & env->mie) != 0; 291 #else 292 return true; 293 #endif 294 } 295 296 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 297 target_ulong *data) 298 { 299 env->pc = data[0]; 300 } 301 302 static void riscv_cpu_reset(DeviceState *dev) 303 { 304 CPUState *cs = CPU(dev); 305 RISCVCPU *cpu = RISCV_CPU(cs); 306 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 307 CPURISCVState *env = &cpu->env; 308 309 mcc->parent_reset(dev); 310 #ifndef CONFIG_USER_ONLY 311 env->priv = PRV_M; 312 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 313 env->mcause = 0; 314 env->pc = env->resetvec; 315 #endif 316 cs->exception_index = EXCP_NONE; 317 env->load_res = -1; 318 set_default_nan_mode(1, &env->fp_status); 319 } 320 321 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 322 { 323 #if defined(TARGET_RISCV32) 324 info->print_insn = print_insn_riscv32; 325 #elif defined(TARGET_RISCV64) 326 info->print_insn = print_insn_riscv64; 327 #endif 328 } 329 330 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 331 { 332 CPUState *cs = CPU(dev); 333 RISCVCPU *cpu = RISCV_CPU(dev); 334 CPURISCVState *env = &cpu->env; 335 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 336 int priv_version = PRIV_VERSION_1_11_0; 337 target_ulong target_misa = 0; 338 Error *local_err = NULL; 339 340 cpu_exec_realizefn(cs, &local_err); 341 if (local_err != NULL) { 342 error_propagate(errp, local_err); 343 return; 344 } 345 346 if (cpu->cfg.priv_spec) { 347 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 348 priv_version = PRIV_VERSION_1_11_0; 349 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 350 priv_version = PRIV_VERSION_1_10_0; 351 } else { 352 error_setg(errp, 353 "Unsupported privilege spec version '%s'", 354 cpu->cfg.priv_spec); 355 return; 356 } 357 } 358 359 set_priv_version(env, priv_version); 360 361 if (cpu->cfg.mmu) { 362 set_feature(env, RISCV_FEATURE_MMU); 363 } 364 365 if (cpu->cfg.pmp) { 366 set_feature(env, RISCV_FEATURE_PMP); 367 } 368 369 /* If misa isn't set (rv32 and rv64 machines) set it here */ 370 if (!env->misa) { 371 /* Do some ISA extension error checking */ 372 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 373 error_setg(errp, 374 "I and E extensions are incompatible"); 375 return; 376 } 377 378 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 379 error_setg(errp, 380 "Either I or E extension must be set"); 381 return; 382 } 383 384 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 385 cpu->cfg.ext_a & cpu->cfg.ext_f & 386 cpu->cfg.ext_d)) { 387 warn_report("Setting G will also set IMAFD"); 388 cpu->cfg.ext_i = true; 389 cpu->cfg.ext_m = true; 390 cpu->cfg.ext_a = true; 391 cpu->cfg.ext_f = true; 392 cpu->cfg.ext_d = true; 393 } 394 395 /* Set the ISA extensions, checks should have happened above */ 396 if (cpu->cfg.ext_i) { 397 target_misa |= RVI; 398 } 399 if (cpu->cfg.ext_e) { 400 target_misa |= RVE; 401 } 402 if (cpu->cfg.ext_m) { 403 target_misa |= RVM; 404 } 405 if (cpu->cfg.ext_a) { 406 target_misa |= RVA; 407 } 408 if (cpu->cfg.ext_f) { 409 target_misa |= RVF; 410 } 411 if (cpu->cfg.ext_d) { 412 target_misa |= RVD; 413 } 414 if (cpu->cfg.ext_c) { 415 target_misa |= RVC; 416 } 417 if (cpu->cfg.ext_s) { 418 target_misa |= RVS; 419 } 420 if (cpu->cfg.ext_u) { 421 target_misa |= RVU; 422 } 423 if (cpu->cfg.ext_h) { 424 target_misa |= RVH; 425 } 426 427 set_misa(env, RVXLEN | target_misa); 428 } 429 430 riscv_cpu_register_gdb_regs_for_features(cs); 431 432 qemu_init_vcpu(cs); 433 cpu_reset(cs); 434 435 mcc->parent_realize(dev, errp); 436 } 437 438 static void riscv_cpu_init(Object *obj) 439 { 440 RISCVCPU *cpu = RISCV_CPU(obj); 441 442 cpu_set_cpustate_pointers(cpu); 443 } 444 445 #ifndef CONFIG_USER_ONLY 446 static const VMStateDescription vmstate_riscv_cpu = { 447 .name = "cpu", 448 .unmigratable = 1, 449 }; 450 #endif 451 452 static Property riscv_cpu_properties[] = { 453 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 454 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 455 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 456 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 457 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 458 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 459 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 460 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 461 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 462 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 463 /* This is experimental so mark with 'x-' */ 464 DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), 465 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 466 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 467 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 468 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 469 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 470 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 471 DEFINE_PROP_END_OF_LIST(), 472 }; 473 474 static void riscv_cpu_class_init(ObjectClass *c, void *data) 475 { 476 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 477 CPUClass *cc = CPU_CLASS(c); 478 DeviceClass *dc = DEVICE_CLASS(c); 479 480 device_class_set_parent_realize(dc, riscv_cpu_realize, 481 &mcc->parent_realize); 482 483 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 484 485 cc->class_by_name = riscv_cpu_class_by_name; 486 cc->has_work = riscv_cpu_has_work; 487 cc->do_interrupt = riscv_cpu_do_interrupt; 488 cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt; 489 cc->dump_state = riscv_cpu_dump_state; 490 cc->set_pc = riscv_cpu_set_pc; 491 cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb; 492 cc->gdb_read_register = riscv_cpu_gdb_read_register; 493 cc->gdb_write_register = riscv_cpu_gdb_write_register; 494 cc->gdb_num_core_regs = 33; 495 #if defined(TARGET_RISCV32) 496 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 497 #elif defined(TARGET_RISCV64) 498 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 499 #endif 500 cc->gdb_stop_before_watchpoint = true; 501 cc->disas_set_info = riscv_cpu_disas_set_info; 502 #ifndef CONFIG_USER_ONLY 503 cc->do_transaction_failed = riscv_cpu_do_transaction_failed; 504 cc->do_unaligned_access = riscv_cpu_do_unaligned_access; 505 cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; 506 /* For now, mark unmigratable: */ 507 cc->vmsd = &vmstate_riscv_cpu; 508 #endif 509 #ifdef CONFIG_TCG 510 cc->tcg_initialize = riscv_translate_init; 511 cc->tlb_fill = riscv_cpu_tlb_fill; 512 #endif 513 device_class_set_props(dc, riscv_cpu_properties); 514 } 515 516 char *riscv_isa_string(RISCVCPU *cpu) 517 { 518 int i; 519 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 520 char *isa_str = g_new(char, maxlen); 521 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 522 for (i = 0; i < sizeof(riscv_exts); i++) { 523 if (cpu->env.misa & RV(riscv_exts[i])) { 524 *p++ = qemu_tolower(riscv_exts[i]); 525 } 526 } 527 *p = '\0'; 528 return isa_str; 529 } 530 531 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 532 { 533 ObjectClass *class_a = (ObjectClass *)a; 534 ObjectClass *class_b = (ObjectClass *)b; 535 const char *name_a, *name_b; 536 537 name_a = object_class_get_name(class_a); 538 name_b = object_class_get_name(class_b); 539 return strcmp(name_a, name_b); 540 } 541 542 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 543 { 544 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 545 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 546 547 qemu_printf("%.*s\n", len, typename); 548 } 549 550 void riscv_cpu_list(void) 551 { 552 GSList *list; 553 554 list = object_class_get_list(TYPE_RISCV_CPU, false); 555 list = g_slist_sort(list, riscv_cpu_list_compare); 556 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 557 g_slist_free(list); 558 } 559 560 #define DEFINE_CPU(type_name, initfn) \ 561 { \ 562 .name = type_name, \ 563 .parent = TYPE_RISCV_CPU, \ 564 .instance_init = initfn \ 565 } 566 567 static const TypeInfo riscv_cpu_type_infos[] = { 568 { 569 .name = TYPE_RISCV_CPU, 570 .parent = TYPE_CPU, 571 .instance_size = sizeof(RISCVCPU), 572 .instance_init = riscv_cpu_init, 573 .abstract = true, 574 .class_size = sizeof(RISCVCPUClass), 575 .class_init = riscv_cpu_class_init, 576 }, 577 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 578 #if defined(TARGET_RISCV32) 579 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init), 580 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 581 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init), 582 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 583 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init), 584 #elif defined(TARGET_RISCV64) 585 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), 586 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init), 587 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init), 588 #endif 589 }; 590 591 DEFINE_TYPES(riscv_cpu_type_infos) 592