1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "exec/exec-all.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "fpu/softfloat-helpers.h" 32 #include "sysemu/kvm.h" 33 #include "kvm_riscv.h" 34 35 /* RISC-V CPU definitions */ 36 37 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 38 39 const char * const riscv_int_regnames[] = { 40 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 41 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 42 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 43 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 44 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 45 }; 46 47 const char * const riscv_int_regnamesh[] = { 48 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 49 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 50 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 51 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 52 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 53 "x30h/t5h", "x31h/t6h" 54 }; 55 56 const char * const riscv_fpr_regnames[] = { 57 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 58 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 59 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 60 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 61 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 62 "f30/ft10", "f31/ft11" 63 }; 64 65 static const char * const riscv_excp_names[] = { 66 "misaligned_fetch", 67 "fault_fetch", 68 "illegal_instruction", 69 "breakpoint", 70 "misaligned_load", 71 "fault_load", 72 "misaligned_store", 73 "fault_store", 74 "user_ecall", 75 "supervisor_ecall", 76 "hypervisor_ecall", 77 "machine_ecall", 78 "exec_page_fault", 79 "load_page_fault", 80 "reserved", 81 "store_page_fault", 82 "reserved", 83 "reserved", 84 "reserved", 85 "reserved", 86 "guest_exec_page_fault", 87 "guest_load_page_fault", 88 "reserved", 89 "guest_store_page_fault", 90 }; 91 92 static const char * const riscv_intr_names[] = { 93 "u_software", 94 "s_software", 95 "vs_software", 96 "m_software", 97 "u_timer", 98 "s_timer", 99 "vs_timer", 100 "m_timer", 101 "u_external", 102 "s_external", 103 "vs_external", 104 "m_external", 105 "reserved", 106 "reserved", 107 "reserved", 108 "reserved" 109 }; 110 111 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 112 { 113 if (async) { 114 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 115 riscv_intr_names[cause] : "(unknown)"; 116 } else { 117 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 118 riscv_excp_names[cause] : "(unknown)"; 119 } 120 } 121 122 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 123 { 124 env->misa_mxl_max = env->misa_mxl = mxl; 125 env->misa_ext_mask = env->misa_ext = ext; 126 } 127 128 static void set_priv_version(CPURISCVState *env, int priv_ver) 129 { 130 env->priv_ver = priv_ver; 131 } 132 133 static void set_vext_version(CPURISCVState *env, int vext_ver) 134 { 135 env->vext_ver = vext_ver; 136 } 137 138 static void set_resetvec(CPURISCVState *env, target_ulong resetvec) 139 { 140 #ifndef CONFIG_USER_ONLY 141 env->resetvec = resetvec; 142 #endif 143 } 144 145 static void riscv_any_cpu_init(Object *obj) 146 { 147 CPURISCVState *env = &RISCV_CPU(obj)->env; 148 #if defined(TARGET_RISCV32) 149 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 150 #elif defined(TARGET_RISCV64) 151 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 152 #endif 153 set_priv_version(env, PRIV_VERSION_1_11_0); 154 } 155 156 #if defined(TARGET_RISCV64) 157 static void rv64_base_cpu_init(Object *obj) 158 { 159 CPURISCVState *env = &RISCV_CPU(obj)->env; 160 /* We set this in the realise function */ 161 set_misa(env, MXL_RV64, 0); 162 } 163 164 static void rv64_sifive_u_cpu_init(Object *obj) 165 { 166 CPURISCVState *env = &RISCV_CPU(obj)->env; 167 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 168 set_priv_version(env, PRIV_VERSION_1_10_0); 169 } 170 171 static void rv64_sifive_e_cpu_init(Object *obj) 172 { 173 CPURISCVState *env = &RISCV_CPU(obj)->env; 174 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 175 set_priv_version(env, PRIV_VERSION_1_10_0); 176 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 177 } 178 179 static void rv128_base_cpu_init(Object *obj) 180 { 181 if (qemu_tcg_mttcg_enabled()) { 182 /* Missing 128-bit aligned atomics */ 183 error_report("128-bit RISC-V currently does not work with Multi " 184 "Threaded TCG. Please use: -accel tcg,thread=single"); 185 exit(EXIT_FAILURE); 186 } 187 CPURISCVState *env = &RISCV_CPU(obj)->env; 188 /* We set this in the realise function */ 189 set_misa(env, MXL_RV128, 0); 190 } 191 #else 192 static void rv32_base_cpu_init(Object *obj) 193 { 194 CPURISCVState *env = &RISCV_CPU(obj)->env; 195 /* We set this in the realise function */ 196 set_misa(env, MXL_RV32, 0); 197 } 198 199 static void rv32_sifive_u_cpu_init(Object *obj) 200 { 201 CPURISCVState *env = &RISCV_CPU(obj)->env; 202 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 203 set_priv_version(env, PRIV_VERSION_1_10_0); 204 } 205 206 static void rv32_sifive_e_cpu_init(Object *obj) 207 { 208 CPURISCVState *env = &RISCV_CPU(obj)->env; 209 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 210 set_priv_version(env, PRIV_VERSION_1_10_0); 211 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 212 } 213 214 static void rv32_ibex_cpu_init(Object *obj) 215 { 216 CPURISCVState *env = &RISCV_CPU(obj)->env; 217 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 218 set_priv_version(env, PRIV_VERSION_1_10_0); 219 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 220 qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); 221 } 222 223 static void rv32_imafcu_nommu_cpu_init(Object *obj) 224 { 225 CPURISCVState *env = &RISCV_CPU(obj)->env; 226 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 227 set_priv_version(env, PRIV_VERSION_1_10_0); 228 set_resetvec(env, DEFAULT_RSTVEC); 229 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 230 } 231 #endif 232 233 #if defined(CONFIG_KVM) 234 static void riscv_host_cpu_init(Object *obj) 235 { 236 CPURISCVState *env = &RISCV_CPU(obj)->env; 237 #if defined(TARGET_RISCV32) 238 set_misa(env, MXL_RV32, 0); 239 #elif defined(TARGET_RISCV64) 240 set_misa(env, MXL_RV64, 0); 241 #endif 242 } 243 #endif 244 245 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 246 { 247 ObjectClass *oc; 248 char *typename; 249 char **cpuname; 250 251 cpuname = g_strsplit(cpu_model, ",", 1); 252 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 253 oc = object_class_by_name(typename); 254 g_strfreev(cpuname); 255 g_free(typename); 256 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 257 object_class_is_abstract(oc)) { 258 return NULL; 259 } 260 return oc; 261 } 262 263 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 264 { 265 RISCVCPU *cpu = RISCV_CPU(cs); 266 CPURISCVState *env = &cpu->env; 267 int i; 268 269 #if !defined(CONFIG_USER_ONLY) 270 if (riscv_has_ext(env, RVH)) { 271 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 272 } 273 #endif 274 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 275 #ifndef CONFIG_USER_ONLY 276 { 277 static const int dump_csrs[] = { 278 CSR_MHARTID, 279 CSR_MSTATUS, 280 CSR_MSTATUSH, 281 CSR_HSTATUS, 282 CSR_VSSTATUS, 283 CSR_MIP, 284 CSR_MIE, 285 CSR_MIDELEG, 286 CSR_HIDELEG, 287 CSR_MEDELEG, 288 CSR_HEDELEG, 289 CSR_MTVEC, 290 CSR_STVEC, 291 CSR_VSTVEC, 292 CSR_MEPC, 293 CSR_SEPC, 294 CSR_VSEPC, 295 CSR_MCAUSE, 296 CSR_SCAUSE, 297 CSR_VSCAUSE, 298 CSR_MTVAL, 299 CSR_STVAL, 300 CSR_HTVAL, 301 CSR_MTVAL2, 302 CSR_MSCRATCH, 303 CSR_SSCRATCH, 304 CSR_SATP, 305 CSR_MMTE, 306 CSR_UPMBASE, 307 CSR_UPMMASK, 308 CSR_SPMBASE, 309 CSR_SPMMASK, 310 CSR_MPMBASE, 311 CSR_MPMMASK, 312 }; 313 314 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 315 int csrno = dump_csrs[i]; 316 target_ulong val = 0; 317 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 318 319 /* 320 * Rely on the smode, hmode, etc, predicates within csr.c 321 * to do the filtering of the registers that are present. 322 */ 323 if (res == RISCV_EXCP_NONE) { 324 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 325 csr_ops[csrno].name, val); 326 } 327 } 328 } 329 #endif 330 331 for (i = 0; i < 32; i++) { 332 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 333 riscv_int_regnames[i], env->gpr[i]); 334 if ((i & 3) == 3) { 335 qemu_fprintf(f, "\n"); 336 } 337 } 338 if (flags & CPU_DUMP_FPU) { 339 for (i = 0; i < 32; i++) { 340 qemu_fprintf(f, " %-8s %016" PRIx64, 341 riscv_fpr_regnames[i], env->fpr[i]); 342 if ((i & 3) == 3) { 343 qemu_fprintf(f, "\n"); 344 } 345 } 346 } 347 } 348 349 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 350 { 351 RISCVCPU *cpu = RISCV_CPU(cs); 352 CPURISCVState *env = &cpu->env; 353 354 if (env->xl == MXL_RV32) { 355 env->pc = (int32_t)value; 356 } else { 357 env->pc = value; 358 } 359 } 360 361 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 362 const TranslationBlock *tb) 363 { 364 RISCVCPU *cpu = RISCV_CPU(cs); 365 CPURISCVState *env = &cpu->env; 366 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 367 368 if (xl == MXL_RV32) { 369 env->pc = (int32_t)tb->pc; 370 } else { 371 env->pc = tb->pc; 372 } 373 } 374 375 static bool riscv_cpu_has_work(CPUState *cs) 376 { 377 #ifndef CONFIG_USER_ONLY 378 RISCVCPU *cpu = RISCV_CPU(cs); 379 CPURISCVState *env = &cpu->env; 380 /* 381 * Definition of the WFI instruction requires it to ignore the privilege 382 * mode and delegation registers, but respect individual enables 383 */ 384 return (env->mip & env->mie) != 0; 385 #else 386 return true; 387 #endif 388 } 389 390 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 391 target_ulong *data) 392 { 393 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 394 if (xl == MXL_RV32) { 395 env->pc = (int32_t)data[0]; 396 } else { 397 env->pc = data[0]; 398 } 399 } 400 401 static void riscv_cpu_reset(DeviceState *dev) 402 { 403 CPUState *cs = CPU(dev); 404 RISCVCPU *cpu = RISCV_CPU(cs); 405 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 406 CPURISCVState *env = &cpu->env; 407 408 mcc->parent_reset(dev); 409 #ifndef CONFIG_USER_ONLY 410 env->misa_mxl = env->misa_mxl_max; 411 env->priv = PRV_M; 412 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 413 if (env->misa_mxl > MXL_RV32) { 414 /* 415 * The reset status of SXL/UXL is undefined, but mstatus is WARL 416 * and we must ensure that the value after init is valid for read. 417 */ 418 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 419 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 420 if (riscv_has_ext(env, RVH)) { 421 env->vsstatus = set_field(env->vsstatus, 422 MSTATUS64_SXL, env->misa_mxl); 423 env->vsstatus = set_field(env->vsstatus, 424 MSTATUS64_UXL, env->misa_mxl); 425 env->mstatus_hs = set_field(env->mstatus_hs, 426 MSTATUS64_SXL, env->misa_mxl); 427 env->mstatus_hs = set_field(env->mstatus_hs, 428 MSTATUS64_UXL, env->misa_mxl); 429 } 430 } 431 env->mcause = 0; 432 env->miclaim = MIP_SGEIP; 433 env->pc = env->resetvec; 434 env->two_stage_lookup = false; 435 /* mmte is supposed to have pm.current hardwired to 1 */ 436 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 437 #endif 438 env->xl = riscv_cpu_mxl(env); 439 riscv_cpu_update_mask(env); 440 cs->exception_index = RISCV_EXCP_NONE; 441 env->load_res = -1; 442 set_default_nan_mode(1, &env->fp_status); 443 444 #ifndef CONFIG_USER_ONLY 445 if (kvm_enabled()) { 446 kvm_riscv_reset_vcpu(cpu); 447 } 448 #endif 449 } 450 451 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 452 { 453 RISCVCPU *cpu = RISCV_CPU(s); 454 455 switch (riscv_cpu_mxl(&cpu->env)) { 456 case MXL_RV32: 457 info->print_insn = print_insn_riscv32; 458 break; 459 case MXL_RV64: 460 info->print_insn = print_insn_riscv64; 461 break; 462 case MXL_RV128: 463 info->print_insn = print_insn_riscv128; 464 break; 465 default: 466 g_assert_not_reached(); 467 } 468 } 469 470 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 471 { 472 CPUState *cs = CPU(dev); 473 RISCVCPU *cpu = RISCV_CPU(dev); 474 CPURISCVState *env = &cpu->env; 475 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 476 CPUClass *cc = CPU_CLASS(mcc); 477 int priv_version = 0; 478 Error *local_err = NULL; 479 480 cpu_exec_realizefn(cs, &local_err); 481 if (local_err != NULL) { 482 error_propagate(errp, local_err); 483 return; 484 } 485 486 if (cpu->cfg.priv_spec) { 487 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 488 priv_version = PRIV_VERSION_1_11_0; 489 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 490 priv_version = PRIV_VERSION_1_10_0; 491 } else { 492 error_setg(errp, 493 "Unsupported privilege spec version '%s'", 494 cpu->cfg.priv_spec); 495 return; 496 } 497 } 498 499 if (priv_version) { 500 set_priv_version(env, priv_version); 501 } else if (!env->priv_ver) { 502 set_priv_version(env, PRIV_VERSION_1_11_0); 503 } 504 505 if (cpu->cfg.mmu) { 506 riscv_set_feature(env, RISCV_FEATURE_MMU); 507 } 508 509 if (cpu->cfg.pmp) { 510 riscv_set_feature(env, RISCV_FEATURE_PMP); 511 512 /* 513 * Enhanced PMP should only be available 514 * on harts with PMP support 515 */ 516 if (cpu->cfg.epmp) { 517 riscv_set_feature(env, RISCV_FEATURE_EPMP); 518 } 519 } 520 521 set_resetvec(env, cpu->cfg.resetvec); 522 523 /* Validate that MISA_MXL is set properly. */ 524 switch (env->misa_mxl_max) { 525 #ifdef TARGET_RISCV64 526 case MXL_RV64: 527 case MXL_RV128: 528 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 529 break; 530 #endif 531 case MXL_RV32: 532 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 533 break; 534 default: 535 g_assert_not_reached(); 536 } 537 assert(env->misa_mxl_max == env->misa_mxl); 538 539 /* If only MISA_EXT is unset for misa, then set it from properties */ 540 if (env->misa_ext == 0) { 541 uint32_t ext = 0; 542 543 /* Do some ISA extension error checking */ 544 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 545 error_setg(errp, 546 "I and E extensions are incompatible"); 547 return; 548 } 549 550 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 551 error_setg(errp, 552 "Either I or E extension must be set"); 553 return; 554 } 555 556 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 557 cpu->cfg.ext_a & cpu->cfg.ext_f & 558 cpu->cfg.ext_d)) { 559 warn_report("Setting G will also set IMAFD"); 560 cpu->cfg.ext_i = true; 561 cpu->cfg.ext_m = true; 562 cpu->cfg.ext_a = true; 563 cpu->cfg.ext_f = true; 564 cpu->cfg.ext_d = true; 565 } 566 567 /* Set the ISA extensions, checks should have happened above */ 568 if (cpu->cfg.ext_i) { 569 ext |= RVI; 570 } 571 if (cpu->cfg.ext_e) { 572 ext |= RVE; 573 } 574 if (cpu->cfg.ext_m) { 575 ext |= RVM; 576 } 577 if (cpu->cfg.ext_a) { 578 ext |= RVA; 579 } 580 if (cpu->cfg.ext_f) { 581 ext |= RVF; 582 } 583 if (cpu->cfg.ext_d) { 584 ext |= RVD; 585 } 586 if (cpu->cfg.ext_c) { 587 ext |= RVC; 588 } 589 if (cpu->cfg.ext_s) { 590 ext |= RVS; 591 } 592 if (cpu->cfg.ext_u) { 593 ext |= RVU; 594 } 595 if (cpu->cfg.ext_h) { 596 ext |= RVH; 597 } 598 if (cpu->cfg.ext_v) { 599 int vext_version = VEXT_VERSION_1_00_0; 600 ext |= RVV; 601 if (!is_power_of_2(cpu->cfg.vlen)) { 602 error_setg(errp, 603 "Vector extension VLEN must be power of 2"); 604 return; 605 } 606 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 607 error_setg(errp, 608 "Vector extension implementation only supports VLEN " 609 "in the range [128, %d]", RV_VLEN_MAX); 610 return; 611 } 612 if (!is_power_of_2(cpu->cfg.elen)) { 613 error_setg(errp, 614 "Vector extension ELEN must be power of 2"); 615 return; 616 } 617 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 618 error_setg(errp, 619 "Vector extension implementation only supports ELEN " 620 "in the range [8, 64]"); 621 return; 622 } 623 if (cpu->cfg.vext_spec) { 624 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 625 vext_version = VEXT_VERSION_1_00_0; 626 } else { 627 error_setg(errp, 628 "Unsupported vector spec version '%s'", 629 cpu->cfg.vext_spec); 630 return; 631 } 632 } else { 633 qemu_log("vector version is not specified, " 634 "use the default value v1.0\n"); 635 } 636 set_vext_version(env, vext_version); 637 } 638 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 639 error_setg(errp, "Zve32f/Zve64f extension depends upon RVF."); 640 return; 641 } 642 if (cpu->cfg.ext_j) { 643 ext |= RVJ; 644 } 645 646 set_misa(env, env->misa_mxl, ext); 647 } 648 649 riscv_cpu_register_gdb_regs_for_features(cs); 650 651 qemu_init_vcpu(cs); 652 cpu_reset(cs); 653 654 mcc->parent_realize(dev, errp); 655 } 656 657 #ifndef CONFIG_USER_ONLY 658 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 659 { 660 RISCVCPU *cpu = RISCV_CPU(opaque); 661 CPURISCVState *env = &cpu->env; 662 663 if (irq < IRQ_LOCAL_MAX) { 664 switch (irq) { 665 case IRQ_U_SOFT: 666 case IRQ_S_SOFT: 667 case IRQ_VS_SOFT: 668 case IRQ_M_SOFT: 669 case IRQ_U_TIMER: 670 case IRQ_S_TIMER: 671 case IRQ_VS_TIMER: 672 case IRQ_M_TIMER: 673 case IRQ_U_EXT: 674 case IRQ_S_EXT: 675 case IRQ_VS_EXT: 676 case IRQ_M_EXT: 677 if (kvm_enabled()) { 678 kvm_riscv_set_irq(cpu, irq, level); 679 } else { 680 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 681 } 682 break; 683 default: 684 g_assert_not_reached(); 685 } 686 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 687 /* Require H-extension for handling guest local interrupts */ 688 if (!riscv_has_ext(env, RVH)) { 689 g_assert_not_reached(); 690 } 691 692 /* Compute bit position in HGEIP CSR */ 693 irq = irq - IRQ_LOCAL_MAX + 1; 694 if (env->geilen < irq) { 695 g_assert_not_reached(); 696 } 697 698 /* Update HGEIP CSR */ 699 env->hgeip &= ~((target_ulong)1 << irq); 700 if (level) { 701 env->hgeip |= (target_ulong)1 << irq; 702 } 703 704 /* Update mip.SGEIP bit */ 705 riscv_cpu_update_mip(cpu, MIP_SGEIP, 706 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 707 } else { 708 g_assert_not_reached(); 709 } 710 } 711 #endif /* CONFIG_USER_ONLY */ 712 713 static void riscv_cpu_init(Object *obj) 714 { 715 RISCVCPU *cpu = RISCV_CPU(obj); 716 717 cpu_set_cpustate_pointers(cpu); 718 719 #ifndef CONFIG_USER_ONLY 720 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 721 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 722 #endif /* CONFIG_USER_ONLY */ 723 } 724 725 static Property riscv_cpu_properties[] = { 726 /* Defaults for standard extensions */ 727 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 728 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 729 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 730 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 731 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 732 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 733 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 734 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 735 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 736 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 737 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 738 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 739 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 740 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 741 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 742 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 743 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 744 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 745 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 746 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 747 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 748 749 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 750 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 751 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 752 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 753 754 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 755 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 756 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 757 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 758 759 /* Vendor-specific custom extensions */ 760 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 761 762 /* These are experimental so mark with 'x-' */ 763 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 764 /* ePMP 0.9.3 */ 765 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 766 767 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 768 DEFINE_PROP_END_OF_LIST(), 769 }; 770 771 static gchar *riscv_gdb_arch_name(CPUState *cs) 772 { 773 RISCVCPU *cpu = RISCV_CPU(cs); 774 CPURISCVState *env = &cpu->env; 775 776 switch (riscv_cpu_mxl(env)) { 777 case MXL_RV32: 778 return g_strdup("riscv:rv32"); 779 case MXL_RV64: 780 case MXL_RV128: 781 return g_strdup("riscv:rv64"); 782 default: 783 g_assert_not_reached(); 784 } 785 } 786 787 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 788 { 789 RISCVCPU *cpu = RISCV_CPU(cs); 790 791 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 792 return cpu->dyn_csr_xml; 793 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 794 return cpu->dyn_vreg_xml; 795 } 796 797 return NULL; 798 } 799 800 #ifndef CONFIG_USER_ONLY 801 #include "hw/core/sysemu-cpu-ops.h" 802 803 static const struct SysemuCPUOps riscv_sysemu_ops = { 804 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 805 .write_elf64_note = riscv_cpu_write_elf64_note, 806 .write_elf32_note = riscv_cpu_write_elf32_note, 807 .legacy_vmsd = &vmstate_riscv_cpu, 808 }; 809 #endif 810 811 #include "hw/core/tcg-cpu-ops.h" 812 813 static const struct TCGCPUOps riscv_tcg_ops = { 814 .initialize = riscv_translate_init, 815 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 816 817 #ifndef CONFIG_USER_ONLY 818 .tlb_fill = riscv_cpu_tlb_fill, 819 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 820 .do_interrupt = riscv_cpu_do_interrupt, 821 .do_transaction_failed = riscv_cpu_do_transaction_failed, 822 .do_unaligned_access = riscv_cpu_do_unaligned_access, 823 #endif /* !CONFIG_USER_ONLY */ 824 }; 825 826 static void riscv_cpu_class_init(ObjectClass *c, void *data) 827 { 828 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 829 CPUClass *cc = CPU_CLASS(c); 830 DeviceClass *dc = DEVICE_CLASS(c); 831 832 device_class_set_parent_realize(dc, riscv_cpu_realize, 833 &mcc->parent_realize); 834 835 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 836 837 cc->class_by_name = riscv_cpu_class_by_name; 838 cc->has_work = riscv_cpu_has_work; 839 cc->dump_state = riscv_cpu_dump_state; 840 cc->set_pc = riscv_cpu_set_pc; 841 cc->gdb_read_register = riscv_cpu_gdb_read_register; 842 cc->gdb_write_register = riscv_cpu_gdb_write_register; 843 cc->gdb_num_core_regs = 33; 844 cc->gdb_stop_before_watchpoint = true; 845 cc->disas_set_info = riscv_cpu_disas_set_info; 846 #ifndef CONFIG_USER_ONLY 847 cc->sysemu_ops = &riscv_sysemu_ops; 848 #endif 849 cc->gdb_arch_name = riscv_gdb_arch_name; 850 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 851 cc->tcg_ops = &riscv_tcg_ops; 852 853 device_class_set_props(dc, riscv_cpu_properties); 854 } 855 856 char *riscv_isa_string(RISCVCPU *cpu) 857 { 858 int i; 859 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 860 char *isa_str = g_new(char, maxlen); 861 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 862 for (i = 0; i < sizeof(riscv_exts); i++) { 863 if (cpu->env.misa_ext & RV(riscv_exts[i])) { 864 *p++ = qemu_tolower(riscv_exts[i]); 865 } 866 } 867 *p = '\0'; 868 return isa_str; 869 } 870 871 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 872 { 873 ObjectClass *class_a = (ObjectClass *)a; 874 ObjectClass *class_b = (ObjectClass *)b; 875 const char *name_a, *name_b; 876 877 name_a = object_class_get_name(class_a); 878 name_b = object_class_get_name(class_b); 879 return strcmp(name_a, name_b); 880 } 881 882 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 883 { 884 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 885 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 886 887 qemu_printf("%.*s\n", len, typename); 888 } 889 890 void riscv_cpu_list(void) 891 { 892 GSList *list; 893 894 list = object_class_get_list(TYPE_RISCV_CPU, false); 895 list = g_slist_sort(list, riscv_cpu_list_compare); 896 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 897 g_slist_free(list); 898 } 899 900 #define DEFINE_CPU(type_name, initfn) \ 901 { \ 902 .name = type_name, \ 903 .parent = TYPE_RISCV_CPU, \ 904 .instance_init = initfn \ 905 } 906 907 static const TypeInfo riscv_cpu_type_infos[] = { 908 { 909 .name = TYPE_RISCV_CPU, 910 .parent = TYPE_CPU, 911 .instance_size = sizeof(RISCVCPU), 912 .instance_align = __alignof__(RISCVCPU), 913 .instance_init = riscv_cpu_init, 914 .abstract = true, 915 .class_size = sizeof(RISCVCPUClass), 916 .class_init = riscv_cpu_class_init, 917 }, 918 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 919 #if defined(CONFIG_KVM) 920 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 921 #endif 922 #if defined(TARGET_RISCV32) 923 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 924 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 925 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 926 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 927 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 928 #elif defined(TARGET_RISCV64) 929 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 930 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 931 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 932 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 933 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 934 #endif 935 }; 936 937 DEFINE_TYPES(riscv_cpu_type_infos) 938