1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "qemu/error-report.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "fpu/softfloat-helpers.h" 36 #include "sysemu/kvm.h" 37 #include "kvm_riscv.h" 38 #include "tcg/tcg.h" 39 40 /* RISC-V CPU definitions */ 41 42 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 43 (QEMU_VERSION_MINOR << 8) | \ 44 (QEMU_VERSION_MICRO)) 45 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 46 47 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 48 49 struct isa_ext_data { 50 const char *name; 51 int min_version; 52 int ext_enable_offset; 53 }; 54 55 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ 56 {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 57 58 /* 59 * Here are the ordering rules of extension naming defined by RISC-V 60 * specification : 61 * 1. All extensions should be separated from other multi-letter extensions 62 * by an underscore. 63 * 2. The first letter following the 'Z' conventionally indicates the most 64 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 65 * If multiple 'Z' extensions are named, they should be ordered first 66 * by category, then alphabetically within a category. 67 * 3. Standard supervisor-level extensions (starts with 'S') should be 68 * listed after standard unprivileged extensions. If multiple 69 * supervisor-level extensions are listed, they should be ordered 70 * alphabetically. 71 * 4. Non-standard extensions (starts with 'X') must be listed after all 72 * standard extensions. They must be separated from other multi-letter 73 * extensions by an underscore. 74 * 75 * Single letter extensions are checked in riscv_cpu_validate_misa_priv() 76 * instead. 77 */ 78 static const struct isa_ext_data isa_edata_arr[] = { 79 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), 80 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), 81 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), 82 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), 83 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), 84 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), 85 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), 86 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), 87 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), 88 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), 89 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), 90 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), 91 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), 92 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), 93 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), 94 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), 95 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), 96 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), 97 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), 98 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), 99 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), 100 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), 101 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), 102 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), 103 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), 104 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), 105 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), 106 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), 107 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), 108 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), 109 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), 110 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), 111 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), 112 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), 113 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), 114 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), 115 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), 116 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), 117 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), 118 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), 119 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), 120 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), 121 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), 122 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), 123 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), 124 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), 125 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), 126 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), 127 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), 128 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), 129 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), 130 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), 131 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), 132 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), 133 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 134 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 135 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), 136 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), 137 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 138 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), 139 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), 140 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 141 }; 142 143 static bool isa_ext_is_enabled(RISCVCPU *cpu, 144 const struct isa_ext_data *edata) 145 { 146 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 147 148 return *ext_enabled; 149 } 150 151 static void isa_ext_update_enabled(RISCVCPU *cpu, 152 const struct isa_ext_data *edata, bool en) 153 { 154 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 155 156 *ext_enabled = en; 157 } 158 159 const char * const riscv_int_regnames[] = { 160 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 161 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 162 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 163 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 164 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 165 }; 166 167 const char * const riscv_int_regnamesh[] = { 168 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 169 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 170 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 171 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 172 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 173 "x30h/t5h", "x31h/t6h" 174 }; 175 176 const char * const riscv_fpr_regnames[] = { 177 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 178 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 179 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 180 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 181 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 182 "f30/ft10", "f31/ft11" 183 }; 184 185 static const char * const riscv_excp_names[] = { 186 "misaligned_fetch", 187 "fault_fetch", 188 "illegal_instruction", 189 "breakpoint", 190 "misaligned_load", 191 "fault_load", 192 "misaligned_store", 193 "fault_store", 194 "user_ecall", 195 "supervisor_ecall", 196 "hypervisor_ecall", 197 "machine_ecall", 198 "exec_page_fault", 199 "load_page_fault", 200 "reserved", 201 "store_page_fault", 202 "reserved", 203 "reserved", 204 "reserved", 205 "reserved", 206 "guest_exec_page_fault", 207 "guest_load_page_fault", 208 "reserved", 209 "guest_store_page_fault", 210 }; 211 212 static const char * const riscv_intr_names[] = { 213 "u_software", 214 "s_software", 215 "vs_software", 216 "m_software", 217 "u_timer", 218 "s_timer", 219 "vs_timer", 220 "m_timer", 221 "u_external", 222 "s_external", 223 "vs_external", 224 "m_external", 225 "reserved", 226 "reserved", 227 "reserved", 228 "reserved" 229 }; 230 231 static void register_cpu_props(Object *obj); 232 233 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 234 { 235 if (async) { 236 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 237 riscv_intr_names[cause] : "(unknown)"; 238 } else { 239 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 240 riscv_excp_names[cause] : "(unknown)"; 241 } 242 } 243 244 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 245 { 246 env->misa_mxl_max = env->misa_mxl = mxl; 247 env->misa_ext_mask = env->misa_ext = ext; 248 } 249 250 static void set_priv_version(CPURISCVState *env, int priv_ver) 251 { 252 env->priv_ver = priv_ver; 253 } 254 255 static void set_vext_version(CPURISCVState *env, int vext_ver) 256 { 257 env->vext_ver = vext_ver; 258 } 259 260 #ifndef CONFIG_USER_ONLY 261 static uint8_t satp_mode_from_str(const char *satp_mode_str) 262 { 263 if (!strncmp(satp_mode_str, "mbare", 5)) { 264 return VM_1_10_MBARE; 265 } 266 267 if (!strncmp(satp_mode_str, "sv32", 4)) { 268 return VM_1_10_SV32; 269 } 270 271 if (!strncmp(satp_mode_str, "sv39", 4)) { 272 return VM_1_10_SV39; 273 } 274 275 if (!strncmp(satp_mode_str, "sv48", 4)) { 276 return VM_1_10_SV48; 277 } 278 279 if (!strncmp(satp_mode_str, "sv57", 4)) { 280 return VM_1_10_SV57; 281 } 282 283 if (!strncmp(satp_mode_str, "sv64", 4)) { 284 return VM_1_10_SV64; 285 } 286 287 g_assert_not_reached(); 288 } 289 290 uint8_t satp_mode_max_from_map(uint32_t map) 291 { 292 /* map here has at least one bit set, so no problem with clz */ 293 return 31 - __builtin_clz(map); 294 } 295 296 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) 297 { 298 if (is_32_bit) { 299 switch (satp_mode) { 300 case VM_1_10_SV32: 301 return "sv32"; 302 case VM_1_10_MBARE: 303 return "none"; 304 } 305 } else { 306 switch (satp_mode) { 307 case VM_1_10_SV64: 308 return "sv64"; 309 case VM_1_10_SV57: 310 return "sv57"; 311 case VM_1_10_SV48: 312 return "sv48"; 313 case VM_1_10_SV39: 314 return "sv39"; 315 case VM_1_10_MBARE: 316 return "none"; 317 } 318 } 319 320 g_assert_not_reached(); 321 } 322 323 static void set_satp_mode_max_supported(RISCVCPU *cpu, 324 uint8_t satp_mode) 325 { 326 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 327 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; 328 329 for (int i = 0; i <= satp_mode; ++i) { 330 if (valid_vm[i]) { 331 cpu->cfg.satp_mode.supported |= (1 << i); 332 } 333 } 334 } 335 336 /* Set the satp mode to the max supported */ 337 static void set_satp_mode_default_map(RISCVCPU *cpu) 338 { 339 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; 340 } 341 #endif 342 343 static void riscv_any_cpu_init(Object *obj) 344 { 345 CPURISCVState *env = &RISCV_CPU(obj)->env; 346 #if defined(TARGET_RISCV32) 347 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 348 #elif defined(TARGET_RISCV64) 349 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 350 #endif 351 352 #ifndef CONFIG_USER_ONLY 353 set_satp_mode_max_supported(RISCV_CPU(obj), 354 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? 355 VM_1_10_SV32 : VM_1_10_SV57); 356 #endif 357 358 set_priv_version(env, PRIV_VERSION_1_12_0); 359 register_cpu_props(obj); 360 } 361 362 #if defined(TARGET_RISCV64) 363 static void rv64_base_cpu_init(Object *obj) 364 { 365 CPURISCVState *env = &RISCV_CPU(obj)->env; 366 /* We set this in the realise function */ 367 set_misa(env, MXL_RV64, 0); 368 register_cpu_props(obj); 369 /* Set latest version of privileged specification */ 370 set_priv_version(env, PRIV_VERSION_1_12_0); 371 #ifndef CONFIG_USER_ONLY 372 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 373 #endif 374 } 375 376 static void rv64_sifive_u_cpu_init(Object *obj) 377 { 378 CPURISCVState *env = &RISCV_CPU(obj)->env; 379 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 380 register_cpu_props(obj); 381 set_priv_version(env, PRIV_VERSION_1_10_0); 382 #ifndef CONFIG_USER_ONLY 383 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); 384 #endif 385 } 386 387 static void rv64_sifive_e_cpu_init(Object *obj) 388 { 389 CPURISCVState *env = &RISCV_CPU(obj)->env; 390 RISCVCPU *cpu = RISCV_CPU(obj); 391 392 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 393 register_cpu_props(obj); 394 set_priv_version(env, PRIV_VERSION_1_10_0); 395 cpu->cfg.mmu = false; 396 #ifndef CONFIG_USER_ONLY 397 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 398 #endif 399 } 400 401 static void rv64_thead_c906_cpu_init(Object *obj) 402 { 403 CPURISCVState *env = &RISCV_CPU(obj)->env; 404 RISCVCPU *cpu = RISCV_CPU(obj); 405 406 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 407 set_priv_version(env, PRIV_VERSION_1_11_0); 408 409 cpu->cfg.ext_g = true; 410 cpu->cfg.ext_u = true; 411 cpu->cfg.ext_icsr = true; 412 cpu->cfg.ext_zfh = true; 413 cpu->cfg.mmu = true; 414 cpu->cfg.ext_xtheadba = true; 415 cpu->cfg.ext_xtheadbb = true; 416 cpu->cfg.ext_xtheadbs = true; 417 cpu->cfg.ext_xtheadcmo = true; 418 cpu->cfg.ext_xtheadcondmov = true; 419 cpu->cfg.ext_xtheadfmemidx = true; 420 cpu->cfg.ext_xtheadmac = true; 421 cpu->cfg.ext_xtheadmemidx = true; 422 cpu->cfg.ext_xtheadmempair = true; 423 cpu->cfg.ext_xtheadsync = true; 424 425 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 426 #ifndef CONFIG_USER_ONLY 427 set_satp_mode_max_supported(cpu, VM_1_10_SV39); 428 #endif 429 } 430 431 static void rv128_base_cpu_init(Object *obj) 432 { 433 if (qemu_tcg_mttcg_enabled()) { 434 /* Missing 128-bit aligned atomics */ 435 error_report("128-bit RISC-V currently does not work with Multi " 436 "Threaded TCG. Please use: -accel tcg,thread=single"); 437 exit(EXIT_FAILURE); 438 } 439 CPURISCVState *env = &RISCV_CPU(obj)->env; 440 /* We set this in the realise function */ 441 set_misa(env, MXL_RV128, 0); 442 register_cpu_props(obj); 443 /* Set latest version of privileged specification */ 444 set_priv_version(env, PRIV_VERSION_1_12_0); 445 #ifndef CONFIG_USER_ONLY 446 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 447 #endif 448 } 449 #else 450 static void rv32_base_cpu_init(Object *obj) 451 { 452 CPURISCVState *env = &RISCV_CPU(obj)->env; 453 /* We set this in the realise function */ 454 set_misa(env, MXL_RV32, 0); 455 register_cpu_props(obj); 456 /* Set latest version of privileged specification */ 457 set_priv_version(env, PRIV_VERSION_1_12_0); 458 #ifndef CONFIG_USER_ONLY 459 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 460 #endif 461 } 462 463 static void rv32_sifive_u_cpu_init(Object *obj) 464 { 465 CPURISCVState *env = &RISCV_CPU(obj)->env; 466 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 467 register_cpu_props(obj); 468 set_priv_version(env, PRIV_VERSION_1_10_0); 469 #ifndef CONFIG_USER_ONLY 470 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 471 #endif 472 } 473 474 static void rv32_sifive_e_cpu_init(Object *obj) 475 { 476 CPURISCVState *env = &RISCV_CPU(obj)->env; 477 RISCVCPU *cpu = RISCV_CPU(obj); 478 479 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 480 register_cpu_props(obj); 481 set_priv_version(env, PRIV_VERSION_1_10_0); 482 cpu->cfg.mmu = false; 483 #ifndef CONFIG_USER_ONLY 484 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 485 #endif 486 } 487 488 static void rv32_ibex_cpu_init(Object *obj) 489 { 490 CPURISCVState *env = &RISCV_CPU(obj)->env; 491 RISCVCPU *cpu = RISCV_CPU(obj); 492 493 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 494 register_cpu_props(obj); 495 set_priv_version(env, PRIV_VERSION_1_11_0); 496 cpu->cfg.mmu = false; 497 #ifndef CONFIG_USER_ONLY 498 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 499 #endif 500 cpu->cfg.epmp = true; 501 } 502 503 static void rv32_imafcu_nommu_cpu_init(Object *obj) 504 { 505 CPURISCVState *env = &RISCV_CPU(obj)->env; 506 RISCVCPU *cpu = RISCV_CPU(obj); 507 508 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 509 register_cpu_props(obj); 510 set_priv_version(env, PRIV_VERSION_1_10_0); 511 cpu->cfg.mmu = false; 512 #ifndef CONFIG_USER_ONLY 513 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 514 #endif 515 } 516 #endif 517 518 #if defined(CONFIG_KVM) 519 static void riscv_host_cpu_init(Object *obj) 520 { 521 CPURISCVState *env = &RISCV_CPU(obj)->env; 522 #if defined(TARGET_RISCV32) 523 set_misa(env, MXL_RV32, 0); 524 #elif defined(TARGET_RISCV64) 525 set_misa(env, MXL_RV64, 0); 526 #endif 527 register_cpu_props(obj); 528 } 529 #endif 530 531 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 532 { 533 ObjectClass *oc; 534 char *typename; 535 char **cpuname; 536 537 cpuname = g_strsplit(cpu_model, ",", 1); 538 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 539 oc = object_class_by_name(typename); 540 g_strfreev(cpuname); 541 g_free(typename); 542 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 543 object_class_is_abstract(oc)) { 544 return NULL; 545 } 546 return oc; 547 } 548 549 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 550 { 551 RISCVCPU *cpu = RISCV_CPU(cs); 552 CPURISCVState *env = &cpu->env; 553 int i; 554 555 #if !defined(CONFIG_USER_ONLY) 556 if (riscv_has_ext(env, RVH)) { 557 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); 558 } 559 #endif 560 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 561 #ifndef CONFIG_USER_ONLY 562 { 563 static const int dump_csrs[] = { 564 CSR_MHARTID, 565 CSR_MSTATUS, 566 CSR_MSTATUSH, 567 /* 568 * CSR_SSTATUS is intentionally omitted here as its value 569 * can be figured out by looking at CSR_MSTATUS 570 */ 571 CSR_HSTATUS, 572 CSR_VSSTATUS, 573 CSR_MIP, 574 CSR_MIE, 575 CSR_MIDELEG, 576 CSR_HIDELEG, 577 CSR_MEDELEG, 578 CSR_HEDELEG, 579 CSR_MTVEC, 580 CSR_STVEC, 581 CSR_VSTVEC, 582 CSR_MEPC, 583 CSR_SEPC, 584 CSR_VSEPC, 585 CSR_MCAUSE, 586 CSR_SCAUSE, 587 CSR_VSCAUSE, 588 CSR_MTVAL, 589 CSR_STVAL, 590 CSR_HTVAL, 591 CSR_MTVAL2, 592 CSR_MSCRATCH, 593 CSR_SSCRATCH, 594 CSR_SATP, 595 CSR_MMTE, 596 CSR_UPMBASE, 597 CSR_UPMMASK, 598 CSR_SPMBASE, 599 CSR_SPMMASK, 600 CSR_MPMBASE, 601 CSR_MPMMASK, 602 }; 603 604 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 605 int csrno = dump_csrs[i]; 606 target_ulong val = 0; 607 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 608 609 /* 610 * Rely on the smode, hmode, etc, predicates within csr.c 611 * to do the filtering of the registers that are present. 612 */ 613 if (res == RISCV_EXCP_NONE) { 614 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 615 csr_ops[csrno].name, val); 616 } 617 } 618 } 619 #endif 620 621 for (i = 0; i < 32; i++) { 622 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 623 riscv_int_regnames[i], env->gpr[i]); 624 if ((i & 3) == 3) { 625 qemu_fprintf(f, "\n"); 626 } 627 } 628 if (flags & CPU_DUMP_FPU) { 629 for (i = 0; i < 32; i++) { 630 qemu_fprintf(f, " %-8s %016" PRIx64, 631 riscv_fpr_regnames[i], env->fpr[i]); 632 if ((i & 3) == 3) { 633 qemu_fprintf(f, "\n"); 634 } 635 } 636 } 637 } 638 639 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 640 { 641 RISCVCPU *cpu = RISCV_CPU(cs); 642 CPURISCVState *env = &cpu->env; 643 644 if (env->xl == MXL_RV32) { 645 env->pc = (int32_t)value; 646 } else { 647 env->pc = value; 648 } 649 } 650 651 static vaddr riscv_cpu_get_pc(CPUState *cs) 652 { 653 RISCVCPU *cpu = RISCV_CPU(cs); 654 CPURISCVState *env = &cpu->env; 655 656 /* Match cpu_get_tb_cpu_state. */ 657 if (env->xl == MXL_RV32) { 658 return env->pc & UINT32_MAX; 659 } 660 return env->pc; 661 } 662 663 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 664 const TranslationBlock *tb) 665 { 666 RISCVCPU *cpu = RISCV_CPU(cs); 667 CPURISCVState *env = &cpu->env; 668 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 669 670 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 671 672 if (xl == MXL_RV32) { 673 env->pc = (int32_t) tb->pc; 674 } else { 675 env->pc = tb->pc; 676 } 677 } 678 679 static bool riscv_cpu_has_work(CPUState *cs) 680 { 681 #ifndef CONFIG_USER_ONLY 682 RISCVCPU *cpu = RISCV_CPU(cs); 683 CPURISCVState *env = &cpu->env; 684 /* 685 * Definition of the WFI instruction requires it to ignore the privilege 686 * mode and delegation registers, but respect individual enables 687 */ 688 return riscv_cpu_all_pending(env) != 0; 689 #else 690 return true; 691 #endif 692 } 693 694 static void riscv_restore_state_to_opc(CPUState *cs, 695 const TranslationBlock *tb, 696 const uint64_t *data) 697 { 698 RISCVCPU *cpu = RISCV_CPU(cs); 699 CPURISCVState *env = &cpu->env; 700 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 701 702 if (xl == MXL_RV32) { 703 env->pc = (int32_t)data[0]; 704 } else { 705 env->pc = data[0]; 706 } 707 env->bins = data[1]; 708 } 709 710 static void riscv_cpu_reset_hold(Object *obj) 711 { 712 #ifndef CONFIG_USER_ONLY 713 uint8_t iprio; 714 int i, irq, rdzero; 715 #endif 716 CPUState *cs = CPU(obj); 717 RISCVCPU *cpu = RISCV_CPU(cs); 718 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 719 CPURISCVState *env = &cpu->env; 720 721 if (mcc->parent_phases.hold) { 722 mcc->parent_phases.hold(obj); 723 } 724 #ifndef CONFIG_USER_ONLY 725 env->misa_mxl = env->misa_mxl_max; 726 env->priv = PRV_M; 727 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 728 if (env->misa_mxl > MXL_RV32) { 729 /* 730 * The reset status of SXL/UXL is undefined, but mstatus is WARL 731 * and we must ensure that the value after init is valid for read. 732 */ 733 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 734 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 735 if (riscv_has_ext(env, RVH)) { 736 env->vsstatus = set_field(env->vsstatus, 737 MSTATUS64_SXL, env->misa_mxl); 738 env->vsstatus = set_field(env->vsstatus, 739 MSTATUS64_UXL, env->misa_mxl); 740 env->mstatus_hs = set_field(env->mstatus_hs, 741 MSTATUS64_SXL, env->misa_mxl); 742 env->mstatus_hs = set_field(env->mstatus_hs, 743 MSTATUS64_UXL, env->misa_mxl); 744 } 745 } 746 env->mcause = 0; 747 env->miclaim = MIP_SGEIP; 748 env->pc = env->resetvec; 749 env->bins = 0; 750 env->two_stage_lookup = false; 751 752 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | 753 (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); 754 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | 755 (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); 756 757 /* Initialized default priorities of local interrupts. */ 758 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 759 iprio = riscv_cpu_default_priority(i); 760 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 761 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 762 env->hviprio[i] = 0; 763 } 764 i = 0; 765 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 766 if (!rdzero) { 767 env->hviprio[irq] = env->miprio[irq]; 768 } 769 i++; 770 } 771 /* mmte is supposed to have pm.current hardwired to 1 */ 772 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 773 #endif 774 env->xl = riscv_cpu_mxl(env); 775 riscv_cpu_update_mask(env); 776 cs->exception_index = RISCV_EXCP_NONE; 777 env->load_res = -1; 778 set_default_nan_mode(1, &env->fp_status); 779 780 #ifndef CONFIG_USER_ONLY 781 if (cpu->cfg.debug) { 782 riscv_trigger_init(env); 783 } 784 785 if (kvm_enabled()) { 786 kvm_riscv_reset_vcpu(cpu); 787 } 788 #endif 789 } 790 791 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 792 { 793 RISCVCPU *cpu = RISCV_CPU(s); 794 795 switch (riscv_cpu_mxl(&cpu->env)) { 796 case MXL_RV32: 797 info->print_insn = print_insn_riscv32; 798 break; 799 case MXL_RV64: 800 info->print_insn = print_insn_riscv64; 801 break; 802 case MXL_RV128: 803 info->print_insn = print_insn_riscv128; 804 break; 805 default: 806 g_assert_not_reached(); 807 } 808 } 809 810 /* 811 * Check consistency between chosen extensions while setting 812 * cpu->cfg accordingly. 813 */ 814 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 815 { 816 CPURISCVState *env = &cpu->env; 817 818 /* Do some ISA extension error checking */ 819 if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && 820 riscv_has_ext(env, RVM) && 821 riscv_has_ext(env, RVA) && 822 riscv_has_ext(env, RVF) && 823 riscv_has_ext(env, RVD) && 824 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 825 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 826 cpu->cfg.ext_icsr = true; 827 cpu->cfg.ext_ifencei = true; 828 829 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; 830 env->misa_ext_mask = env->misa_ext; 831 } 832 833 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 834 error_setg(errp, 835 "I and E extensions are incompatible"); 836 return; 837 } 838 839 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 840 error_setg(errp, 841 "Either I or E extension must be set"); 842 return; 843 } 844 845 if (riscv_has_ext(env, RVS) && !cpu->cfg.ext_u) { 846 error_setg(errp, 847 "Setting S extension without U extension is illegal"); 848 return; 849 } 850 851 if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) { 852 error_setg(errp, 853 "H depends on an I base integer ISA with 32 x registers"); 854 return; 855 } 856 857 if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) { 858 error_setg(errp, "H extension implicitly requires S-mode"); 859 return; 860 } 861 862 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { 863 error_setg(errp, "F extension requires Zicsr"); 864 return; 865 } 866 867 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 868 error_setg(errp, "Zawrs extension requires A extension"); 869 return; 870 } 871 872 if (cpu->cfg.ext_zfh) { 873 cpu->cfg.ext_zfhmin = true; 874 } 875 876 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 877 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 878 return; 879 } 880 881 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 882 error_setg(errp, "D extension requires F extension"); 883 return; 884 } 885 886 /* The V vector extension depends on the Zve64d extension */ 887 if (cpu->cfg.ext_v) { 888 cpu->cfg.ext_zve64d = true; 889 } 890 891 /* The Zve64d extension depends on the Zve64f extension */ 892 if (cpu->cfg.ext_zve64d) { 893 cpu->cfg.ext_zve64f = true; 894 } 895 896 /* The Zve64f extension depends on the Zve32f extension */ 897 if (cpu->cfg.ext_zve64f) { 898 cpu->cfg.ext_zve32f = true; 899 } 900 901 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 902 error_setg(errp, "Zve64d/V extensions require D extension"); 903 return; 904 } 905 906 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 907 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 908 return; 909 } 910 911 if (cpu->cfg.ext_zvfh) { 912 cpu->cfg.ext_zvfhmin = true; 913 } 914 915 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 916 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 917 return; 918 } 919 920 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 921 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 922 return; 923 } 924 925 /* Set the ISA extensions, checks should have happened above */ 926 if (cpu->cfg.ext_zhinx) { 927 cpu->cfg.ext_zhinxmin = true; 928 } 929 930 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { 931 cpu->cfg.ext_zfinx = true; 932 } 933 934 if (cpu->cfg.ext_zfinx) { 935 if (!cpu->cfg.ext_icsr) { 936 error_setg(errp, "Zfinx extension requires Zicsr"); 937 return; 938 } 939 if (riscv_has_ext(env, RVF)) { 940 error_setg(errp, 941 "Zfinx cannot be supported together with F extension"); 942 return; 943 } 944 } 945 946 if (cpu->cfg.ext_zce) { 947 cpu->cfg.ext_zca = true; 948 cpu->cfg.ext_zcb = true; 949 cpu->cfg.ext_zcmp = true; 950 cpu->cfg.ext_zcmt = true; 951 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 952 cpu->cfg.ext_zcf = true; 953 } 954 } 955 956 if (riscv_has_ext(env, RVC)) { 957 cpu->cfg.ext_zca = true; 958 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 959 cpu->cfg.ext_zcf = true; 960 } 961 if (riscv_has_ext(env, RVD)) { 962 cpu->cfg.ext_zcd = true; 963 } 964 } 965 966 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 967 error_setg(errp, "Zcf extension is only relevant to RV32"); 968 return; 969 } 970 971 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 972 error_setg(errp, "Zcf extension requires F extension"); 973 return; 974 } 975 976 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 977 error_setg(errp, "Zcd extension requires D extension"); 978 return; 979 } 980 981 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 982 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 983 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 984 "extension"); 985 return; 986 } 987 988 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 989 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 990 "Zcd extension"); 991 return; 992 } 993 994 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { 995 error_setg(errp, "Zcmt extension requires Zicsr extension"); 996 return; 997 } 998 999 if (cpu->cfg.ext_zk) { 1000 cpu->cfg.ext_zkn = true; 1001 cpu->cfg.ext_zkr = true; 1002 cpu->cfg.ext_zkt = true; 1003 } 1004 1005 if (cpu->cfg.ext_zkn) { 1006 cpu->cfg.ext_zbkb = true; 1007 cpu->cfg.ext_zbkc = true; 1008 cpu->cfg.ext_zbkx = true; 1009 cpu->cfg.ext_zkne = true; 1010 cpu->cfg.ext_zknd = true; 1011 cpu->cfg.ext_zknh = true; 1012 } 1013 1014 if (cpu->cfg.ext_zks) { 1015 cpu->cfg.ext_zbkb = true; 1016 cpu->cfg.ext_zbkc = true; 1017 cpu->cfg.ext_zbkx = true; 1018 cpu->cfg.ext_zksed = true; 1019 cpu->cfg.ext_zksh = true; 1020 } 1021 1022 if (cpu->cfg.ext_v) { 1023 int vext_version = VEXT_VERSION_1_00_0; 1024 if (!is_power_of_2(cpu->cfg.vlen)) { 1025 error_setg(errp, 1026 "Vector extension VLEN must be power of 2"); 1027 return; 1028 } 1029 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 1030 error_setg(errp, 1031 "Vector extension implementation only supports VLEN " 1032 "in the range [128, %d]", RV_VLEN_MAX); 1033 return; 1034 } 1035 if (!is_power_of_2(cpu->cfg.elen)) { 1036 error_setg(errp, 1037 "Vector extension ELEN must be power of 2"); 1038 return; 1039 } 1040 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 1041 error_setg(errp, 1042 "Vector extension implementation only supports ELEN " 1043 "in the range [8, 64]"); 1044 return; 1045 } 1046 if (cpu->cfg.vext_spec) { 1047 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 1048 vext_version = VEXT_VERSION_1_00_0; 1049 } else { 1050 error_setg(errp, 1051 "Unsupported vector spec version '%s'", 1052 cpu->cfg.vext_spec); 1053 return; 1054 } 1055 } else { 1056 qemu_log("vector version is not specified, " 1057 "use the default value v1.0\n"); 1058 } 1059 set_vext_version(env, vext_version); 1060 } 1061 } 1062 1063 #ifndef CONFIG_USER_ONLY 1064 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) 1065 { 1066 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 1067 uint8_t satp_mode_map_max; 1068 uint8_t satp_mode_supported_max = 1069 satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 1070 1071 if (cpu->cfg.satp_mode.map == 0) { 1072 if (cpu->cfg.satp_mode.init == 0) { 1073 /* If unset by the user, we fallback to the default satp mode. */ 1074 set_satp_mode_default_map(cpu); 1075 } else { 1076 /* 1077 * Find the lowest level that was disabled and then enable the 1078 * first valid level below which can be found in 1079 * valid_vm_1_10_32/64. 1080 */ 1081 for (int i = 1; i < 16; ++i) { 1082 if ((cpu->cfg.satp_mode.init & (1 << i)) && 1083 (cpu->cfg.satp_mode.supported & (1 << i))) { 1084 for (int j = i - 1; j >= 0; --j) { 1085 if (cpu->cfg.satp_mode.supported & (1 << j)) { 1086 cpu->cfg.satp_mode.map |= (1 << j); 1087 break; 1088 } 1089 } 1090 break; 1091 } 1092 } 1093 } 1094 } 1095 1096 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 1097 1098 /* Make sure the user asked for a supported configuration (HW and qemu) */ 1099 if (satp_mode_map_max > satp_mode_supported_max) { 1100 error_setg(errp, "satp_mode %s is higher than hw max capability %s", 1101 satp_mode_str(satp_mode_map_max, rv32), 1102 satp_mode_str(satp_mode_supported_max, rv32)); 1103 return; 1104 } 1105 1106 /* 1107 * Make sure the user did not ask for an invalid configuration as per 1108 * the specification. 1109 */ 1110 if (!rv32) { 1111 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1112 if (!(cpu->cfg.satp_mode.map & (1 << i)) && 1113 (cpu->cfg.satp_mode.init & (1 << i)) && 1114 (cpu->cfg.satp_mode.supported & (1 << i))) { 1115 error_setg(errp, "cannot disable %s satp mode if %s " 1116 "is enabled", satp_mode_str(i, false), 1117 satp_mode_str(satp_mode_map_max, false)); 1118 return; 1119 } 1120 } 1121 } 1122 1123 /* Finally expand the map so that all valid modes are set */ 1124 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1125 if (cpu->cfg.satp_mode.supported & (1 << i)) { 1126 cpu->cfg.satp_mode.map |= (1 << i); 1127 } 1128 } 1129 } 1130 #endif 1131 1132 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1133 { 1134 #ifndef CONFIG_USER_ONLY 1135 Error *local_err = NULL; 1136 1137 riscv_cpu_satp_mode_finalize(cpu, &local_err); 1138 if (local_err != NULL) { 1139 error_propagate(errp, local_err); 1140 return; 1141 } 1142 #endif 1143 } 1144 1145 static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) 1146 { 1147 uint32_t ext = 0; 1148 1149 if (riscv_has_ext(env, RVI)) { 1150 ext |= RVI; 1151 } 1152 if (riscv_has_ext(env, RVE)) { 1153 ext |= RVE; 1154 } 1155 if (riscv_has_ext(env, RVM)) { 1156 ext |= RVM; 1157 } 1158 if (riscv_has_ext(env, RVA)) { 1159 ext |= RVA; 1160 } 1161 if (riscv_has_ext(env, RVF)) { 1162 ext |= RVF; 1163 } 1164 if (riscv_has_ext(env, RVD)) { 1165 ext |= RVD; 1166 } 1167 if (riscv_has_ext(env, RVC)) { 1168 ext |= RVC; 1169 } 1170 if (riscv_has_ext(env, RVS)) { 1171 ext |= RVS; 1172 } 1173 if (riscv_cpu_cfg(env)->ext_u) { 1174 ext |= RVU; 1175 } 1176 if (riscv_cpu_cfg(env)->ext_h) { 1177 ext |= RVH; 1178 } 1179 if (riscv_cpu_cfg(env)->ext_v) { 1180 ext |= RVV; 1181 } 1182 if (riscv_cpu_cfg(env)->ext_j) { 1183 ext |= RVJ; 1184 } 1185 1186 env->misa_ext = env->misa_ext_mask = ext; 1187 } 1188 1189 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 1190 { 1191 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 1192 error_setg(errp, "H extension requires priv spec 1.12.0"); 1193 return; 1194 } 1195 } 1196 1197 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 1198 { 1199 CPUState *cs = CPU(dev); 1200 RISCVCPU *cpu = RISCV_CPU(dev); 1201 CPURISCVState *env = &cpu->env; 1202 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 1203 CPUClass *cc = CPU_CLASS(mcc); 1204 int i, priv_version = -1; 1205 Error *local_err = NULL; 1206 1207 cpu_exec_realizefn(cs, &local_err); 1208 if (local_err != NULL) { 1209 error_propagate(errp, local_err); 1210 return; 1211 } 1212 1213 if (cpu->cfg.priv_spec) { 1214 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 1215 priv_version = PRIV_VERSION_1_12_0; 1216 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 1217 priv_version = PRIV_VERSION_1_11_0; 1218 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 1219 priv_version = PRIV_VERSION_1_10_0; 1220 } else { 1221 error_setg(errp, 1222 "Unsupported privilege spec version '%s'", 1223 cpu->cfg.priv_spec); 1224 return; 1225 } 1226 } 1227 1228 if (priv_version >= PRIV_VERSION_1_10_0) { 1229 set_priv_version(env, priv_version); 1230 } 1231 1232 /* 1233 * We can't be sure of whether we set defaults during cpu_init() 1234 * or whether the user enabled/disabled some bits via cpu->cfg 1235 * flags. Sync env->misa_ext with cpu->cfg now to allow us to 1236 * use just env->misa_ext later. 1237 */ 1238 riscv_cpu_sync_misa_cfg(env); 1239 1240 riscv_cpu_validate_misa_priv(env, &local_err); 1241 if (local_err != NULL) { 1242 error_propagate(errp, local_err); 1243 return; 1244 } 1245 1246 /* Force disable extensions if priv spec version does not match */ 1247 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1248 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 1249 (env->priv_ver < isa_edata_arr[i].min_version)) { 1250 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 1251 #ifndef CONFIG_USER_ONLY 1252 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 1253 " because privilege spec version does not match", 1254 isa_edata_arr[i].name, env->mhartid); 1255 #else 1256 warn_report("disabling %s extension because " 1257 "privilege spec version does not match", 1258 isa_edata_arr[i].name); 1259 #endif 1260 } 1261 } 1262 1263 if (cpu->cfg.epmp && !cpu->cfg.pmp) { 1264 /* 1265 * Enhanced PMP should only be available 1266 * on harts with PMP support 1267 */ 1268 error_setg(errp, "Invalid configuration: EPMP requires PMP support"); 1269 return; 1270 } 1271 1272 1273 #ifndef CONFIG_USER_ONLY 1274 if (cpu->cfg.ext_sstc) { 1275 riscv_timer_init(cpu); 1276 } 1277 #endif /* CONFIG_USER_ONLY */ 1278 1279 /* Validate that MISA_MXL is set properly. */ 1280 switch (env->misa_mxl_max) { 1281 #ifdef TARGET_RISCV64 1282 case MXL_RV64: 1283 case MXL_RV128: 1284 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 1285 break; 1286 #endif 1287 case MXL_RV32: 1288 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 1289 break; 1290 default: 1291 g_assert_not_reached(); 1292 } 1293 assert(env->misa_mxl_max == env->misa_mxl); 1294 1295 riscv_cpu_validate_set_extensions(cpu, &local_err); 1296 if (local_err != NULL) { 1297 error_propagate(errp, local_err); 1298 return; 1299 } 1300 1301 #ifndef CONFIG_USER_ONLY 1302 if (cpu->cfg.pmu_num) { 1303 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 1304 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1305 riscv_pmu_timer_cb, cpu); 1306 } 1307 } 1308 #endif 1309 1310 riscv_cpu_finalize_features(cpu, &local_err); 1311 if (local_err != NULL) { 1312 error_propagate(errp, local_err); 1313 return; 1314 } 1315 1316 riscv_cpu_register_gdb_regs_for_features(cs); 1317 1318 qemu_init_vcpu(cs); 1319 cpu_reset(cs); 1320 1321 mcc->parent_realize(dev, errp); 1322 } 1323 1324 #ifndef CONFIG_USER_ONLY 1325 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, 1326 void *opaque, Error **errp) 1327 { 1328 RISCVSATPMap *satp_map = opaque; 1329 uint8_t satp = satp_mode_from_str(name); 1330 bool value; 1331 1332 value = satp_map->map & (1 << satp); 1333 1334 visit_type_bool(v, name, &value, errp); 1335 } 1336 1337 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, 1338 void *opaque, Error **errp) 1339 { 1340 RISCVSATPMap *satp_map = opaque; 1341 uint8_t satp = satp_mode_from_str(name); 1342 bool value; 1343 1344 if (!visit_type_bool(v, name, &value, errp)) { 1345 return; 1346 } 1347 1348 satp_map->map = deposit32(satp_map->map, satp, 1, value); 1349 satp_map->init |= 1 << satp; 1350 } 1351 1352 static void riscv_add_satp_mode_properties(Object *obj) 1353 { 1354 RISCVCPU *cpu = RISCV_CPU(obj); 1355 1356 if (cpu->env.misa_mxl == MXL_RV32) { 1357 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, 1358 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1359 } else { 1360 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, 1361 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1362 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, 1363 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1364 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, 1365 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1366 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, 1367 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1368 } 1369 } 1370 1371 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1372 { 1373 RISCVCPU *cpu = RISCV_CPU(opaque); 1374 CPURISCVState *env = &cpu->env; 1375 1376 if (irq < IRQ_LOCAL_MAX) { 1377 switch (irq) { 1378 case IRQ_U_SOFT: 1379 case IRQ_S_SOFT: 1380 case IRQ_VS_SOFT: 1381 case IRQ_M_SOFT: 1382 case IRQ_U_TIMER: 1383 case IRQ_S_TIMER: 1384 case IRQ_VS_TIMER: 1385 case IRQ_M_TIMER: 1386 case IRQ_U_EXT: 1387 case IRQ_VS_EXT: 1388 case IRQ_M_EXT: 1389 if (kvm_enabled()) { 1390 kvm_riscv_set_irq(cpu, irq, level); 1391 } else { 1392 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); 1393 } 1394 break; 1395 case IRQ_S_EXT: 1396 if (kvm_enabled()) { 1397 kvm_riscv_set_irq(cpu, irq, level); 1398 } else { 1399 env->external_seip = level; 1400 riscv_cpu_update_mip(env, 1 << irq, 1401 BOOL_TO_MASK(level | env->software_seip)); 1402 } 1403 break; 1404 default: 1405 g_assert_not_reached(); 1406 } 1407 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1408 /* Require H-extension for handling guest local interrupts */ 1409 if (!riscv_has_ext(env, RVH)) { 1410 g_assert_not_reached(); 1411 } 1412 1413 /* Compute bit position in HGEIP CSR */ 1414 irq = irq - IRQ_LOCAL_MAX + 1; 1415 if (env->geilen < irq) { 1416 g_assert_not_reached(); 1417 } 1418 1419 /* Update HGEIP CSR */ 1420 env->hgeip &= ~((target_ulong)1 << irq); 1421 if (level) { 1422 env->hgeip |= (target_ulong)1 << irq; 1423 } 1424 1425 /* Update mip.SGEIP bit */ 1426 riscv_cpu_update_mip(env, MIP_SGEIP, 1427 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1428 } else { 1429 g_assert_not_reached(); 1430 } 1431 } 1432 #endif /* CONFIG_USER_ONLY */ 1433 1434 static void riscv_cpu_init(Object *obj) 1435 { 1436 RISCVCPU *cpu = RISCV_CPU(obj); 1437 1438 cpu->cfg.ext_ifencei = true; 1439 cpu->cfg.ext_icsr = true; 1440 cpu->cfg.mmu = true; 1441 cpu->cfg.pmp = true; 1442 1443 cpu_set_cpustate_pointers(cpu); 1444 1445 #ifndef CONFIG_USER_ONLY 1446 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1447 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1448 #endif /* CONFIG_USER_ONLY */ 1449 } 1450 1451 typedef struct RISCVCPUMisaExtConfig { 1452 const char *name; 1453 const char *description; 1454 target_ulong misa_bit; 1455 bool enabled; 1456 } RISCVCPUMisaExtConfig; 1457 1458 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1459 void *opaque, Error **errp) 1460 { 1461 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1462 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1463 RISCVCPU *cpu = RISCV_CPU(obj); 1464 CPURISCVState *env = &cpu->env; 1465 bool value; 1466 1467 if (!visit_type_bool(v, name, &value, errp)) { 1468 return; 1469 } 1470 1471 if (value) { 1472 env->misa_ext |= misa_bit; 1473 env->misa_ext_mask |= misa_bit; 1474 } else { 1475 env->misa_ext &= ~misa_bit; 1476 env->misa_ext_mask &= ~misa_bit; 1477 } 1478 } 1479 1480 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1481 void *opaque, Error **errp) 1482 { 1483 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1484 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1485 RISCVCPU *cpu = RISCV_CPU(obj); 1486 CPURISCVState *env = &cpu->env; 1487 bool value; 1488 1489 value = env->misa_ext & misa_bit; 1490 1491 visit_type_bool(v, name, &value, errp); 1492 } 1493 1494 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1495 {.name = "a", .description = "Atomic instructions", 1496 .misa_bit = RVA, .enabled = true}, 1497 {.name = "c", .description = "Compressed instructions", 1498 .misa_bit = RVC, .enabled = true}, 1499 {.name = "d", .description = "Double-precision float point", 1500 .misa_bit = RVD, .enabled = true}, 1501 {.name = "f", .description = "Single-precision float point", 1502 .misa_bit = RVF, .enabled = true}, 1503 {.name = "i", .description = "Base integer instruction set", 1504 .misa_bit = RVI, .enabled = true}, 1505 {.name = "e", .description = "Base integer instruction set (embedded)", 1506 .misa_bit = RVE, .enabled = false}, 1507 {.name = "m", .description = "Integer multiplication and division", 1508 .misa_bit = RVM, .enabled = true}, 1509 {.name = "s", .description = "Supervisor-level instructions", 1510 .misa_bit = RVS, .enabled = true}, 1511 }; 1512 1513 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1514 { 1515 int i; 1516 1517 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1518 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1519 1520 object_property_add(cpu_obj, misa_cfg->name, "bool", 1521 cpu_get_misa_ext_cfg, 1522 cpu_set_misa_ext_cfg, 1523 NULL, (void *)misa_cfg); 1524 object_property_set_description(cpu_obj, misa_cfg->name, 1525 misa_cfg->description); 1526 object_property_set_bool(cpu_obj, misa_cfg->name, 1527 misa_cfg->enabled, NULL); 1528 } 1529 } 1530 1531 static Property riscv_cpu_extensions[] = { 1532 /* Defaults for standard extensions */ 1533 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1534 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1535 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1536 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1537 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1538 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1539 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1540 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1541 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1542 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1543 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1544 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1545 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1546 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1547 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), 1548 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1549 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1550 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1551 1552 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1553 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1554 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1555 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1556 1557 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), 1558 1559 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1560 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1561 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1562 1563 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1564 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1565 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1566 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1567 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1568 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1569 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1570 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1571 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1572 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1573 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1574 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1575 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1576 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1577 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1578 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1579 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1580 1581 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1582 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1583 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1584 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1585 1586 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), 1587 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), 1588 DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), 1589 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), 1590 1591 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1592 1593 /* Vendor-specific custom extensions */ 1594 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1595 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1596 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1597 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1598 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1599 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1600 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1601 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1602 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1603 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1604 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1605 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1606 1607 /* These are experimental so mark with 'x-' */ 1608 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), 1609 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1610 1611 DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), 1612 DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), 1613 DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), 1614 DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), 1615 DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), 1616 DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), 1617 DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), 1618 1619 /* ePMP 0.9.3 */ 1620 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1621 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1622 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1623 1624 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), 1625 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), 1626 1627 DEFINE_PROP_END_OF_LIST(), 1628 }; 1629 1630 /* 1631 * Register CPU props based on env.misa_ext. If a non-zero 1632 * value was set, register only the required cpu->cfg.ext_* 1633 * properties and leave. env.misa_ext = 0 means that we want 1634 * all the default properties to be registered. 1635 */ 1636 static void register_cpu_props(Object *obj) 1637 { 1638 RISCVCPU *cpu = RISCV_CPU(obj); 1639 uint32_t misa_ext = cpu->env.misa_ext; 1640 Property *prop; 1641 DeviceState *dev = DEVICE(obj); 1642 1643 /* 1644 * If misa_ext is not zero, set cfg properties now to 1645 * allow them to be read during riscv_cpu_realize() 1646 * later on. 1647 */ 1648 if (cpu->env.misa_ext != 0) { 1649 cpu->cfg.ext_v = misa_ext & RVV; 1650 cpu->cfg.ext_u = misa_ext & RVU; 1651 cpu->cfg.ext_h = misa_ext & RVH; 1652 cpu->cfg.ext_j = misa_ext & RVJ; 1653 1654 /* 1655 * We don't want to set the default riscv_cpu_extensions 1656 * in this case. 1657 */ 1658 return; 1659 } 1660 1661 riscv_cpu_add_misa_properties(obj); 1662 1663 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1664 qdev_property_add_static(dev, prop); 1665 } 1666 1667 #ifndef CONFIG_USER_ONLY 1668 riscv_add_satp_mode_properties(obj); 1669 #endif 1670 } 1671 1672 static Property riscv_cpu_properties[] = { 1673 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1674 1675 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1676 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1677 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1678 1679 #ifndef CONFIG_USER_ONLY 1680 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1681 #endif 1682 1683 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1684 1685 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1686 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1687 1688 /* 1689 * write_misa() is marked as experimental for now so mark 1690 * it with -x and default to 'false'. 1691 */ 1692 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1693 DEFINE_PROP_END_OF_LIST(), 1694 }; 1695 1696 static gchar *riscv_gdb_arch_name(CPUState *cs) 1697 { 1698 RISCVCPU *cpu = RISCV_CPU(cs); 1699 CPURISCVState *env = &cpu->env; 1700 1701 switch (riscv_cpu_mxl(env)) { 1702 case MXL_RV32: 1703 return g_strdup("riscv:rv32"); 1704 case MXL_RV64: 1705 case MXL_RV128: 1706 return g_strdup("riscv:rv64"); 1707 default: 1708 g_assert_not_reached(); 1709 } 1710 } 1711 1712 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1713 { 1714 RISCVCPU *cpu = RISCV_CPU(cs); 1715 1716 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1717 return cpu->dyn_csr_xml; 1718 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1719 return cpu->dyn_vreg_xml; 1720 } 1721 1722 return NULL; 1723 } 1724 1725 #ifndef CONFIG_USER_ONLY 1726 static int64_t riscv_get_arch_id(CPUState *cs) 1727 { 1728 RISCVCPU *cpu = RISCV_CPU(cs); 1729 1730 return cpu->env.mhartid; 1731 } 1732 1733 #include "hw/core/sysemu-cpu-ops.h" 1734 1735 static const struct SysemuCPUOps riscv_sysemu_ops = { 1736 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1737 .write_elf64_note = riscv_cpu_write_elf64_note, 1738 .write_elf32_note = riscv_cpu_write_elf32_note, 1739 .legacy_vmsd = &vmstate_riscv_cpu, 1740 }; 1741 #endif 1742 1743 #include "hw/core/tcg-cpu-ops.h" 1744 1745 static const struct TCGCPUOps riscv_tcg_ops = { 1746 .initialize = riscv_translate_init, 1747 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1748 .restore_state_to_opc = riscv_restore_state_to_opc, 1749 1750 #ifndef CONFIG_USER_ONLY 1751 .tlb_fill = riscv_cpu_tlb_fill, 1752 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1753 .do_interrupt = riscv_cpu_do_interrupt, 1754 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1755 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1756 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1757 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1758 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1759 #endif /* !CONFIG_USER_ONLY */ 1760 }; 1761 1762 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1763 { 1764 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1765 CPUClass *cc = CPU_CLASS(c); 1766 DeviceClass *dc = DEVICE_CLASS(c); 1767 ResettableClass *rc = RESETTABLE_CLASS(c); 1768 1769 device_class_set_parent_realize(dc, riscv_cpu_realize, 1770 &mcc->parent_realize); 1771 1772 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1773 &mcc->parent_phases); 1774 1775 cc->class_by_name = riscv_cpu_class_by_name; 1776 cc->has_work = riscv_cpu_has_work; 1777 cc->dump_state = riscv_cpu_dump_state; 1778 cc->set_pc = riscv_cpu_set_pc; 1779 cc->get_pc = riscv_cpu_get_pc; 1780 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1781 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1782 cc->gdb_num_core_regs = 33; 1783 cc->gdb_stop_before_watchpoint = true; 1784 cc->disas_set_info = riscv_cpu_disas_set_info; 1785 #ifndef CONFIG_USER_ONLY 1786 cc->sysemu_ops = &riscv_sysemu_ops; 1787 cc->get_arch_id = riscv_get_arch_id; 1788 #endif 1789 cc->gdb_arch_name = riscv_gdb_arch_name; 1790 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1791 cc->tcg_ops = &riscv_tcg_ops; 1792 1793 device_class_set_props(dc, riscv_cpu_properties); 1794 } 1795 1796 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, 1797 int max_str_len) 1798 { 1799 char *old = *isa_str; 1800 char *new = *isa_str; 1801 int i; 1802 1803 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1804 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1805 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1806 g_free(old); 1807 old = new; 1808 } 1809 } 1810 1811 *isa_str = new; 1812 } 1813 1814 char *riscv_isa_string(RISCVCPU *cpu) 1815 { 1816 int i; 1817 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1818 char *isa_str = g_new(char, maxlen); 1819 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1820 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1821 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1822 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1823 } 1824 } 1825 *p = '\0'; 1826 if (!cpu->cfg.short_isa_string) { 1827 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1828 } 1829 return isa_str; 1830 } 1831 1832 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1833 { 1834 ObjectClass *class_a = (ObjectClass *)a; 1835 ObjectClass *class_b = (ObjectClass *)b; 1836 const char *name_a, *name_b; 1837 1838 name_a = object_class_get_name(class_a); 1839 name_b = object_class_get_name(class_b); 1840 return strcmp(name_a, name_b); 1841 } 1842 1843 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1844 { 1845 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1846 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1847 1848 qemu_printf("%.*s\n", len, typename); 1849 } 1850 1851 void riscv_cpu_list(void) 1852 { 1853 GSList *list; 1854 1855 list = object_class_get_list(TYPE_RISCV_CPU, false); 1856 list = g_slist_sort(list, riscv_cpu_list_compare); 1857 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1858 g_slist_free(list); 1859 } 1860 1861 #define DEFINE_CPU(type_name, initfn) \ 1862 { \ 1863 .name = type_name, \ 1864 .parent = TYPE_RISCV_CPU, \ 1865 .instance_init = initfn \ 1866 } 1867 1868 static const TypeInfo riscv_cpu_type_infos[] = { 1869 { 1870 .name = TYPE_RISCV_CPU, 1871 .parent = TYPE_CPU, 1872 .instance_size = sizeof(RISCVCPU), 1873 .instance_align = __alignof__(RISCVCPU), 1874 .instance_init = riscv_cpu_init, 1875 .abstract = true, 1876 .class_size = sizeof(RISCVCPUClass), 1877 .class_init = riscv_cpu_class_init, 1878 }, 1879 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1880 #if defined(CONFIG_KVM) 1881 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1882 #endif 1883 #if defined(TARGET_RISCV32) 1884 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1885 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1886 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1887 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1888 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1889 #elif defined(TARGET_RISCV64) 1890 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1891 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1892 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1893 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1894 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1895 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1896 #endif 1897 }; 1898 1899 DEFINE_TYPES(riscv_cpu_type_infos) 1900