xref: /openbmc/qemu/target/riscv/cpu.c (revision e7b5dfd3)
1 /*
2  * QEMU RISC-V CPU
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
23 #include "qemu/log.h"
24 #include "cpu.h"
25 #include "exec/exec-all.h"
26 #include "qapi/error.h"
27 #include "qemu/error-report.h"
28 #include "hw/qdev-properties.h"
29 #include "migration/vmstate.h"
30 #include "fpu/softfloat-helpers.h"
31 
32 /* RISC-V CPU definitions */
33 
34 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG";
35 
36 const char * const riscv_int_regnames[] = {
37   "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
38   "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
39   "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
40   "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
41   "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
42 };
43 
44 const char * const riscv_fpr_regnames[] = {
45   "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
46   "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
47   "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
48   "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
49   "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
50   "f30/ft10", "f31/ft11"
51 };
52 
53 const char * const riscv_excp_names[] = {
54     "misaligned_fetch",
55     "fault_fetch",
56     "illegal_instruction",
57     "breakpoint",
58     "misaligned_load",
59     "fault_load",
60     "misaligned_store",
61     "fault_store",
62     "user_ecall",
63     "supervisor_ecall",
64     "hypervisor_ecall",
65     "machine_ecall",
66     "exec_page_fault",
67     "load_page_fault",
68     "reserved",
69     "store_page_fault",
70     "reserved",
71     "reserved",
72     "reserved",
73     "reserved",
74     "guest_exec_page_fault",
75     "guest_load_page_fault",
76     "reserved",
77     "guest_store_page_fault",
78 };
79 
80 const char * const riscv_intr_names[] = {
81     "u_software",
82     "s_software",
83     "vs_software",
84     "m_software",
85     "u_timer",
86     "s_timer",
87     "vs_timer",
88     "m_timer",
89     "u_external",
90     "vs_external",
91     "h_external",
92     "m_external",
93     "reserved",
94     "reserved",
95     "reserved",
96     "reserved"
97 };
98 
99 static void set_misa(CPURISCVState *env, target_ulong misa)
100 {
101     env->misa_mask = env->misa = misa;
102 }
103 
104 static void set_priv_version(CPURISCVState *env, int priv_ver)
105 {
106     env->priv_ver = priv_ver;
107 }
108 
109 static void set_feature(CPURISCVState *env, int feature)
110 {
111     env->features |= (1ULL << feature);
112 }
113 
114 static void set_resetvec(CPURISCVState *env, int resetvec)
115 {
116 #ifndef CONFIG_USER_ONLY
117     env->resetvec = resetvec;
118 #endif
119 }
120 
121 static void riscv_any_cpu_init(Object *obj)
122 {
123     CPURISCVState *env = &RISCV_CPU(obj)->env;
124     set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
125     set_priv_version(env, PRIV_VERSION_1_11_0);
126     set_resetvec(env, DEFAULT_RSTVEC);
127 }
128 
129 static void riscv_base_cpu_init(Object *obj)
130 {
131     CPURISCVState *env = &RISCV_CPU(obj)->env;
132     /* We set this in the realise function */
133     set_misa(env, 0);
134     set_resetvec(env, DEFAULT_RSTVEC);
135 }
136 
137 #if defined(TARGET_RISCV32)
138 
139 static void rv32gcsu_priv1_10_0_cpu_init(Object *obj)
140 {
141     CPURISCVState *env = &RISCV_CPU(obj)->env;
142     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
143     set_priv_version(env, PRIV_VERSION_1_10_0);
144     set_resetvec(env, DEFAULT_RSTVEC);
145 }
146 
147 static void rv32imcu_nommu_cpu_init(Object *obj)
148 {
149     CPURISCVState *env = &RISCV_CPU(obj)->env;
150     set_misa(env, RV32 | RVI | RVM | RVC | RVU);
151     set_priv_version(env, PRIV_VERSION_1_10_0);
152     set_resetvec(env, 0x8090);
153     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
154 }
155 
156 static void rv32imacu_nommu_cpu_init(Object *obj)
157 {
158     CPURISCVState *env = &RISCV_CPU(obj)->env;
159     set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
160     set_priv_version(env, PRIV_VERSION_1_10_0);
161     set_resetvec(env, DEFAULT_RSTVEC);
162     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
163 }
164 
165 static void rv32imafcu_nommu_cpu_init(Object *obj)
166 {
167     CPURISCVState *env = &RISCV_CPU(obj)->env;
168     set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU);
169     set_priv_version(env, PRIV_VERSION_1_10_0);
170     set_resetvec(env, DEFAULT_RSTVEC);
171     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
172 }
173 
174 #elif defined(TARGET_RISCV64)
175 
176 static void rv64gcsu_priv1_10_0_cpu_init(Object *obj)
177 {
178     CPURISCVState *env = &RISCV_CPU(obj)->env;
179     set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
180     set_priv_version(env, PRIV_VERSION_1_10_0);
181     set_resetvec(env, DEFAULT_RSTVEC);
182 }
183 
184 static void rv64imacu_nommu_cpu_init(Object *obj)
185 {
186     CPURISCVState *env = &RISCV_CPU(obj)->env;
187     set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
188     set_priv_version(env, PRIV_VERSION_1_10_0);
189     set_resetvec(env, DEFAULT_RSTVEC);
190     qdev_prop_set_bit(DEVICE(obj), "mmu", false);
191 }
192 
193 #endif
194 
195 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
196 {
197     ObjectClass *oc;
198     char *typename;
199     char **cpuname;
200 
201     cpuname = g_strsplit(cpu_model, ",", 1);
202     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
203     oc = object_class_by_name(typename);
204     g_strfreev(cpuname);
205     g_free(typename);
206     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
207         object_class_is_abstract(oc)) {
208         return NULL;
209     }
210     return oc;
211 }
212 
213 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
214 {
215     RISCVCPU *cpu = RISCV_CPU(cs);
216     CPURISCVState *env = &cpu->env;
217     int i;
218 
219 #if !defined(CONFIG_USER_ONLY)
220     if (riscv_has_ext(env, RVH)) {
221         qemu_fprintf(f, " %s %d\n", "V      =  ", riscv_cpu_virt_enabled(env));
222     }
223 #endif
224     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
225 #ifndef CONFIG_USER_ONLY
226     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid);
227     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus);
228 #ifdef TARGET_RISCV32
229     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush);
230 #endif
231     if (riscv_has_ext(env, RVH)) {
232         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus);
233         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus);
234     }
235     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip     ", env->mip);
236     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie     ", env->mie);
237     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg);
238     if (riscv_has_ext(env, RVH)) {
239         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg);
240     }
241     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg);
242     if (riscv_has_ext(env, RVH)) {
243         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg);
244     }
245     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec   ", env->mtvec);
246     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec   ", env->stvec);
247     if (riscv_has_ext(env, RVH)) {
248         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec  ", env->vstvec);
249     }
250     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc    ", env->mepc);
251     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc    ", env->sepc);
252     if (riscv_has_ext(env, RVH)) {
253         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc   ", env->vsepc);
254     }
255     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause  ", env->mcause);
256     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause  ", env->scause);
257     if (riscv_has_ext(env, RVH)) {
258         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause);
259     }
260     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval);
261     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr);
262     if (riscv_has_ext(env, RVH)) {
263         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval);
264         qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2);
265     }
266 #endif
267 
268     for (i = 0; i < 32; i++) {
269         qemu_fprintf(f, " %s " TARGET_FMT_lx,
270                      riscv_int_regnames[i], env->gpr[i]);
271         if ((i & 3) == 3) {
272             qemu_fprintf(f, "\n");
273         }
274     }
275     if (flags & CPU_DUMP_FPU) {
276         for (i = 0; i < 32; i++) {
277             qemu_fprintf(f, " %s %016" PRIx64,
278                          riscv_fpr_regnames[i], env->fpr[i]);
279             if ((i & 3) == 3) {
280                 qemu_fprintf(f, "\n");
281             }
282         }
283     }
284 }
285 
286 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
287 {
288     RISCVCPU *cpu = RISCV_CPU(cs);
289     CPURISCVState *env = &cpu->env;
290     env->pc = value;
291 }
292 
293 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
294 {
295     RISCVCPU *cpu = RISCV_CPU(cs);
296     CPURISCVState *env = &cpu->env;
297     env->pc = tb->pc;
298 }
299 
300 static bool riscv_cpu_has_work(CPUState *cs)
301 {
302 #ifndef CONFIG_USER_ONLY
303     RISCVCPU *cpu = RISCV_CPU(cs);
304     CPURISCVState *env = &cpu->env;
305     /*
306      * Definition of the WFI instruction requires it to ignore the privilege
307      * mode and delegation registers, but respect individual enables
308      */
309     return (env->mip & env->mie) != 0;
310 #else
311     return true;
312 #endif
313 }
314 
315 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb,
316                           target_ulong *data)
317 {
318     env->pc = data[0];
319 }
320 
321 static void riscv_cpu_reset(DeviceState *dev)
322 {
323     CPUState *cs = CPU(dev);
324     RISCVCPU *cpu = RISCV_CPU(cs);
325     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
326     CPURISCVState *env = &cpu->env;
327 
328     mcc->parent_reset(dev);
329 #ifndef CONFIG_USER_ONLY
330     env->priv = PRV_M;
331     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
332     env->mcause = 0;
333     env->pc = env->resetvec;
334 #endif
335     cs->exception_index = EXCP_NONE;
336     env->load_res = -1;
337     set_default_nan_mode(1, &env->fp_status);
338 }
339 
340 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
341 {
342 #if defined(TARGET_RISCV32)
343     info->print_insn = print_insn_riscv32;
344 #elif defined(TARGET_RISCV64)
345     info->print_insn = print_insn_riscv64;
346 #endif
347 }
348 
349 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
350 {
351     CPUState *cs = CPU(dev);
352     RISCVCPU *cpu = RISCV_CPU(dev);
353     CPURISCVState *env = &cpu->env;
354     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
355     int priv_version = PRIV_VERSION_1_11_0;
356     target_ulong target_misa = 0;
357     Error *local_err = NULL;
358 
359     cpu_exec_realizefn(cs, &local_err);
360     if (local_err != NULL) {
361         error_propagate(errp, local_err);
362         return;
363     }
364 
365     if (cpu->cfg.priv_spec) {
366         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
367             priv_version = PRIV_VERSION_1_11_0;
368         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
369             priv_version = PRIV_VERSION_1_10_0;
370         } else {
371             error_setg(errp,
372                        "Unsupported privilege spec version '%s'",
373                        cpu->cfg.priv_spec);
374             return;
375         }
376     }
377 
378     set_priv_version(env, priv_version);
379 
380     if (cpu->cfg.mmu) {
381         set_feature(env, RISCV_FEATURE_MMU);
382     }
383 
384     if (cpu->cfg.pmp) {
385         set_feature(env, RISCV_FEATURE_PMP);
386     }
387 
388     /* If misa isn't set (rv32 and rv64 machines) set it here */
389     if (!env->misa) {
390         /* Do some ISA extension error checking */
391         if (cpu->cfg.ext_i && cpu->cfg.ext_e) {
392             error_setg(errp,
393                        "I and E extensions are incompatible");
394                        return;
395        }
396 
397         if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) {
398             error_setg(errp,
399                        "Either I or E extension must be set");
400                        return;
401        }
402 
403        if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m &
404                                cpu->cfg.ext_a & cpu->cfg.ext_f &
405                                cpu->cfg.ext_d)) {
406             warn_report("Setting G will also set IMAFD");
407             cpu->cfg.ext_i = true;
408             cpu->cfg.ext_m = true;
409             cpu->cfg.ext_a = true;
410             cpu->cfg.ext_f = true;
411             cpu->cfg.ext_d = true;
412         }
413 
414         /* Set the ISA extensions, checks should have happened above */
415         if (cpu->cfg.ext_i) {
416             target_misa |= RVI;
417         }
418         if (cpu->cfg.ext_e) {
419             target_misa |= RVE;
420         }
421         if (cpu->cfg.ext_m) {
422             target_misa |= RVM;
423         }
424         if (cpu->cfg.ext_a) {
425             target_misa |= RVA;
426         }
427         if (cpu->cfg.ext_f) {
428             target_misa |= RVF;
429         }
430         if (cpu->cfg.ext_d) {
431             target_misa |= RVD;
432         }
433         if (cpu->cfg.ext_c) {
434             target_misa |= RVC;
435         }
436         if (cpu->cfg.ext_s) {
437             target_misa |= RVS;
438         }
439         if (cpu->cfg.ext_u) {
440             target_misa |= RVU;
441         }
442         if (cpu->cfg.ext_h) {
443             target_misa |= RVH;
444         }
445 
446         set_misa(env, RVXLEN | target_misa);
447     }
448 
449     riscv_cpu_register_gdb_regs_for_features(cs);
450 
451     qemu_init_vcpu(cs);
452     cpu_reset(cs);
453 
454     mcc->parent_realize(dev, errp);
455 }
456 
457 static void riscv_cpu_init(Object *obj)
458 {
459     RISCVCPU *cpu = RISCV_CPU(obj);
460 
461     cpu_set_cpustate_pointers(cpu);
462 }
463 
464 #ifndef CONFIG_USER_ONLY
465 static const VMStateDescription vmstate_riscv_cpu = {
466     .name = "cpu",
467     .unmigratable = 1,
468 };
469 #endif
470 
471 static Property riscv_cpu_properties[] = {
472     DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true),
473     DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false),
474     DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true),
475     DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true),
476     DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true),
477     DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true),
478     DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true),
479     DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
480     DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
481     DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
482     /* This is experimental so mark with 'x-' */
483     DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
484     DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
485     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
486     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
487     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
488     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
489     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
490     DEFINE_PROP_END_OF_LIST(),
491 };
492 
493 static void riscv_cpu_class_init(ObjectClass *c, void *data)
494 {
495     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
496     CPUClass *cc = CPU_CLASS(c);
497     DeviceClass *dc = DEVICE_CLASS(c);
498 
499     device_class_set_parent_realize(dc, riscv_cpu_realize,
500                                     &mcc->parent_realize);
501 
502     device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset);
503 
504     cc->class_by_name = riscv_cpu_class_by_name;
505     cc->has_work = riscv_cpu_has_work;
506     cc->do_interrupt = riscv_cpu_do_interrupt;
507     cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt;
508     cc->dump_state = riscv_cpu_dump_state;
509     cc->set_pc = riscv_cpu_set_pc;
510     cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb;
511     cc->gdb_read_register = riscv_cpu_gdb_read_register;
512     cc->gdb_write_register = riscv_cpu_gdb_write_register;
513     cc->gdb_num_core_regs = 33;
514 #if defined(TARGET_RISCV32)
515     cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
516 #elif defined(TARGET_RISCV64)
517     cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
518 #endif
519     cc->gdb_stop_before_watchpoint = true;
520     cc->disas_set_info = riscv_cpu_disas_set_info;
521 #ifndef CONFIG_USER_ONLY
522     cc->do_transaction_failed = riscv_cpu_do_transaction_failed;
523     cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
524     cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
525     /* For now, mark unmigratable: */
526     cc->vmsd = &vmstate_riscv_cpu;
527 #endif
528 #ifdef CONFIG_TCG
529     cc->tcg_initialize = riscv_translate_init;
530     cc->tlb_fill = riscv_cpu_tlb_fill;
531 #endif
532     device_class_set_props(dc, riscv_cpu_properties);
533 }
534 
535 char *riscv_isa_string(RISCVCPU *cpu)
536 {
537     int i;
538     const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1;
539     char *isa_str = g_new(char, maxlen);
540     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
541     for (i = 0; i < sizeof(riscv_exts); i++) {
542         if (cpu->env.misa & RV(riscv_exts[i])) {
543             *p++ = qemu_tolower(riscv_exts[i]);
544         }
545     }
546     *p = '\0';
547     return isa_str;
548 }
549 
550 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
551 {
552     ObjectClass *class_a = (ObjectClass *)a;
553     ObjectClass *class_b = (ObjectClass *)b;
554     const char *name_a, *name_b;
555 
556     name_a = object_class_get_name(class_a);
557     name_b = object_class_get_name(class_b);
558     return strcmp(name_a, name_b);
559 }
560 
561 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
562 {
563     const char *typename = object_class_get_name(OBJECT_CLASS(data));
564     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
565 
566     qemu_printf("%.*s\n", len, typename);
567 }
568 
569 void riscv_cpu_list(void)
570 {
571     GSList *list;
572 
573     list = object_class_get_list(TYPE_RISCV_CPU, false);
574     list = g_slist_sort(list, riscv_cpu_list_compare);
575     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
576     g_slist_free(list);
577 }
578 
579 #define DEFINE_CPU(type_name, initfn)      \
580     {                                      \
581         .name = type_name,                 \
582         .parent = TYPE_RISCV_CPU,          \
583         .instance_init = initfn            \
584     }
585 
586 static const TypeInfo riscv_cpu_type_infos[] = {
587     {
588         .name = TYPE_RISCV_CPU,
589         .parent = TYPE_CPU,
590         .instance_size = sizeof(RISCVCPU),
591         .instance_init = riscv_cpu_init,
592         .abstract = true,
593         .class_size = sizeof(RISCVCPUClass),
594         .class_init = riscv_cpu_class_init,
595     },
596     DEFINE_CPU(TYPE_RISCV_CPU_ANY,              riscv_any_cpu_init),
597 #if defined(TARGET_RISCV32)
598     DEFINE_CPU(TYPE_RISCV_CPU_BASE32,           riscv_base_cpu_init),
599     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32imcu_nommu_cpu_init),
600     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32imacu_nommu_cpu_init),
601     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32imafcu_nommu_cpu_init),
602     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32gcsu_priv1_10_0_cpu_init),
603 #elif defined(TARGET_RISCV64)
604     DEFINE_CPU(TYPE_RISCV_CPU_BASE64,           riscv_base_cpu_init),
605     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64imacu_nommu_cpu_init),
606     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64gcsu_priv1_10_0_cpu_init),
607 #endif
608 };
609 
610 DEFINE_TYPES(riscv_cpu_type_infos)
611