1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "pmu.h" 26 #include "internals.h" 27 #include "time_helper.h" 28 #include "exec/exec-all.h" 29 #include "qapi/error.h" 30 #include "qemu/error-report.h" 31 #include "hw/qdev-properties.h" 32 #include "migration/vmstate.h" 33 #include "fpu/softfloat-helpers.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_riscv.h" 36 37 /* RISC-V CPU definitions */ 38 39 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 40 (QEMU_VERSION_MINOR << 8) | \ 41 (QEMU_VERSION_MICRO)) 42 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 43 44 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 45 46 struct isa_ext_data { 47 const char *name; 48 bool multi_letter; 49 int min_version; 50 int ext_enable_offset; 51 }; 52 53 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ 54 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 55 56 /** 57 * Here are the ordering rules of extension naming defined by RISC-V 58 * specification : 59 * 1. All extensions should be separated from other multi-letter extensions 60 * by an underscore. 61 * 2. The first letter following the 'Z' conventionally indicates the most 62 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 63 * If multiple 'Z' extensions are named, they should be ordered first 64 * by category, then alphabetically within a category. 65 * 3. Standard supervisor-level extensions (starts with 'S') should be 66 * listed after standard unprivileged extensions. If multiple 67 * supervisor-level extensions are listed, they should be ordered 68 * alphabetically. 69 * 4. Non-standard extensions (starts with 'X') must be listed after all 70 * standard extensions. They must be separated from other multi-letter 71 * extensions by an underscore. 72 */ 73 static const struct isa_ext_data isa_edata_arr[] = { 74 ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), 75 ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), 76 ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), 77 ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), 78 ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), 79 ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), 80 ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), 81 ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), 82 ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), 83 ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), 84 ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), 85 ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), 86 ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), 87 ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), 88 ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), 89 ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), 90 ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), 91 ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), 92 ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), 93 ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), 94 ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), 95 ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), 96 ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), 97 ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), 98 ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), 99 ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), 100 ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), 101 ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), 102 ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), 103 ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), 104 ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), 105 ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), 106 ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), 107 ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), 108 ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), 109 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), 110 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), 111 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), 112 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 113 }; 114 115 static bool isa_ext_is_enabled(RISCVCPU *cpu, 116 const struct isa_ext_data *edata) 117 { 118 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 119 120 return *ext_enabled; 121 } 122 123 static void isa_ext_update_enabled(RISCVCPU *cpu, 124 const struct isa_ext_data *edata, bool en) 125 { 126 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 127 128 *ext_enabled = en; 129 } 130 131 const char * const riscv_int_regnames[] = { 132 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 133 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 134 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 135 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 136 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 137 }; 138 139 const char * const riscv_int_regnamesh[] = { 140 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 141 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 142 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 143 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 144 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 145 "x30h/t5h", "x31h/t6h" 146 }; 147 148 const char * const riscv_fpr_regnames[] = { 149 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 150 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 151 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 152 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 153 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 154 "f30/ft10", "f31/ft11" 155 }; 156 157 static const char * const riscv_excp_names[] = { 158 "misaligned_fetch", 159 "fault_fetch", 160 "illegal_instruction", 161 "breakpoint", 162 "misaligned_load", 163 "fault_load", 164 "misaligned_store", 165 "fault_store", 166 "user_ecall", 167 "supervisor_ecall", 168 "hypervisor_ecall", 169 "machine_ecall", 170 "exec_page_fault", 171 "load_page_fault", 172 "reserved", 173 "store_page_fault", 174 "reserved", 175 "reserved", 176 "reserved", 177 "reserved", 178 "guest_exec_page_fault", 179 "guest_load_page_fault", 180 "reserved", 181 "guest_store_page_fault", 182 }; 183 184 static const char * const riscv_intr_names[] = { 185 "u_software", 186 "s_software", 187 "vs_software", 188 "m_software", 189 "u_timer", 190 "s_timer", 191 "vs_timer", 192 "m_timer", 193 "u_external", 194 "s_external", 195 "vs_external", 196 "m_external", 197 "reserved", 198 "reserved", 199 "reserved", 200 "reserved" 201 }; 202 203 static void register_cpu_props(DeviceState *dev); 204 205 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 206 { 207 if (async) { 208 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 209 riscv_intr_names[cause] : "(unknown)"; 210 } else { 211 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 212 riscv_excp_names[cause] : "(unknown)"; 213 } 214 } 215 216 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 217 { 218 env->misa_mxl_max = env->misa_mxl = mxl; 219 env->misa_ext_mask = env->misa_ext = ext; 220 } 221 222 static void set_priv_version(CPURISCVState *env, int priv_ver) 223 { 224 env->priv_ver = priv_ver; 225 } 226 227 static void set_vext_version(CPURISCVState *env, int vext_ver) 228 { 229 env->vext_ver = vext_ver; 230 } 231 232 static void riscv_any_cpu_init(Object *obj) 233 { 234 CPURISCVState *env = &RISCV_CPU(obj)->env; 235 #if defined(TARGET_RISCV32) 236 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 237 #elif defined(TARGET_RISCV64) 238 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 239 #endif 240 set_priv_version(env, PRIV_VERSION_1_12_0); 241 register_cpu_props(DEVICE(obj)); 242 } 243 244 #if defined(TARGET_RISCV64) 245 static void rv64_base_cpu_init(Object *obj) 246 { 247 CPURISCVState *env = &RISCV_CPU(obj)->env; 248 /* We set this in the realise function */ 249 set_misa(env, MXL_RV64, 0); 250 register_cpu_props(DEVICE(obj)); 251 /* Set latest version of privileged specification */ 252 set_priv_version(env, PRIV_VERSION_1_12_0); 253 } 254 255 static void rv64_sifive_u_cpu_init(Object *obj) 256 { 257 CPURISCVState *env = &RISCV_CPU(obj)->env; 258 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 259 set_priv_version(env, PRIV_VERSION_1_10_0); 260 } 261 262 static void rv64_sifive_e_cpu_init(Object *obj) 263 { 264 CPURISCVState *env = &RISCV_CPU(obj)->env; 265 RISCVCPU *cpu = RISCV_CPU(obj); 266 267 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 268 set_priv_version(env, PRIV_VERSION_1_10_0); 269 cpu->cfg.mmu = false; 270 } 271 272 static void rv128_base_cpu_init(Object *obj) 273 { 274 if (qemu_tcg_mttcg_enabled()) { 275 /* Missing 128-bit aligned atomics */ 276 error_report("128-bit RISC-V currently does not work with Multi " 277 "Threaded TCG. Please use: -accel tcg,thread=single"); 278 exit(EXIT_FAILURE); 279 } 280 CPURISCVState *env = &RISCV_CPU(obj)->env; 281 /* We set this in the realise function */ 282 set_misa(env, MXL_RV128, 0); 283 register_cpu_props(DEVICE(obj)); 284 /* Set latest version of privileged specification */ 285 set_priv_version(env, PRIV_VERSION_1_12_0); 286 } 287 #else 288 static void rv32_base_cpu_init(Object *obj) 289 { 290 CPURISCVState *env = &RISCV_CPU(obj)->env; 291 /* We set this in the realise function */ 292 set_misa(env, MXL_RV32, 0); 293 register_cpu_props(DEVICE(obj)); 294 /* Set latest version of privileged specification */ 295 set_priv_version(env, PRIV_VERSION_1_12_0); 296 } 297 298 static void rv32_sifive_u_cpu_init(Object *obj) 299 { 300 CPURISCVState *env = &RISCV_CPU(obj)->env; 301 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 302 set_priv_version(env, PRIV_VERSION_1_10_0); 303 } 304 305 static void rv32_sifive_e_cpu_init(Object *obj) 306 { 307 CPURISCVState *env = &RISCV_CPU(obj)->env; 308 RISCVCPU *cpu = RISCV_CPU(obj); 309 310 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 311 set_priv_version(env, PRIV_VERSION_1_10_0); 312 cpu->cfg.mmu = false; 313 } 314 315 static void rv32_ibex_cpu_init(Object *obj) 316 { 317 CPURISCVState *env = &RISCV_CPU(obj)->env; 318 RISCVCPU *cpu = RISCV_CPU(obj); 319 320 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 321 set_priv_version(env, PRIV_VERSION_1_11_0); 322 cpu->cfg.mmu = false; 323 cpu->cfg.epmp = true; 324 } 325 326 static void rv32_imafcu_nommu_cpu_init(Object *obj) 327 { 328 CPURISCVState *env = &RISCV_CPU(obj)->env; 329 RISCVCPU *cpu = RISCV_CPU(obj); 330 331 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 332 set_priv_version(env, PRIV_VERSION_1_10_0); 333 cpu->cfg.mmu = false; 334 } 335 #endif 336 337 #if defined(CONFIG_KVM) 338 static void riscv_host_cpu_init(Object *obj) 339 { 340 CPURISCVState *env = &RISCV_CPU(obj)->env; 341 #if defined(TARGET_RISCV32) 342 set_misa(env, MXL_RV32, 0); 343 #elif defined(TARGET_RISCV64) 344 set_misa(env, MXL_RV64, 0); 345 #endif 346 register_cpu_props(DEVICE(obj)); 347 } 348 #endif 349 350 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 351 { 352 ObjectClass *oc; 353 char *typename; 354 char **cpuname; 355 356 cpuname = g_strsplit(cpu_model, ",", 1); 357 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 358 oc = object_class_by_name(typename); 359 g_strfreev(cpuname); 360 g_free(typename); 361 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 362 object_class_is_abstract(oc)) { 363 return NULL; 364 } 365 return oc; 366 } 367 368 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 369 { 370 RISCVCPU *cpu = RISCV_CPU(cs); 371 CPURISCVState *env = &cpu->env; 372 int i; 373 374 #if !defined(CONFIG_USER_ONLY) 375 if (riscv_has_ext(env, RVH)) { 376 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 377 } 378 #endif 379 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 380 #ifndef CONFIG_USER_ONLY 381 { 382 static const int dump_csrs[] = { 383 CSR_MHARTID, 384 CSR_MSTATUS, 385 CSR_MSTATUSH, 386 /* 387 * CSR_SSTATUS is intentionally omitted here as its value 388 * can be figured out by looking at CSR_MSTATUS 389 */ 390 CSR_HSTATUS, 391 CSR_VSSTATUS, 392 CSR_MIP, 393 CSR_MIE, 394 CSR_MIDELEG, 395 CSR_HIDELEG, 396 CSR_MEDELEG, 397 CSR_HEDELEG, 398 CSR_MTVEC, 399 CSR_STVEC, 400 CSR_VSTVEC, 401 CSR_MEPC, 402 CSR_SEPC, 403 CSR_VSEPC, 404 CSR_MCAUSE, 405 CSR_SCAUSE, 406 CSR_VSCAUSE, 407 CSR_MTVAL, 408 CSR_STVAL, 409 CSR_HTVAL, 410 CSR_MTVAL2, 411 CSR_MSCRATCH, 412 CSR_SSCRATCH, 413 CSR_SATP, 414 CSR_MMTE, 415 CSR_UPMBASE, 416 CSR_UPMMASK, 417 CSR_SPMBASE, 418 CSR_SPMMASK, 419 CSR_MPMBASE, 420 CSR_MPMMASK, 421 }; 422 423 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 424 int csrno = dump_csrs[i]; 425 target_ulong val = 0; 426 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 427 428 /* 429 * Rely on the smode, hmode, etc, predicates within csr.c 430 * to do the filtering of the registers that are present. 431 */ 432 if (res == RISCV_EXCP_NONE) { 433 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 434 csr_ops[csrno].name, val); 435 } 436 } 437 } 438 #endif 439 440 for (i = 0; i < 32; i++) { 441 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 442 riscv_int_regnames[i], env->gpr[i]); 443 if ((i & 3) == 3) { 444 qemu_fprintf(f, "\n"); 445 } 446 } 447 if (flags & CPU_DUMP_FPU) { 448 for (i = 0; i < 32; i++) { 449 qemu_fprintf(f, " %-8s %016" PRIx64, 450 riscv_fpr_regnames[i], env->fpr[i]); 451 if ((i & 3) == 3) { 452 qemu_fprintf(f, "\n"); 453 } 454 } 455 } 456 } 457 458 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 459 { 460 RISCVCPU *cpu = RISCV_CPU(cs); 461 CPURISCVState *env = &cpu->env; 462 463 if (env->xl == MXL_RV32) { 464 env->pc = (int32_t)value; 465 } else { 466 env->pc = value; 467 } 468 } 469 470 static vaddr riscv_cpu_get_pc(CPUState *cs) 471 { 472 RISCVCPU *cpu = RISCV_CPU(cs); 473 CPURISCVState *env = &cpu->env; 474 475 /* Match cpu_get_tb_cpu_state. */ 476 if (env->xl == MXL_RV32) { 477 return env->pc & UINT32_MAX; 478 } 479 return env->pc; 480 } 481 482 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 483 const TranslationBlock *tb) 484 { 485 RISCVCPU *cpu = RISCV_CPU(cs); 486 CPURISCVState *env = &cpu->env; 487 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 488 489 if (xl == MXL_RV32) { 490 env->pc = (int32_t)tb_pc(tb); 491 } else { 492 env->pc = tb_pc(tb); 493 } 494 } 495 496 static bool riscv_cpu_has_work(CPUState *cs) 497 { 498 #ifndef CONFIG_USER_ONLY 499 RISCVCPU *cpu = RISCV_CPU(cs); 500 CPURISCVState *env = &cpu->env; 501 /* 502 * Definition of the WFI instruction requires it to ignore the privilege 503 * mode and delegation registers, but respect individual enables 504 */ 505 return riscv_cpu_all_pending(env) != 0; 506 #else 507 return true; 508 #endif 509 } 510 511 static void riscv_restore_state_to_opc(CPUState *cs, 512 const TranslationBlock *tb, 513 const uint64_t *data) 514 { 515 RISCVCPU *cpu = RISCV_CPU(cs); 516 CPURISCVState *env = &cpu->env; 517 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 518 519 if (xl == MXL_RV32) { 520 env->pc = (int32_t)data[0]; 521 } else { 522 env->pc = data[0]; 523 } 524 env->bins = data[1]; 525 } 526 527 static void riscv_cpu_reset_hold(Object *obj) 528 { 529 #ifndef CONFIG_USER_ONLY 530 uint8_t iprio; 531 int i, irq, rdzero; 532 #endif 533 CPUState *cs = CPU(obj); 534 RISCVCPU *cpu = RISCV_CPU(cs); 535 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 536 CPURISCVState *env = &cpu->env; 537 538 if (mcc->parent_phases.hold) { 539 mcc->parent_phases.hold(obj); 540 } 541 #ifndef CONFIG_USER_ONLY 542 env->misa_mxl = env->misa_mxl_max; 543 env->priv = PRV_M; 544 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 545 if (env->misa_mxl > MXL_RV32) { 546 /* 547 * The reset status of SXL/UXL is undefined, but mstatus is WARL 548 * and we must ensure that the value after init is valid for read. 549 */ 550 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 551 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 552 if (riscv_has_ext(env, RVH)) { 553 env->vsstatus = set_field(env->vsstatus, 554 MSTATUS64_SXL, env->misa_mxl); 555 env->vsstatus = set_field(env->vsstatus, 556 MSTATUS64_UXL, env->misa_mxl); 557 env->mstatus_hs = set_field(env->mstatus_hs, 558 MSTATUS64_SXL, env->misa_mxl); 559 env->mstatus_hs = set_field(env->mstatus_hs, 560 MSTATUS64_UXL, env->misa_mxl); 561 } 562 } 563 env->mcause = 0; 564 env->miclaim = MIP_SGEIP; 565 env->pc = env->resetvec; 566 env->bins = 0; 567 env->two_stage_lookup = false; 568 569 /* Initialized default priorities of local interrupts. */ 570 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 571 iprio = riscv_cpu_default_priority(i); 572 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 573 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 574 env->hviprio[i] = 0; 575 } 576 i = 0; 577 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 578 if (!rdzero) { 579 env->hviprio[irq] = env->miprio[irq]; 580 } 581 i++; 582 } 583 /* mmte is supposed to have pm.current hardwired to 1 */ 584 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 585 #endif 586 env->xl = riscv_cpu_mxl(env); 587 riscv_cpu_update_mask(env); 588 cs->exception_index = RISCV_EXCP_NONE; 589 env->load_res = -1; 590 set_default_nan_mode(1, &env->fp_status); 591 592 #ifndef CONFIG_USER_ONLY 593 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 594 riscv_trigger_init(env); 595 } 596 597 if (kvm_enabled()) { 598 kvm_riscv_reset_vcpu(cpu); 599 } 600 #endif 601 } 602 603 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 604 { 605 RISCVCPU *cpu = RISCV_CPU(s); 606 607 switch (riscv_cpu_mxl(&cpu->env)) { 608 case MXL_RV32: 609 info->print_insn = print_insn_riscv32; 610 break; 611 case MXL_RV64: 612 info->print_insn = print_insn_riscv64; 613 break; 614 case MXL_RV128: 615 info->print_insn = print_insn_riscv128; 616 break; 617 default: 618 g_assert_not_reached(); 619 } 620 } 621 622 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 623 { 624 CPUState *cs = CPU(dev); 625 RISCVCPU *cpu = RISCV_CPU(dev); 626 CPURISCVState *env = &cpu->env; 627 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 628 CPUClass *cc = CPU_CLASS(mcc); 629 int i, priv_version = -1; 630 Error *local_err = NULL; 631 632 cpu_exec_realizefn(cs, &local_err); 633 if (local_err != NULL) { 634 error_propagate(errp, local_err); 635 return; 636 } 637 638 if (cpu->cfg.priv_spec) { 639 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 640 priv_version = PRIV_VERSION_1_12_0; 641 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 642 priv_version = PRIV_VERSION_1_11_0; 643 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 644 priv_version = PRIV_VERSION_1_10_0; 645 } else { 646 error_setg(errp, 647 "Unsupported privilege spec version '%s'", 648 cpu->cfg.priv_spec); 649 return; 650 } 651 } 652 653 if (priv_version >= PRIV_VERSION_1_10_0) { 654 set_priv_version(env, priv_version); 655 } 656 657 /* Force disable extensions if priv spec version does not match */ 658 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 659 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 660 (env->priv_ver < isa_edata_arr[i].min_version)) { 661 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 662 #ifndef CONFIG_USER_ONLY 663 warn_report("disabling %s extension for hart 0x%lx because " 664 "privilege spec version does not match", 665 isa_edata_arr[i].name, (unsigned long)env->mhartid); 666 #else 667 warn_report("disabling %s extension because " 668 "privilege spec version does not match", 669 isa_edata_arr[i].name); 670 #endif 671 } 672 } 673 674 if (cpu->cfg.mmu) { 675 riscv_set_feature(env, RISCV_FEATURE_MMU); 676 } 677 678 if (cpu->cfg.pmp) { 679 riscv_set_feature(env, RISCV_FEATURE_PMP); 680 681 /* 682 * Enhanced PMP should only be available 683 * on harts with PMP support 684 */ 685 if (cpu->cfg.epmp) { 686 riscv_set_feature(env, RISCV_FEATURE_EPMP); 687 } 688 } 689 690 if (cpu->cfg.debug) { 691 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 692 } 693 694 695 #ifndef CONFIG_USER_ONLY 696 if (cpu->cfg.ext_sstc) { 697 riscv_timer_init(cpu); 698 } 699 #endif /* CONFIG_USER_ONLY */ 700 701 /* Validate that MISA_MXL is set properly. */ 702 switch (env->misa_mxl_max) { 703 #ifdef TARGET_RISCV64 704 case MXL_RV64: 705 case MXL_RV128: 706 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 707 break; 708 #endif 709 case MXL_RV32: 710 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 711 break; 712 default: 713 g_assert_not_reached(); 714 } 715 assert(env->misa_mxl_max == env->misa_mxl); 716 717 /* If only MISA_EXT is unset for misa, then set it from properties */ 718 if (env->misa_ext == 0) { 719 uint32_t ext = 0; 720 721 /* Do some ISA extension error checking */ 722 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 723 cpu->cfg.ext_a && cpu->cfg.ext_f && 724 cpu->cfg.ext_d && 725 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 726 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 727 cpu->cfg.ext_i = true; 728 cpu->cfg.ext_m = true; 729 cpu->cfg.ext_a = true; 730 cpu->cfg.ext_f = true; 731 cpu->cfg.ext_d = true; 732 cpu->cfg.ext_icsr = true; 733 cpu->cfg.ext_ifencei = true; 734 } 735 736 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 737 error_setg(errp, 738 "I and E extensions are incompatible"); 739 return; 740 } 741 742 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 743 error_setg(errp, 744 "Either I or E extension must be set"); 745 return; 746 } 747 748 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 749 error_setg(errp, 750 "Setting S extension without U extension is illegal"); 751 return; 752 } 753 754 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { 755 error_setg(errp, 756 "H depends on an I base integer ISA with 32 x registers"); 757 return; 758 } 759 760 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 761 error_setg(errp, "H extension implicitly requires S-mode"); 762 return; 763 } 764 765 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 766 error_setg(errp, "F extension requires Zicsr"); 767 return; 768 } 769 770 if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { 771 error_setg(errp, "Zawrs extension requires A extension"); 772 return; 773 } 774 775 if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { 776 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 777 return; 778 } 779 780 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 781 error_setg(errp, "D extension requires F extension"); 782 return; 783 } 784 785 if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { 786 error_setg(errp, "V extension requires D extension"); 787 return; 788 } 789 790 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 791 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 792 return; 793 } 794 795 /* Set the ISA extensions, checks should have happened above */ 796 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || 797 cpu->cfg.ext_zhinxmin) { 798 cpu->cfg.ext_zfinx = true; 799 } 800 801 if (cpu->cfg.ext_zfinx) { 802 if (!cpu->cfg.ext_icsr) { 803 error_setg(errp, "Zfinx extension requires Zicsr"); 804 return; 805 } 806 if (cpu->cfg.ext_f) { 807 error_setg(errp, 808 "Zfinx cannot be supported together with F extension"); 809 return; 810 } 811 } 812 813 if (cpu->cfg.ext_zk) { 814 cpu->cfg.ext_zkn = true; 815 cpu->cfg.ext_zkr = true; 816 cpu->cfg.ext_zkt = true; 817 } 818 819 if (cpu->cfg.ext_zkn) { 820 cpu->cfg.ext_zbkb = true; 821 cpu->cfg.ext_zbkc = true; 822 cpu->cfg.ext_zbkx = true; 823 cpu->cfg.ext_zkne = true; 824 cpu->cfg.ext_zknd = true; 825 cpu->cfg.ext_zknh = true; 826 } 827 828 if (cpu->cfg.ext_zks) { 829 cpu->cfg.ext_zbkb = true; 830 cpu->cfg.ext_zbkc = true; 831 cpu->cfg.ext_zbkx = true; 832 cpu->cfg.ext_zksed = true; 833 cpu->cfg.ext_zksh = true; 834 } 835 836 if (cpu->cfg.ext_i) { 837 ext |= RVI; 838 } 839 if (cpu->cfg.ext_e) { 840 ext |= RVE; 841 } 842 if (cpu->cfg.ext_m) { 843 ext |= RVM; 844 } 845 if (cpu->cfg.ext_a) { 846 ext |= RVA; 847 } 848 if (cpu->cfg.ext_f) { 849 ext |= RVF; 850 } 851 if (cpu->cfg.ext_d) { 852 ext |= RVD; 853 } 854 if (cpu->cfg.ext_c) { 855 ext |= RVC; 856 } 857 if (cpu->cfg.ext_s) { 858 ext |= RVS; 859 } 860 if (cpu->cfg.ext_u) { 861 ext |= RVU; 862 } 863 if (cpu->cfg.ext_h) { 864 ext |= RVH; 865 } 866 if (cpu->cfg.ext_v) { 867 int vext_version = VEXT_VERSION_1_00_0; 868 ext |= RVV; 869 if (!is_power_of_2(cpu->cfg.vlen)) { 870 error_setg(errp, 871 "Vector extension VLEN must be power of 2"); 872 return; 873 } 874 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 875 error_setg(errp, 876 "Vector extension implementation only supports VLEN " 877 "in the range [128, %d]", RV_VLEN_MAX); 878 return; 879 } 880 if (!is_power_of_2(cpu->cfg.elen)) { 881 error_setg(errp, 882 "Vector extension ELEN must be power of 2"); 883 return; 884 } 885 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 886 error_setg(errp, 887 "Vector extension implementation only supports ELEN " 888 "in the range [8, 64]"); 889 return; 890 } 891 if (cpu->cfg.vext_spec) { 892 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 893 vext_version = VEXT_VERSION_1_00_0; 894 } else { 895 error_setg(errp, 896 "Unsupported vector spec version '%s'", 897 cpu->cfg.vext_spec); 898 return; 899 } 900 } else { 901 qemu_log("vector version is not specified, " 902 "use the default value v1.0\n"); 903 } 904 set_vext_version(env, vext_version); 905 } 906 if (cpu->cfg.ext_j) { 907 ext |= RVJ; 908 } 909 910 set_misa(env, env->misa_mxl, ext); 911 } 912 913 #ifndef CONFIG_USER_ONLY 914 if (cpu->cfg.pmu_num) { 915 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 916 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 917 riscv_pmu_timer_cb, cpu); 918 } 919 } 920 #endif 921 922 riscv_cpu_register_gdb_regs_for_features(cs); 923 924 qemu_init_vcpu(cs); 925 cpu_reset(cs); 926 927 mcc->parent_realize(dev, errp); 928 } 929 930 #ifndef CONFIG_USER_ONLY 931 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 932 { 933 RISCVCPU *cpu = RISCV_CPU(opaque); 934 CPURISCVState *env = &cpu->env; 935 936 if (irq < IRQ_LOCAL_MAX) { 937 switch (irq) { 938 case IRQ_U_SOFT: 939 case IRQ_S_SOFT: 940 case IRQ_VS_SOFT: 941 case IRQ_M_SOFT: 942 case IRQ_U_TIMER: 943 case IRQ_S_TIMER: 944 case IRQ_VS_TIMER: 945 case IRQ_M_TIMER: 946 case IRQ_U_EXT: 947 case IRQ_VS_EXT: 948 case IRQ_M_EXT: 949 if (kvm_enabled()) { 950 kvm_riscv_set_irq(cpu, irq, level); 951 } else { 952 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 953 } 954 break; 955 case IRQ_S_EXT: 956 if (kvm_enabled()) { 957 kvm_riscv_set_irq(cpu, irq, level); 958 } else { 959 env->external_seip = level; 960 riscv_cpu_update_mip(cpu, 1 << irq, 961 BOOL_TO_MASK(level | env->software_seip)); 962 } 963 break; 964 default: 965 g_assert_not_reached(); 966 } 967 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 968 /* Require H-extension for handling guest local interrupts */ 969 if (!riscv_has_ext(env, RVH)) { 970 g_assert_not_reached(); 971 } 972 973 /* Compute bit position in HGEIP CSR */ 974 irq = irq - IRQ_LOCAL_MAX + 1; 975 if (env->geilen < irq) { 976 g_assert_not_reached(); 977 } 978 979 /* Update HGEIP CSR */ 980 env->hgeip &= ~((target_ulong)1 << irq); 981 if (level) { 982 env->hgeip |= (target_ulong)1 << irq; 983 } 984 985 /* Update mip.SGEIP bit */ 986 riscv_cpu_update_mip(cpu, MIP_SGEIP, 987 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 988 } else { 989 g_assert_not_reached(); 990 } 991 } 992 #endif /* CONFIG_USER_ONLY */ 993 994 static void riscv_cpu_init(Object *obj) 995 { 996 RISCVCPU *cpu = RISCV_CPU(obj); 997 998 cpu->cfg.ext_ifencei = true; 999 cpu->cfg.ext_icsr = true; 1000 cpu->cfg.mmu = true; 1001 cpu->cfg.pmp = true; 1002 1003 cpu_set_cpustate_pointers(cpu); 1004 1005 #ifndef CONFIG_USER_ONLY 1006 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1007 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1008 #endif /* CONFIG_USER_ONLY */ 1009 } 1010 1011 static Property riscv_cpu_extensions[] = { 1012 /* Defaults for standard extensions */ 1013 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 1014 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 1015 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1016 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 1017 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 1018 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 1019 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 1020 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 1021 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 1022 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1023 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1024 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1025 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1026 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1027 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1028 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1029 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1030 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1031 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1032 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1033 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1034 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1035 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1036 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1037 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1038 1039 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1040 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1041 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1042 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1043 1044 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1045 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1046 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1047 1048 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1049 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1050 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1051 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1052 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1053 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1054 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1055 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1056 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1057 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1058 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1059 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1060 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1061 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1062 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1063 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1064 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1065 1066 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1067 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1068 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1069 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1070 1071 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1072 1073 /* Vendor-specific custom extensions */ 1074 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1075 1076 /* These are experimental so mark with 'x-' */ 1077 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1078 /* ePMP 0.9.3 */ 1079 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1080 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1081 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1082 1083 DEFINE_PROP_END_OF_LIST(), 1084 }; 1085 1086 static void register_cpu_props(DeviceState *dev) 1087 { 1088 Property *prop; 1089 1090 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1091 qdev_property_add_static(dev, prop); 1092 } 1093 } 1094 1095 static Property riscv_cpu_properties[] = { 1096 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1097 1098 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1099 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1100 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1101 1102 #ifndef CONFIG_USER_ONLY 1103 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1104 #endif 1105 1106 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1107 1108 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1109 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1110 DEFINE_PROP_END_OF_LIST(), 1111 }; 1112 1113 static gchar *riscv_gdb_arch_name(CPUState *cs) 1114 { 1115 RISCVCPU *cpu = RISCV_CPU(cs); 1116 CPURISCVState *env = &cpu->env; 1117 1118 switch (riscv_cpu_mxl(env)) { 1119 case MXL_RV32: 1120 return g_strdup("riscv:rv32"); 1121 case MXL_RV64: 1122 case MXL_RV128: 1123 return g_strdup("riscv:rv64"); 1124 default: 1125 g_assert_not_reached(); 1126 } 1127 } 1128 1129 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1130 { 1131 RISCVCPU *cpu = RISCV_CPU(cs); 1132 1133 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1134 return cpu->dyn_csr_xml; 1135 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1136 return cpu->dyn_vreg_xml; 1137 } 1138 1139 return NULL; 1140 } 1141 1142 #ifndef CONFIG_USER_ONLY 1143 #include "hw/core/sysemu-cpu-ops.h" 1144 1145 static const struct SysemuCPUOps riscv_sysemu_ops = { 1146 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1147 .write_elf64_note = riscv_cpu_write_elf64_note, 1148 .write_elf32_note = riscv_cpu_write_elf32_note, 1149 .legacy_vmsd = &vmstate_riscv_cpu, 1150 }; 1151 #endif 1152 1153 #include "hw/core/tcg-cpu-ops.h" 1154 1155 static const struct TCGCPUOps riscv_tcg_ops = { 1156 .initialize = riscv_translate_init, 1157 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1158 .restore_state_to_opc = riscv_restore_state_to_opc, 1159 1160 #ifndef CONFIG_USER_ONLY 1161 .tlb_fill = riscv_cpu_tlb_fill, 1162 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1163 .do_interrupt = riscv_cpu_do_interrupt, 1164 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1165 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1166 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1167 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1168 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1169 #endif /* !CONFIG_USER_ONLY */ 1170 }; 1171 1172 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1173 { 1174 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1175 CPUClass *cc = CPU_CLASS(c); 1176 DeviceClass *dc = DEVICE_CLASS(c); 1177 ResettableClass *rc = RESETTABLE_CLASS(c); 1178 1179 device_class_set_parent_realize(dc, riscv_cpu_realize, 1180 &mcc->parent_realize); 1181 1182 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1183 &mcc->parent_phases); 1184 1185 cc->class_by_name = riscv_cpu_class_by_name; 1186 cc->has_work = riscv_cpu_has_work; 1187 cc->dump_state = riscv_cpu_dump_state; 1188 cc->set_pc = riscv_cpu_set_pc; 1189 cc->get_pc = riscv_cpu_get_pc; 1190 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1191 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1192 cc->gdb_num_core_regs = 33; 1193 cc->gdb_stop_before_watchpoint = true; 1194 cc->disas_set_info = riscv_cpu_disas_set_info; 1195 #ifndef CONFIG_USER_ONLY 1196 cc->sysemu_ops = &riscv_sysemu_ops; 1197 #endif 1198 cc->gdb_arch_name = riscv_gdb_arch_name; 1199 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1200 cc->tcg_ops = &riscv_tcg_ops; 1201 1202 device_class_set_props(dc, riscv_cpu_properties); 1203 } 1204 1205 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1206 { 1207 char *old = *isa_str; 1208 char *new = *isa_str; 1209 int i; 1210 1211 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1212 if (isa_edata_arr[i].multi_letter && 1213 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1214 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1215 g_free(old); 1216 old = new; 1217 } 1218 } 1219 1220 *isa_str = new; 1221 } 1222 1223 char *riscv_isa_string(RISCVCPU *cpu) 1224 { 1225 int i; 1226 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1227 char *isa_str = g_new(char, maxlen); 1228 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1229 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1230 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1231 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1232 } 1233 } 1234 *p = '\0'; 1235 if (!cpu->cfg.short_isa_string) { 1236 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1237 } 1238 return isa_str; 1239 } 1240 1241 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1242 { 1243 ObjectClass *class_a = (ObjectClass *)a; 1244 ObjectClass *class_b = (ObjectClass *)b; 1245 const char *name_a, *name_b; 1246 1247 name_a = object_class_get_name(class_a); 1248 name_b = object_class_get_name(class_b); 1249 return strcmp(name_a, name_b); 1250 } 1251 1252 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1253 { 1254 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1255 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1256 1257 qemu_printf("%.*s\n", len, typename); 1258 } 1259 1260 void riscv_cpu_list(void) 1261 { 1262 GSList *list; 1263 1264 list = object_class_get_list(TYPE_RISCV_CPU, false); 1265 list = g_slist_sort(list, riscv_cpu_list_compare); 1266 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1267 g_slist_free(list); 1268 } 1269 1270 #define DEFINE_CPU(type_name, initfn) \ 1271 { \ 1272 .name = type_name, \ 1273 .parent = TYPE_RISCV_CPU, \ 1274 .instance_init = initfn \ 1275 } 1276 1277 static const TypeInfo riscv_cpu_type_infos[] = { 1278 { 1279 .name = TYPE_RISCV_CPU, 1280 .parent = TYPE_CPU, 1281 .instance_size = sizeof(RISCVCPU), 1282 .instance_align = __alignof__(RISCVCPU), 1283 .instance_init = riscv_cpu_init, 1284 .abstract = true, 1285 .class_size = sizeof(RISCVCPUClass), 1286 .class_init = riscv_cpu_class_init, 1287 }, 1288 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1289 #if defined(CONFIG_KVM) 1290 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1291 #endif 1292 #if defined(TARGET_RISCV32) 1293 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1294 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1295 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1296 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1297 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1298 #elif defined(TARGET_RISCV64) 1299 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1300 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1301 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1302 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1303 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1304 #endif 1305 }; 1306 1307 DEFINE_TYPES(riscv_cpu_type_infos) 1308