1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "qemu/error-report.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "fpu/softfloat-helpers.h" 36 #include "sysemu/kvm.h" 37 #include "kvm_riscv.h" 38 #include "tcg/tcg.h" 39 40 /* RISC-V CPU definitions */ 41 42 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 43 (QEMU_VERSION_MINOR << 8) | \ 44 (QEMU_VERSION_MICRO)) 45 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 46 47 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 48 49 struct isa_ext_data { 50 const char *name; 51 int min_version; 52 int ext_enable_offset; 53 }; 54 55 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ 56 {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 57 58 /* 59 * Here are the ordering rules of extension naming defined by RISC-V 60 * specification : 61 * 1. All extensions should be separated from other multi-letter extensions 62 * by an underscore. 63 * 2. The first letter following the 'Z' conventionally indicates the most 64 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 65 * If multiple 'Z' extensions are named, they should be ordered first 66 * by category, then alphabetically within a category. 67 * 3. Standard supervisor-level extensions (starts with 'S') should be 68 * listed after standard unprivileged extensions. If multiple 69 * supervisor-level extensions are listed, they should be ordered 70 * alphabetically. 71 * 4. Non-standard extensions (starts with 'X') must be listed after all 72 * standard extensions. They must be separated from other multi-letter 73 * extensions by an underscore. 74 * 75 * Single letter extensions are checked in riscv_cpu_validate_misa_priv() 76 * instead. 77 */ 78 static const struct isa_ext_data isa_edata_arr[] = { 79 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), 80 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), 81 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), 82 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), 83 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), 84 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), 85 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), 86 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), 87 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), 88 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), 89 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), 90 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), 91 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), 92 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), 93 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), 94 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), 95 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), 96 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), 97 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), 98 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), 99 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), 100 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), 101 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), 102 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), 103 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), 104 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), 105 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), 106 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), 107 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), 108 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), 109 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), 110 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), 111 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), 112 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), 113 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), 114 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), 115 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), 116 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), 117 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), 118 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), 119 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), 120 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), 121 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), 122 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), 123 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), 124 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), 125 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), 126 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), 127 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), 128 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), 129 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), 130 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), 131 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), 132 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), 133 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 134 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 135 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), 136 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), 137 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 138 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), 139 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), 140 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 141 }; 142 143 static bool isa_ext_is_enabled(RISCVCPU *cpu, 144 const struct isa_ext_data *edata) 145 { 146 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 147 148 return *ext_enabled; 149 } 150 151 static void isa_ext_update_enabled(RISCVCPU *cpu, 152 const struct isa_ext_data *edata, bool en) 153 { 154 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 155 156 *ext_enabled = en; 157 } 158 159 const char * const riscv_int_regnames[] = { 160 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 161 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 162 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 163 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 164 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 165 }; 166 167 const char * const riscv_int_regnamesh[] = { 168 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 169 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 170 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 171 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 172 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 173 "x30h/t5h", "x31h/t6h" 174 }; 175 176 const char * const riscv_fpr_regnames[] = { 177 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 178 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 179 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 180 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 181 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 182 "f30/ft10", "f31/ft11" 183 }; 184 185 static const char * const riscv_excp_names[] = { 186 "misaligned_fetch", 187 "fault_fetch", 188 "illegal_instruction", 189 "breakpoint", 190 "misaligned_load", 191 "fault_load", 192 "misaligned_store", 193 "fault_store", 194 "user_ecall", 195 "supervisor_ecall", 196 "hypervisor_ecall", 197 "machine_ecall", 198 "exec_page_fault", 199 "load_page_fault", 200 "reserved", 201 "store_page_fault", 202 "reserved", 203 "reserved", 204 "reserved", 205 "reserved", 206 "guest_exec_page_fault", 207 "guest_load_page_fault", 208 "reserved", 209 "guest_store_page_fault", 210 }; 211 212 static const char * const riscv_intr_names[] = { 213 "u_software", 214 "s_software", 215 "vs_software", 216 "m_software", 217 "u_timer", 218 "s_timer", 219 "vs_timer", 220 "m_timer", 221 "u_external", 222 "s_external", 223 "vs_external", 224 "m_external", 225 "reserved", 226 "reserved", 227 "reserved", 228 "reserved" 229 }; 230 231 static void register_cpu_props(Object *obj); 232 233 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 234 { 235 if (async) { 236 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 237 riscv_intr_names[cause] : "(unknown)"; 238 } else { 239 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 240 riscv_excp_names[cause] : "(unknown)"; 241 } 242 } 243 244 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 245 { 246 env->misa_mxl_max = env->misa_mxl = mxl; 247 env->misa_ext_mask = env->misa_ext = ext; 248 } 249 250 static void set_priv_version(CPURISCVState *env, int priv_ver) 251 { 252 env->priv_ver = priv_ver; 253 } 254 255 static void set_vext_version(CPURISCVState *env, int vext_ver) 256 { 257 env->vext_ver = vext_ver; 258 } 259 260 #ifndef CONFIG_USER_ONLY 261 static uint8_t satp_mode_from_str(const char *satp_mode_str) 262 { 263 if (!strncmp(satp_mode_str, "mbare", 5)) { 264 return VM_1_10_MBARE; 265 } 266 267 if (!strncmp(satp_mode_str, "sv32", 4)) { 268 return VM_1_10_SV32; 269 } 270 271 if (!strncmp(satp_mode_str, "sv39", 4)) { 272 return VM_1_10_SV39; 273 } 274 275 if (!strncmp(satp_mode_str, "sv48", 4)) { 276 return VM_1_10_SV48; 277 } 278 279 if (!strncmp(satp_mode_str, "sv57", 4)) { 280 return VM_1_10_SV57; 281 } 282 283 if (!strncmp(satp_mode_str, "sv64", 4)) { 284 return VM_1_10_SV64; 285 } 286 287 g_assert_not_reached(); 288 } 289 290 uint8_t satp_mode_max_from_map(uint32_t map) 291 { 292 /* map here has at least one bit set, so no problem with clz */ 293 return 31 - __builtin_clz(map); 294 } 295 296 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) 297 { 298 if (is_32_bit) { 299 switch (satp_mode) { 300 case VM_1_10_SV32: 301 return "sv32"; 302 case VM_1_10_MBARE: 303 return "none"; 304 } 305 } else { 306 switch (satp_mode) { 307 case VM_1_10_SV64: 308 return "sv64"; 309 case VM_1_10_SV57: 310 return "sv57"; 311 case VM_1_10_SV48: 312 return "sv48"; 313 case VM_1_10_SV39: 314 return "sv39"; 315 case VM_1_10_MBARE: 316 return "none"; 317 } 318 } 319 320 g_assert_not_reached(); 321 } 322 323 static void set_satp_mode_max_supported(RISCVCPU *cpu, 324 uint8_t satp_mode) 325 { 326 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 327 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; 328 329 for (int i = 0; i <= satp_mode; ++i) { 330 if (valid_vm[i]) { 331 cpu->cfg.satp_mode.supported |= (1 << i); 332 } 333 } 334 } 335 336 /* Set the satp mode to the max supported */ 337 static void set_satp_mode_default_map(RISCVCPU *cpu) 338 { 339 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; 340 } 341 #endif 342 343 static void riscv_any_cpu_init(Object *obj) 344 { 345 CPURISCVState *env = &RISCV_CPU(obj)->env; 346 #if defined(TARGET_RISCV32) 347 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 348 #elif defined(TARGET_RISCV64) 349 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 350 #endif 351 352 #ifndef CONFIG_USER_ONLY 353 set_satp_mode_max_supported(RISCV_CPU(obj), 354 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? 355 VM_1_10_SV32 : VM_1_10_SV57); 356 #endif 357 358 set_priv_version(env, PRIV_VERSION_1_12_0); 359 register_cpu_props(obj); 360 } 361 362 #if defined(TARGET_RISCV64) 363 static void rv64_base_cpu_init(Object *obj) 364 { 365 CPURISCVState *env = &RISCV_CPU(obj)->env; 366 /* We set this in the realise function */ 367 set_misa(env, MXL_RV64, 0); 368 register_cpu_props(obj); 369 /* Set latest version of privileged specification */ 370 set_priv_version(env, PRIV_VERSION_1_12_0); 371 #ifndef CONFIG_USER_ONLY 372 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 373 #endif 374 } 375 376 static void rv64_sifive_u_cpu_init(Object *obj) 377 { 378 CPURISCVState *env = &RISCV_CPU(obj)->env; 379 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 380 register_cpu_props(obj); 381 set_priv_version(env, PRIV_VERSION_1_10_0); 382 #ifndef CONFIG_USER_ONLY 383 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); 384 #endif 385 } 386 387 static void rv64_sifive_e_cpu_init(Object *obj) 388 { 389 CPURISCVState *env = &RISCV_CPU(obj)->env; 390 RISCVCPU *cpu = RISCV_CPU(obj); 391 392 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 393 register_cpu_props(obj); 394 set_priv_version(env, PRIV_VERSION_1_10_0); 395 cpu->cfg.mmu = false; 396 #ifndef CONFIG_USER_ONLY 397 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 398 #endif 399 } 400 401 static void rv64_thead_c906_cpu_init(Object *obj) 402 { 403 CPURISCVState *env = &RISCV_CPU(obj)->env; 404 RISCVCPU *cpu = RISCV_CPU(obj); 405 406 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 407 set_priv_version(env, PRIV_VERSION_1_11_0); 408 409 cpu->cfg.ext_g = true; 410 cpu->cfg.ext_icsr = true; 411 cpu->cfg.ext_zfh = true; 412 cpu->cfg.mmu = true; 413 cpu->cfg.ext_xtheadba = true; 414 cpu->cfg.ext_xtheadbb = true; 415 cpu->cfg.ext_xtheadbs = true; 416 cpu->cfg.ext_xtheadcmo = true; 417 cpu->cfg.ext_xtheadcondmov = true; 418 cpu->cfg.ext_xtheadfmemidx = true; 419 cpu->cfg.ext_xtheadmac = true; 420 cpu->cfg.ext_xtheadmemidx = true; 421 cpu->cfg.ext_xtheadmempair = true; 422 cpu->cfg.ext_xtheadsync = true; 423 424 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 425 #ifndef CONFIG_USER_ONLY 426 set_satp_mode_max_supported(cpu, VM_1_10_SV39); 427 #endif 428 } 429 430 static void rv128_base_cpu_init(Object *obj) 431 { 432 if (qemu_tcg_mttcg_enabled()) { 433 /* Missing 128-bit aligned atomics */ 434 error_report("128-bit RISC-V currently does not work with Multi " 435 "Threaded TCG. Please use: -accel tcg,thread=single"); 436 exit(EXIT_FAILURE); 437 } 438 CPURISCVState *env = &RISCV_CPU(obj)->env; 439 /* We set this in the realise function */ 440 set_misa(env, MXL_RV128, 0); 441 register_cpu_props(obj); 442 /* Set latest version of privileged specification */ 443 set_priv_version(env, PRIV_VERSION_1_12_0); 444 #ifndef CONFIG_USER_ONLY 445 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 446 #endif 447 } 448 #else 449 static void rv32_base_cpu_init(Object *obj) 450 { 451 CPURISCVState *env = &RISCV_CPU(obj)->env; 452 /* We set this in the realise function */ 453 set_misa(env, MXL_RV32, 0); 454 register_cpu_props(obj); 455 /* Set latest version of privileged specification */ 456 set_priv_version(env, PRIV_VERSION_1_12_0); 457 #ifndef CONFIG_USER_ONLY 458 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 459 #endif 460 } 461 462 static void rv32_sifive_u_cpu_init(Object *obj) 463 { 464 CPURISCVState *env = &RISCV_CPU(obj)->env; 465 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 466 register_cpu_props(obj); 467 set_priv_version(env, PRIV_VERSION_1_10_0); 468 #ifndef CONFIG_USER_ONLY 469 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 470 #endif 471 } 472 473 static void rv32_sifive_e_cpu_init(Object *obj) 474 { 475 CPURISCVState *env = &RISCV_CPU(obj)->env; 476 RISCVCPU *cpu = RISCV_CPU(obj); 477 478 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 479 register_cpu_props(obj); 480 set_priv_version(env, PRIV_VERSION_1_10_0); 481 cpu->cfg.mmu = false; 482 #ifndef CONFIG_USER_ONLY 483 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 484 #endif 485 } 486 487 static void rv32_ibex_cpu_init(Object *obj) 488 { 489 CPURISCVState *env = &RISCV_CPU(obj)->env; 490 RISCVCPU *cpu = RISCV_CPU(obj); 491 492 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 493 register_cpu_props(obj); 494 set_priv_version(env, PRIV_VERSION_1_11_0); 495 cpu->cfg.mmu = false; 496 #ifndef CONFIG_USER_ONLY 497 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 498 #endif 499 cpu->cfg.epmp = true; 500 } 501 502 static void rv32_imafcu_nommu_cpu_init(Object *obj) 503 { 504 CPURISCVState *env = &RISCV_CPU(obj)->env; 505 RISCVCPU *cpu = RISCV_CPU(obj); 506 507 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 508 register_cpu_props(obj); 509 set_priv_version(env, PRIV_VERSION_1_10_0); 510 cpu->cfg.mmu = false; 511 #ifndef CONFIG_USER_ONLY 512 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 513 #endif 514 } 515 #endif 516 517 #if defined(CONFIG_KVM) 518 static void riscv_host_cpu_init(Object *obj) 519 { 520 CPURISCVState *env = &RISCV_CPU(obj)->env; 521 #if defined(TARGET_RISCV32) 522 set_misa(env, MXL_RV32, 0); 523 #elif defined(TARGET_RISCV64) 524 set_misa(env, MXL_RV64, 0); 525 #endif 526 register_cpu_props(obj); 527 } 528 #endif 529 530 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 531 { 532 ObjectClass *oc; 533 char *typename; 534 char **cpuname; 535 536 cpuname = g_strsplit(cpu_model, ",", 1); 537 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 538 oc = object_class_by_name(typename); 539 g_strfreev(cpuname); 540 g_free(typename); 541 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 542 object_class_is_abstract(oc)) { 543 return NULL; 544 } 545 return oc; 546 } 547 548 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 549 { 550 RISCVCPU *cpu = RISCV_CPU(cs); 551 CPURISCVState *env = &cpu->env; 552 int i; 553 554 #if !defined(CONFIG_USER_ONLY) 555 if (riscv_has_ext(env, RVH)) { 556 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); 557 } 558 #endif 559 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 560 #ifndef CONFIG_USER_ONLY 561 { 562 static const int dump_csrs[] = { 563 CSR_MHARTID, 564 CSR_MSTATUS, 565 CSR_MSTATUSH, 566 /* 567 * CSR_SSTATUS is intentionally omitted here as its value 568 * can be figured out by looking at CSR_MSTATUS 569 */ 570 CSR_HSTATUS, 571 CSR_VSSTATUS, 572 CSR_MIP, 573 CSR_MIE, 574 CSR_MIDELEG, 575 CSR_HIDELEG, 576 CSR_MEDELEG, 577 CSR_HEDELEG, 578 CSR_MTVEC, 579 CSR_STVEC, 580 CSR_VSTVEC, 581 CSR_MEPC, 582 CSR_SEPC, 583 CSR_VSEPC, 584 CSR_MCAUSE, 585 CSR_SCAUSE, 586 CSR_VSCAUSE, 587 CSR_MTVAL, 588 CSR_STVAL, 589 CSR_HTVAL, 590 CSR_MTVAL2, 591 CSR_MSCRATCH, 592 CSR_SSCRATCH, 593 CSR_SATP, 594 CSR_MMTE, 595 CSR_UPMBASE, 596 CSR_UPMMASK, 597 CSR_SPMBASE, 598 CSR_SPMMASK, 599 CSR_MPMBASE, 600 CSR_MPMMASK, 601 }; 602 603 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 604 int csrno = dump_csrs[i]; 605 target_ulong val = 0; 606 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 607 608 /* 609 * Rely on the smode, hmode, etc, predicates within csr.c 610 * to do the filtering of the registers that are present. 611 */ 612 if (res == RISCV_EXCP_NONE) { 613 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 614 csr_ops[csrno].name, val); 615 } 616 } 617 } 618 #endif 619 620 for (i = 0; i < 32; i++) { 621 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 622 riscv_int_regnames[i], env->gpr[i]); 623 if ((i & 3) == 3) { 624 qemu_fprintf(f, "\n"); 625 } 626 } 627 if (flags & CPU_DUMP_FPU) { 628 for (i = 0; i < 32; i++) { 629 qemu_fprintf(f, " %-8s %016" PRIx64, 630 riscv_fpr_regnames[i], env->fpr[i]); 631 if ((i & 3) == 3) { 632 qemu_fprintf(f, "\n"); 633 } 634 } 635 } 636 } 637 638 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 639 { 640 RISCVCPU *cpu = RISCV_CPU(cs); 641 CPURISCVState *env = &cpu->env; 642 643 if (env->xl == MXL_RV32) { 644 env->pc = (int32_t)value; 645 } else { 646 env->pc = value; 647 } 648 } 649 650 static vaddr riscv_cpu_get_pc(CPUState *cs) 651 { 652 RISCVCPU *cpu = RISCV_CPU(cs); 653 CPURISCVState *env = &cpu->env; 654 655 /* Match cpu_get_tb_cpu_state. */ 656 if (env->xl == MXL_RV32) { 657 return env->pc & UINT32_MAX; 658 } 659 return env->pc; 660 } 661 662 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 663 const TranslationBlock *tb) 664 { 665 RISCVCPU *cpu = RISCV_CPU(cs); 666 CPURISCVState *env = &cpu->env; 667 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 668 669 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 670 671 if (xl == MXL_RV32) { 672 env->pc = (int32_t) tb->pc; 673 } else { 674 env->pc = tb->pc; 675 } 676 } 677 678 static bool riscv_cpu_has_work(CPUState *cs) 679 { 680 #ifndef CONFIG_USER_ONLY 681 RISCVCPU *cpu = RISCV_CPU(cs); 682 CPURISCVState *env = &cpu->env; 683 /* 684 * Definition of the WFI instruction requires it to ignore the privilege 685 * mode and delegation registers, but respect individual enables 686 */ 687 return riscv_cpu_all_pending(env) != 0; 688 #else 689 return true; 690 #endif 691 } 692 693 static void riscv_restore_state_to_opc(CPUState *cs, 694 const TranslationBlock *tb, 695 const uint64_t *data) 696 { 697 RISCVCPU *cpu = RISCV_CPU(cs); 698 CPURISCVState *env = &cpu->env; 699 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 700 701 if (xl == MXL_RV32) { 702 env->pc = (int32_t)data[0]; 703 } else { 704 env->pc = data[0]; 705 } 706 env->bins = data[1]; 707 } 708 709 static void riscv_cpu_reset_hold(Object *obj) 710 { 711 #ifndef CONFIG_USER_ONLY 712 uint8_t iprio; 713 int i, irq, rdzero; 714 #endif 715 CPUState *cs = CPU(obj); 716 RISCVCPU *cpu = RISCV_CPU(cs); 717 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 718 CPURISCVState *env = &cpu->env; 719 720 if (mcc->parent_phases.hold) { 721 mcc->parent_phases.hold(obj); 722 } 723 #ifndef CONFIG_USER_ONLY 724 env->misa_mxl = env->misa_mxl_max; 725 env->priv = PRV_M; 726 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 727 if (env->misa_mxl > MXL_RV32) { 728 /* 729 * The reset status of SXL/UXL is undefined, but mstatus is WARL 730 * and we must ensure that the value after init is valid for read. 731 */ 732 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 733 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 734 if (riscv_has_ext(env, RVH)) { 735 env->vsstatus = set_field(env->vsstatus, 736 MSTATUS64_SXL, env->misa_mxl); 737 env->vsstatus = set_field(env->vsstatus, 738 MSTATUS64_UXL, env->misa_mxl); 739 env->mstatus_hs = set_field(env->mstatus_hs, 740 MSTATUS64_SXL, env->misa_mxl); 741 env->mstatus_hs = set_field(env->mstatus_hs, 742 MSTATUS64_UXL, env->misa_mxl); 743 } 744 } 745 env->mcause = 0; 746 env->miclaim = MIP_SGEIP; 747 env->pc = env->resetvec; 748 env->bins = 0; 749 env->two_stage_lookup = false; 750 751 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | 752 (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); 753 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | 754 (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); 755 756 /* Initialized default priorities of local interrupts. */ 757 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 758 iprio = riscv_cpu_default_priority(i); 759 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 760 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 761 env->hviprio[i] = 0; 762 } 763 i = 0; 764 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 765 if (!rdzero) { 766 env->hviprio[irq] = env->miprio[irq]; 767 } 768 i++; 769 } 770 /* mmte is supposed to have pm.current hardwired to 1 */ 771 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 772 #endif 773 env->xl = riscv_cpu_mxl(env); 774 riscv_cpu_update_mask(env); 775 cs->exception_index = RISCV_EXCP_NONE; 776 env->load_res = -1; 777 set_default_nan_mode(1, &env->fp_status); 778 779 #ifndef CONFIG_USER_ONLY 780 if (cpu->cfg.debug) { 781 riscv_trigger_init(env); 782 } 783 784 if (kvm_enabled()) { 785 kvm_riscv_reset_vcpu(cpu); 786 } 787 #endif 788 } 789 790 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 791 { 792 RISCVCPU *cpu = RISCV_CPU(s); 793 794 switch (riscv_cpu_mxl(&cpu->env)) { 795 case MXL_RV32: 796 info->print_insn = print_insn_riscv32; 797 break; 798 case MXL_RV64: 799 info->print_insn = print_insn_riscv64; 800 break; 801 case MXL_RV128: 802 info->print_insn = print_insn_riscv128; 803 break; 804 default: 805 g_assert_not_reached(); 806 } 807 } 808 809 /* 810 * Check consistency between chosen extensions while setting 811 * cpu->cfg accordingly. 812 */ 813 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 814 { 815 CPURISCVState *env = &cpu->env; 816 817 /* Do some ISA extension error checking */ 818 if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && 819 riscv_has_ext(env, RVM) && 820 riscv_has_ext(env, RVA) && 821 riscv_has_ext(env, RVF) && 822 riscv_has_ext(env, RVD) && 823 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 824 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 825 cpu->cfg.ext_icsr = true; 826 cpu->cfg.ext_ifencei = true; 827 828 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; 829 env->misa_ext_mask = env->misa_ext; 830 } 831 832 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 833 error_setg(errp, 834 "I and E extensions are incompatible"); 835 return; 836 } 837 838 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 839 error_setg(errp, 840 "Either I or E extension must be set"); 841 return; 842 } 843 844 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 845 error_setg(errp, 846 "Setting S extension without U extension is illegal"); 847 return; 848 } 849 850 if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) { 851 error_setg(errp, 852 "H depends on an I base integer ISA with 32 x registers"); 853 return; 854 } 855 856 if (cpu->cfg.ext_h && !riscv_has_ext(env, RVS)) { 857 error_setg(errp, "H extension implicitly requires S-mode"); 858 return; 859 } 860 861 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { 862 error_setg(errp, "F extension requires Zicsr"); 863 return; 864 } 865 866 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 867 error_setg(errp, "Zawrs extension requires A extension"); 868 return; 869 } 870 871 if (cpu->cfg.ext_zfh) { 872 cpu->cfg.ext_zfhmin = true; 873 } 874 875 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 876 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 877 return; 878 } 879 880 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 881 error_setg(errp, "D extension requires F extension"); 882 return; 883 } 884 885 /* The V vector extension depends on the Zve64d extension */ 886 if (cpu->cfg.ext_v) { 887 cpu->cfg.ext_zve64d = true; 888 } 889 890 /* The Zve64d extension depends on the Zve64f extension */ 891 if (cpu->cfg.ext_zve64d) { 892 cpu->cfg.ext_zve64f = true; 893 } 894 895 /* The Zve64f extension depends on the Zve32f extension */ 896 if (cpu->cfg.ext_zve64f) { 897 cpu->cfg.ext_zve32f = true; 898 } 899 900 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 901 error_setg(errp, "Zve64d/V extensions require D extension"); 902 return; 903 } 904 905 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 906 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 907 return; 908 } 909 910 if (cpu->cfg.ext_zvfh) { 911 cpu->cfg.ext_zvfhmin = true; 912 } 913 914 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 915 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 916 return; 917 } 918 919 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 920 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 921 return; 922 } 923 924 /* Set the ISA extensions, checks should have happened above */ 925 if (cpu->cfg.ext_zhinx) { 926 cpu->cfg.ext_zhinxmin = true; 927 } 928 929 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { 930 cpu->cfg.ext_zfinx = true; 931 } 932 933 if (cpu->cfg.ext_zfinx) { 934 if (!cpu->cfg.ext_icsr) { 935 error_setg(errp, "Zfinx extension requires Zicsr"); 936 return; 937 } 938 if (riscv_has_ext(env, RVF)) { 939 error_setg(errp, 940 "Zfinx cannot be supported together with F extension"); 941 return; 942 } 943 } 944 945 if (cpu->cfg.ext_zce) { 946 cpu->cfg.ext_zca = true; 947 cpu->cfg.ext_zcb = true; 948 cpu->cfg.ext_zcmp = true; 949 cpu->cfg.ext_zcmt = true; 950 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 951 cpu->cfg.ext_zcf = true; 952 } 953 } 954 955 if (riscv_has_ext(env, RVC)) { 956 cpu->cfg.ext_zca = true; 957 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 958 cpu->cfg.ext_zcf = true; 959 } 960 if (riscv_has_ext(env, RVD)) { 961 cpu->cfg.ext_zcd = true; 962 } 963 } 964 965 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 966 error_setg(errp, "Zcf extension is only relevant to RV32"); 967 return; 968 } 969 970 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 971 error_setg(errp, "Zcf extension requires F extension"); 972 return; 973 } 974 975 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 976 error_setg(errp, "Zcd extension requires D extension"); 977 return; 978 } 979 980 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 981 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 982 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 983 "extension"); 984 return; 985 } 986 987 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 988 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 989 "Zcd extension"); 990 return; 991 } 992 993 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { 994 error_setg(errp, "Zcmt extension requires Zicsr extension"); 995 return; 996 } 997 998 if (cpu->cfg.ext_zk) { 999 cpu->cfg.ext_zkn = true; 1000 cpu->cfg.ext_zkr = true; 1001 cpu->cfg.ext_zkt = true; 1002 } 1003 1004 if (cpu->cfg.ext_zkn) { 1005 cpu->cfg.ext_zbkb = true; 1006 cpu->cfg.ext_zbkc = true; 1007 cpu->cfg.ext_zbkx = true; 1008 cpu->cfg.ext_zkne = true; 1009 cpu->cfg.ext_zknd = true; 1010 cpu->cfg.ext_zknh = true; 1011 } 1012 1013 if (cpu->cfg.ext_zks) { 1014 cpu->cfg.ext_zbkb = true; 1015 cpu->cfg.ext_zbkc = true; 1016 cpu->cfg.ext_zbkx = true; 1017 cpu->cfg.ext_zksed = true; 1018 cpu->cfg.ext_zksh = true; 1019 } 1020 1021 if (cpu->cfg.ext_v) { 1022 int vext_version = VEXT_VERSION_1_00_0; 1023 if (!is_power_of_2(cpu->cfg.vlen)) { 1024 error_setg(errp, 1025 "Vector extension VLEN must be power of 2"); 1026 return; 1027 } 1028 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 1029 error_setg(errp, 1030 "Vector extension implementation only supports VLEN " 1031 "in the range [128, %d]", RV_VLEN_MAX); 1032 return; 1033 } 1034 if (!is_power_of_2(cpu->cfg.elen)) { 1035 error_setg(errp, 1036 "Vector extension ELEN must be power of 2"); 1037 return; 1038 } 1039 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 1040 error_setg(errp, 1041 "Vector extension implementation only supports ELEN " 1042 "in the range [8, 64]"); 1043 return; 1044 } 1045 if (cpu->cfg.vext_spec) { 1046 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 1047 vext_version = VEXT_VERSION_1_00_0; 1048 } else { 1049 error_setg(errp, 1050 "Unsupported vector spec version '%s'", 1051 cpu->cfg.vext_spec); 1052 return; 1053 } 1054 } else { 1055 qemu_log("vector version is not specified, " 1056 "use the default value v1.0\n"); 1057 } 1058 set_vext_version(env, vext_version); 1059 } 1060 } 1061 1062 #ifndef CONFIG_USER_ONLY 1063 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) 1064 { 1065 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 1066 uint8_t satp_mode_map_max; 1067 uint8_t satp_mode_supported_max = 1068 satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 1069 1070 if (cpu->cfg.satp_mode.map == 0) { 1071 if (cpu->cfg.satp_mode.init == 0) { 1072 /* If unset by the user, we fallback to the default satp mode. */ 1073 set_satp_mode_default_map(cpu); 1074 } else { 1075 /* 1076 * Find the lowest level that was disabled and then enable the 1077 * first valid level below which can be found in 1078 * valid_vm_1_10_32/64. 1079 */ 1080 for (int i = 1; i < 16; ++i) { 1081 if ((cpu->cfg.satp_mode.init & (1 << i)) && 1082 (cpu->cfg.satp_mode.supported & (1 << i))) { 1083 for (int j = i - 1; j >= 0; --j) { 1084 if (cpu->cfg.satp_mode.supported & (1 << j)) { 1085 cpu->cfg.satp_mode.map |= (1 << j); 1086 break; 1087 } 1088 } 1089 break; 1090 } 1091 } 1092 } 1093 } 1094 1095 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 1096 1097 /* Make sure the user asked for a supported configuration (HW and qemu) */ 1098 if (satp_mode_map_max > satp_mode_supported_max) { 1099 error_setg(errp, "satp_mode %s is higher than hw max capability %s", 1100 satp_mode_str(satp_mode_map_max, rv32), 1101 satp_mode_str(satp_mode_supported_max, rv32)); 1102 return; 1103 } 1104 1105 /* 1106 * Make sure the user did not ask for an invalid configuration as per 1107 * the specification. 1108 */ 1109 if (!rv32) { 1110 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1111 if (!(cpu->cfg.satp_mode.map & (1 << i)) && 1112 (cpu->cfg.satp_mode.init & (1 << i)) && 1113 (cpu->cfg.satp_mode.supported & (1 << i))) { 1114 error_setg(errp, "cannot disable %s satp mode if %s " 1115 "is enabled", satp_mode_str(i, false), 1116 satp_mode_str(satp_mode_map_max, false)); 1117 return; 1118 } 1119 } 1120 } 1121 1122 /* Finally expand the map so that all valid modes are set */ 1123 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1124 if (cpu->cfg.satp_mode.supported & (1 << i)) { 1125 cpu->cfg.satp_mode.map |= (1 << i); 1126 } 1127 } 1128 } 1129 #endif 1130 1131 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1132 { 1133 #ifndef CONFIG_USER_ONLY 1134 Error *local_err = NULL; 1135 1136 riscv_cpu_satp_mode_finalize(cpu, &local_err); 1137 if (local_err != NULL) { 1138 error_propagate(errp, local_err); 1139 return; 1140 } 1141 #endif 1142 } 1143 1144 static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) 1145 { 1146 uint32_t ext = 0; 1147 1148 if (riscv_has_ext(env, RVI)) { 1149 ext |= RVI; 1150 } 1151 if (riscv_has_ext(env, RVE)) { 1152 ext |= RVE; 1153 } 1154 if (riscv_has_ext(env, RVM)) { 1155 ext |= RVM; 1156 } 1157 if (riscv_has_ext(env, RVA)) { 1158 ext |= RVA; 1159 } 1160 if (riscv_has_ext(env, RVF)) { 1161 ext |= RVF; 1162 } 1163 if (riscv_has_ext(env, RVD)) { 1164 ext |= RVD; 1165 } 1166 if (riscv_has_ext(env, RVC)) { 1167 ext |= RVC; 1168 } 1169 if (riscv_has_ext(env, RVS)) { 1170 ext |= RVS; 1171 } 1172 if (riscv_has_ext(env, RVU)) { 1173 ext |= RVU; 1174 } 1175 if (riscv_cpu_cfg(env)->ext_h) { 1176 ext |= RVH; 1177 } 1178 if (riscv_cpu_cfg(env)->ext_v) { 1179 ext |= RVV; 1180 } 1181 if (riscv_cpu_cfg(env)->ext_j) { 1182 ext |= RVJ; 1183 } 1184 1185 env->misa_ext = env->misa_ext_mask = ext; 1186 } 1187 1188 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 1189 { 1190 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 1191 error_setg(errp, "H extension requires priv spec 1.12.0"); 1192 return; 1193 } 1194 } 1195 1196 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 1197 { 1198 CPUState *cs = CPU(dev); 1199 RISCVCPU *cpu = RISCV_CPU(dev); 1200 CPURISCVState *env = &cpu->env; 1201 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 1202 CPUClass *cc = CPU_CLASS(mcc); 1203 int i, priv_version = -1; 1204 Error *local_err = NULL; 1205 1206 cpu_exec_realizefn(cs, &local_err); 1207 if (local_err != NULL) { 1208 error_propagate(errp, local_err); 1209 return; 1210 } 1211 1212 if (cpu->cfg.priv_spec) { 1213 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 1214 priv_version = PRIV_VERSION_1_12_0; 1215 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 1216 priv_version = PRIV_VERSION_1_11_0; 1217 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 1218 priv_version = PRIV_VERSION_1_10_0; 1219 } else { 1220 error_setg(errp, 1221 "Unsupported privilege spec version '%s'", 1222 cpu->cfg.priv_spec); 1223 return; 1224 } 1225 } 1226 1227 if (priv_version >= PRIV_VERSION_1_10_0) { 1228 set_priv_version(env, priv_version); 1229 } 1230 1231 /* 1232 * We can't be sure of whether we set defaults during cpu_init() 1233 * or whether the user enabled/disabled some bits via cpu->cfg 1234 * flags. Sync env->misa_ext with cpu->cfg now to allow us to 1235 * use just env->misa_ext later. 1236 */ 1237 riscv_cpu_sync_misa_cfg(env); 1238 1239 riscv_cpu_validate_misa_priv(env, &local_err); 1240 if (local_err != NULL) { 1241 error_propagate(errp, local_err); 1242 return; 1243 } 1244 1245 /* Force disable extensions if priv spec version does not match */ 1246 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1247 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 1248 (env->priv_ver < isa_edata_arr[i].min_version)) { 1249 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 1250 #ifndef CONFIG_USER_ONLY 1251 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 1252 " because privilege spec version does not match", 1253 isa_edata_arr[i].name, env->mhartid); 1254 #else 1255 warn_report("disabling %s extension because " 1256 "privilege spec version does not match", 1257 isa_edata_arr[i].name); 1258 #endif 1259 } 1260 } 1261 1262 if (cpu->cfg.epmp && !cpu->cfg.pmp) { 1263 /* 1264 * Enhanced PMP should only be available 1265 * on harts with PMP support 1266 */ 1267 error_setg(errp, "Invalid configuration: EPMP requires PMP support"); 1268 return; 1269 } 1270 1271 1272 #ifndef CONFIG_USER_ONLY 1273 if (cpu->cfg.ext_sstc) { 1274 riscv_timer_init(cpu); 1275 } 1276 #endif /* CONFIG_USER_ONLY */ 1277 1278 /* Validate that MISA_MXL is set properly. */ 1279 switch (env->misa_mxl_max) { 1280 #ifdef TARGET_RISCV64 1281 case MXL_RV64: 1282 case MXL_RV128: 1283 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 1284 break; 1285 #endif 1286 case MXL_RV32: 1287 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 1288 break; 1289 default: 1290 g_assert_not_reached(); 1291 } 1292 assert(env->misa_mxl_max == env->misa_mxl); 1293 1294 riscv_cpu_validate_set_extensions(cpu, &local_err); 1295 if (local_err != NULL) { 1296 error_propagate(errp, local_err); 1297 return; 1298 } 1299 1300 #ifndef CONFIG_USER_ONLY 1301 if (cpu->cfg.pmu_num) { 1302 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 1303 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1304 riscv_pmu_timer_cb, cpu); 1305 } 1306 } 1307 #endif 1308 1309 riscv_cpu_finalize_features(cpu, &local_err); 1310 if (local_err != NULL) { 1311 error_propagate(errp, local_err); 1312 return; 1313 } 1314 1315 riscv_cpu_register_gdb_regs_for_features(cs); 1316 1317 qemu_init_vcpu(cs); 1318 cpu_reset(cs); 1319 1320 mcc->parent_realize(dev, errp); 1321 } 1322 1323 #ifndef CONFIG_USER_ONLY 1324 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, 1325 void *opaque, Error **errp) 1326 { 1327 RISCVSATPMap *satp_map = opaque; 1328 uint8_t satp = satp_mode_from_str(name); 1329 bool value; 1330 1331 value = satp_map->map & (1 << satp); 1332 1333 visit_type_bool(v, name, &value, errp); 1334 } 1335 1336 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, 1337 void *opaque, Error **errp) 1338 { 1339 RISCVSATPMap *satp_map = opaque; 1340 uint8_t satp = satp_mode_from_str(name); 1341 bool value; 1342 1343 if (!visit_type_bool(v, name, &value, errp)) { 1344 return; 1345 } 1346 1347 satp_map->map = deposit32(satp_map->map, satp, 1, value); 1348 satp_map->init |= 1 << satp; 1349 } 1350 1351 static void riscv_add_satp_mode_properties(Object *obj) 1352 { 1353 RISCVCPU *cpu = RISCV_CPU(obj); 1354 1355 if (cpu->env.misa_mxl == MXL_RV32) { 1356 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, 1357 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1358 } else { 1359 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, 1360 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1361 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, 1362 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1363 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, 1364 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1365 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, 1366 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1367 } 1368 } 1369 1370 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1371 { 1372 RISCVCPU *cpu = RISCV_CPU(opaque); 1373 CPURISCVState *env = &cpu->env; 1374 1375 if (irq < IRQ_LOCAL_MAX) { 1376 switch (irq) { 1377 case IRQ_U_SOFT: 1378 case IRQ_S_SOFT: 1379 case IRQ_VS_SOFT: 1380 case IRQ_M_SOFT: 1381 case IRQ_U_TIMER: 1382 case IRQ_S_TIMER: 1383 case IRQ_VS_TIMER: 1384 case IRQ_M_TIMER: 1385 case IRQ_U_EXT: 1386 case IRQ_VS_EXT: 1387 case IRQ_M_EXT: 1388 if (kvm_enabled()) { 1389 kvm_riscv_set_irq(cpu, irq, level); 1390 } else { 1391 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); 1392 } 1393 break; 1394 case IRQ_S_EXT: 1395 if (kvm_enabled()) { 1396 kvm_riscv_set_irq(cpu, irq, level); 1397 } else { 1398 env->external_seip = level; 1399 riscv_cpu_update_mip(env, 1 << irq, 1400 BOOL_TO_MASK(level | env->software_seip)); 1401 } 1402 break; 1403 default: 1404 g_assert_not_reached(); 1405 } 1406 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1407 /* Require H-extension for handling guest local interrupts */ 1408 if (!riscv_has_ext(env, RVH)) { 1409 g_assert_not_reached(); 1410 } 1411 1412 /* Compute bit position in HGEIP CSR */ 1413 irq = irq - IRQ_LOCAL_MAX + 1; 1414 if (env->geilen < irq) { 1415 g_assert_not_reached(); 1416 } 1417 1418 /* Update HGEIP CSR */ 1419 env->hgeip &= ~((target_ulong)1 << irq); 1420 if (level) { 1421 env->hgeip |= (target_ulong)1 << irq; 1422 } 1423 1424 /* Update mip.SGEIP bit */ 1425 riscv_cpu_update_mip(env, MIP_SGEIP, 1426 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1427 } else { 1428 g_assert_not_reached(); 1429 } 1430 } 1431 #endif /* CONFIG_USER_ONLY */ 1432 1433 static void riscv_cpu_init(Object *obj) 1434 { 1435 RISCVCPU *cpu = RISCV_CPU(obj); 1436 1437 cpu->cfg.ext_ifencei = true; 1438 cpu->cfg.ext_icsr = true; 1439 cpu->cfg.mmu = true; 1440 cpu->cfg.pmp = true; 1441 1442 cpu_set_cpustate_pointers(cpu); 1443 1444 #ifndef CONFIG_USER_ONLY 1445 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1446 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1447 #endif /* CONFIG_USER_ONLY */ 1448 } 1449 1450 typedef struct RISCVCPUMisaExtConfig { 1451 const char *name; 1452 const char *description; 1453 target_ulong misa_bit; 1454 bool enabled; 1455 } RISCVCPUMisaExtConfig; 1456 1457 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1458 void *opaque, Error **errp) 1459 { 1460 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1461 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1462 RISCVCPU *cpu = RISCV_CPU(obj); 1463 CPURISCVState *env = &cpu->env; 1464 bool value; 1465 1466 if (!visit_type_bool(v, name, &value, errp)) { 1467 return; 1468 } 1469 1470 if (value) { 1471 env->misa_ext |= misa_bit; 1472 env->misa_ext_mask |= misa_bit; 1473 } else { 1474 env->misa_ext &= ~misa_bit; 1475 env->misa_ext_mask &= ~misa_bit; 1476 } 1477 } 1478 1479 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1480 void *opaque, Error **errp) 1481 { 1482 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1483 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1484 RISCVCPU *cpu = RISCV_CPU(obj); 1485 CPURISCVState *env = &cpu->env; 1486 bool value; 1487 1488 value = env->misa_ext & misa_bit; 1489 1490 visit_type_bool(v, name, &value, errp); 1491 } 1492 1493 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1494 {.name = "a", .description = "Atomic instructions", 1495 .misa_bit = RVA, .enabled = true}, 1496 {.name = "c", .description = "Compressed instructions", 1497 .misa_bit = RVC, .enabled = true}, 1498 {.name = "d", .description = "Double-precision float point", 1499 .misa_bit = RVD, .enabled = true}, 1500 {.name = "f", .description = "Single-precision float point", 1501 .misa_bit = RVF, .enabled = true}, 1502 {.name = "i", .description = "Base integer instruction set", 1503 .misa_bit = RVI, .enabled = true}, 1504 {.name = "e", .description = "Base integer instruction set (embedded)", 1505 .misa_bit = RVE, .enabled = false}, 1506 {.name = "m", .description = "Integer multiplication and division", 1507 .misa_bit = RVM, .enabled = true}, 1508 {.name = "s", .description = "Supervisor-level instructions", 1509 .misa_bit = RVS, .enabled = true}, 1510 {.name = "u", .description = "User-level instructions", 1511 .misa_bit = RVU, .enabled = true}, 1512 }; 1513 1514 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1515 { 1516 int i; 1517 1518 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1519 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1520 1521 object_property_add(cpu_obj, misa_cfg->name, "bool", 1522 cpu_get_misa_ext_cfg, 1523 cpu_set_misa_ext_cfg, 1524 NULL, (void *)misa_cfg); 1525 object_property_set_description(cpu_obj, misa_cfg->name, 1526 misa_cfg->description); 1527 object_property_set_bool(cpu_obj, misa_cfg->name, 1528 misa_cfg->enabled, NULL); 1529 } 1530 } 1531 1532 static Property riscv_cpu_extensions[] = { 1533 /* Defaults for standard extensions */ 1534 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1535 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1536 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1537 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1538 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1539 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1540 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1541 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1542 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1543 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1544 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1545 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1546 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1547 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), 1548 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1549 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1550 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1551 1552 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1553 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1554 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1555 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1556 1557 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), 1558 1559 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1560 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1561 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1562 1563 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1564 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1565 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1566 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1567 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1568 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1569 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1570 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1571 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1572 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1573 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1574 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1575 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1576 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1577 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1578 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1579 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1580 1581 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1582 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1583 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1584 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1585 1586 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), 1587 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), 1588 DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), 1589 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), 1590 1591 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1592 1593 /* Vendor-specific custom extensions */ 1594 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1595 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1596 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1597 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1598 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1599 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1600 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1601 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1602 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1603 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1604 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1605 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1606 1607 /* These are experimental so mark with 'x-' */ 1608 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), 1609 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1610 1611 DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), 1612 DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), 1613 DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), 1614 DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), 1615 DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), 1616 DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), 1617 DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), 1618 1619 /* ePMP 0.9.3 */ 1620 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1621 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1622 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1623 1624 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), 1625 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), 1626 1627 DEFINE_PROP_END_OF_LIST(), 1628 }; 1629 1630 /* 1631 * Register CPU props based on env.misa_ext. If a non-zero 1632 * value was set, register only the required cpu->cfg.ext_* 1633 * properties and leave. env.misa_ext = 0 means that we want 1634 * all the default properties to be registered. 1635 */ 1636 static void register_cpu_props(Object *obj) 1637 { 1638 RISCVCPU *cpu = RISCV_CPU(obj); 1639 uint32_t misa_ext = cpu->env.misa_ext; 1640 Property *prop; 1641 DeviceState *dev = DEVICE(obj); 1642 1643 /* 1644 * If misa_ext is not zero, set cfg properties now to 1645 * allow them to be read during riscv_cpu_realize() 1646 * later on. 1647 */ 1648 if (cpu->env.misa_ext != 0) { 1649 cpu->cfg.ext_v = misa_ext & RVV; 1650 cpu->cfg.ext_h = misa_ext & RVH; 1651 cpu->cfg.ext_j = misa_ext & RVJ; 1652 1653 /* 1654 * We don't want to set the default riscv_cpu_extensions 1655 * in this case. 1656 */ 1657 return; 1658 } 1659 1660 riscv_cpu_add_misa_properties(obj); 1661 1662 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1663 qdev_property_add_static(dev, prop); 1664 } 1665 1666 #ifndef CONFIG_USER_ONLY 1667 riscv_add_satp_mode_properties(obj); 1668 #endif 1669 } 1670 1671 static Property riscv_cpu_properties[] = { 1672 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1673 1674 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1675 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1676 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1677 1678 #ifndef CONFIG_USER_ONLY 1679 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1680 #endif 1681 1682 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1683 1684 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1685 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1686 1687 /* 1688 * write_misa() is marked as experimental for now so mark 1689 * it with -x and default to 'false'. 1690 */ 1691 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1692 DEFINE_PROP_END_OF_LIST(), 1693 }; 1694 1695 static gchar *riscv_gdb_arch_name(CPUState *cs) 1696 { 1697 RISCVCPU *cpu = RISCV_CPU(cs); 1698 CPURISCVState *env = &cpu->env; 1699 1700 switch (riscv_cpu_mxl(env)) { 1701 case MXL_RV32: 1702 return g_strdup("riscv:rv32"); 1703 case MXL_RV64: 1704 case MXL_RV128: 1705 return g_strdup("riscv:rv64"); 1706 default: 1707 g_assert_not_reached(); 1708 } 1709 } 1710 1711 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1712 { 1713 RISCVCPU *cpu = RISCV_CPU(cs); 1714 1715 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1716 return cpu->dyn_csr_xml; 1717 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1718 return cpu->dyn_vreg_xml; 1719 } 1720 1721 return NULL; 1722 } 1723 1724 #ifndef CONFIG_USER_ONLY 1725 static int64_t riscv_get_arch_id(CPUState *cs) 1726 { 1727 RISCVCPU *cpu = RISCV_CPU(cs); 1728 1729 return cpu->env.mhartid; 1730 } 1731 1732 #include "hw/core/sysemu-cpu-ops.h" 1733 1734 static const struct SysemuCPUOps riscv_sysemu_ops = { 1735 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1736 .write_elf64_note = riscv_cpu_write_elf64_note, 1737 .write_elf32_note = riscv_cpu_write_elf32_note, 1738 .legacy_vmsd = &vmstate_riscv_cpu, 1739 }; 1740 #endif 1741 1742 #include "hw/core/tcg-cpu-ops.h" 1743 1744 static const struct TCGCPUOps riscv_tcg_ops = { 1745 .initialize = riscv_translate_init, 1746 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1747 .restore_state_to_opc = riscv_restore_state_to_opc, 1748 1749 #ifndef CONFIG_USER_ONLY 1750 .tlb_fill = riscv_cpu_tlb_fill, 1751 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1752 .do_interrupt = riscv_cpu_do_interrupt, 1753 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1754 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1755 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1756 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1757 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1758 #endif /* !CONFIG_USER_ONLY */ 1759 }; 1760 1761 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1762 { 1763 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1764 CPUClass *cc = CPU_CLASS(c); 1765 DeviceClass *dc = DEVICE_CLASS(c); 1766 ResettableClass *rc = RESETTABLE_CLASS(c); 1767 1768 device_class_set_parent_realize(dc, riscv_cpu_realize, 1769 &mcc->parent_realize); 1770 1771 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1772 &mcc->parent_phases); 1773 1774 cc->class_by_name = riscv_cpu_class_by_name; 1775 cc->has_work = riscv_cpu_has_work; 1776 cc->dump_state = riscv_cpu_dump_state; 1777 cc->set_pc = riscv_cpu_set_pc; 1778 cc->get_pc = riscv_cpu_get_pc; 1779 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1780 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1781 cc->gdb_num_core_regs = 33; 1782 cc->gdb_stop_before_watchpoint = true; 1783 cc->disas_set_info = riscv_cpu_disas_set_info; 1784 #ifndef CONFIG_USER_ONLY 1785 cc->sysemu_ops = &riscv_sysemu_ops; 1786 cc->get_arch_id = riscv_get_arch_id; 1787 #endif 1788 cc->gdb_arch_name = riscv_gdb_arch_name; 1789 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1790 cc->tcg_ops = &riscv_tcg_ops; 1791 1792 device_class_set_props(dc, riscv_cpu_properties); 1793 } 1794 1795 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, 1796 int max_str_len) 1797 { 1798 char *old = *isa_str; 1799 char *new = *isa_str; 1800 int i; 1801 1802 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1803 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1804 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1805 g_free(old); 1806 old = new; 1807 } 1808 } 1809 1810 *isa_str = new; 1811 } 1812 1813 char *riscv_isa_string(RISCVCPU *cpu) 1814 { 1815 int i; 1816 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1817 char *isa_str = g_new(char, maxlen); 1818 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1819 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1820 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1821 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1822 } 1823 } 1824 *p = '\0'; 1825 if (!cpu->cfg.short_isa_string) { 1826 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1827 } 1828 return isa_str; 1829 } 1830 1831 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1832 { 1833 ObjectClass *class_a = (ObjectClass *)a; 1834 ObjectClass *class_b = (ObjectClass *)b; 1835 const char *name_a, *name_b; 1836 1837 name_a = object_class_get_name(class_a); 1838 name_b = object_class_get_name(class_b); 1839 return strcmp(name_a, name_b); 1840 } 1841 1842 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1843 { 1844 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1845 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1846 1847 qemu_printf("%.*s\n", len, typename); 1848 } 1849 1850 void riscv_cpu_list(void) 1851 { 1852 GSList *list; 1853 1854 list = object_class_get_list(TYPE_RISCV_CPU, false); 1855 list = g_slist_sort(list, riscv_cpu_list_compare); 1856 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1857 g_slist_free(list); 1858 } 1859 1860 #define DEFINE_CPU(type_name, initfn) \ 1861 { \ 1862 .name = type_name, \ 1863 .parent = TYPE_RISCV_CPU, \ 1864 .instance_init = initfn \ 1865 } 1866 1867 static const TypeInfo riscv_cpu_type_infos[] = { 1868 { 1869 .name = TYPE_RISCV_CPU, 1870 .parent = TYPE_CPU, 1871 .instance_size = sizeof(RISCVCPU), 1872 .instance_align = __alignof__(RISCVCPU), 1873 .instance_init = riscv_cpu_init, 1874 .abstract = true, 1875 .class_size = sizeof(RISCVCPUClass), 1876 .class_init = riscv_cpu_class_init, 1877 }, 1878 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1879 #if defined(CONFIG_KVM) 1880 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1881 #endif 1882 #if defined(TARGET_RISCV32) 1883 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1884 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1885 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1886 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1887 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1888 #elif defined(TARGET_RISCV64) 1889 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1890 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1891 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1892 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1893 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1894 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1895 #endif 1896 }; 1897 1898 DEFINE_TYPES(riscv_cpu_type_infos) 1899