1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "exec/exec-all.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "fpu/softfloat-helpers.h" 32 #include "sysemu/kvm.h" 33 #include "kvm_riscv.h" 34 35 /* RISC-V CPU definitions */ 36 37 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 38 (QEMU_VERSION_MINOR << 8) | \ 39 (QEMU_VERSION_MICRO)) 40 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 41 42 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 43 44 struct isa_ext_data { 45 const char *name; 46 bool multi_letter; 47 int min_version; 48 int ext_enable_offset; 49 }; 50 51 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ 52 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 53 54 /** 55 * Here are the ordering rules of extension naming defined by RISC-V 56 * specification : 57 * 1. All extensions should be separated from other multi-letter extensions 58 * by an underscore. 59 * 2. The first letter following the 'Z' conventionally indicates the most 60 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 61 * If multiple 'Z' extensions are named, they should be ordered first 62 * by category, then alphabetically within a category. 63 * 3. Standard supervisor-level extensions (starts with 'S') should be 64 * listed after standard unprivileged extensions. If multiple 65 * supervisor-level extensions are listed, they should be ordered 66 * alphabetically. 67 * 4. Non-standard extensions (starts with 'X') must be listed after all 68 * standard extensions. They must be separated from other multi-letter 69 * extensions by an underscore. 70 */ 71 static const struct isa_ext_data isa_edata_arr[] = { 72 ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), 73 ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), 74 ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), 75 ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), 76 ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), 77 ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), 78 ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), 79 ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), 80 ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), 81 ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), 82 ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), 83 ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), 84 ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), 85 ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), 86 ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), 87 ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), 88 ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), 89 ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), 90 ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), 91 ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), 92 ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), 93 ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), 94 ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), 95 ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), 96 ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), 97 ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), 98 ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), 99 ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), 100 ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), 101 ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), 102 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), 103 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), 104 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), 105 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 106 }; 107 108 static bool isa_ext_is_enabled(RISCVCPU *cpu, 109 const struct isa_ext_data *edata) 110 { 111 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 112 113 return *ext_enabled; 114 } 115 116 static void isa_ext_update_enabled(RISCVCPU *cpu, 117 const struct isa_ext_data *edata, bool en) 118 { 119 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 120 121 *ext_enabled = en; 122 } 123 124 const char * const riscv_int_regnames[] = { 125 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 126 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 127 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 128 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 129 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 130 }; 131 132 const char * const riscv_int_regnamesh[] = { 133 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 134 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 135 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 136 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 137 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 138 "x30h/t5h", "x31h/t6h" 139 }; 140 141 const char * const riscv_fpr_regnames[] = { 142 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 143 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 144 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 145 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 146 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 147 "f30/ft10", "f31/ft11" 148 }; 149 150 static const char * const riscv_excp_names[] = { 151 "misaligned_fetch", 152 "fault_fetch", 153 "illegal_instruction", 154 "breakpoint", 155 "misaligned_load", 156 "fault_load", 157 "misaligned_store", 158 "fault_store", 159 "user_ecall", 160 "supervisor_ecall", 161 "hypervisor_ecall", 162 "machine_ecall", 163 "exec_page_fault", 164 "load_page_fault", 165 "reserved", 166 "store_page_fault", 167 "reserved", 168 "reserved", 169 "reserved", 170 "reserved", 171 "guest_exec_page_fault", 172 "guest_load_page_fault", 173 "reserved", 174 "guest_store_page_fault", 175 }; 176 177 static const char * const riscv_intr_names[] = { 178 "u_software", 179 "s_software", 180 "vs_software", 181 "m_software", 182 "u_timer", 183 "s_timer", 184 "vs_timer", 185 "m_timer", 186 "u_external", 187 "s_external", 188 "vs_external", 189 "m_external", 190 "reserved", 191 "reserved", 192 "reserved", 193 "reserved" 194 }; 195 196 static void register_cpu_props(DeviceState *dev); 197 198 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 199 { 200 if (async) { 201 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 202 riscv_intr_names[cause] : "(unknown)"; 203 } else { 204 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 205 riscv_excp_names[cause] : "(unknown)"; 206 } 207 } 208 209 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 210 { 211 env->misa_mxl_max = env->misa_mxl = mxl; 212 env->misa_ext_mask = env->misa_ext = ext; 213 } 214 215 static void set_priv_version(CPURISCVState *env, int priv_ver) 216 { 217 env->priv_ver = priv_ver; 218 } 219 220 static void set_vext_version(CPURISCVState *env, int vext_ver) 221 { 222 env->vext_ver = vext_ver; 223 } 224 225 static void set_resetvec(CPURISCVState *env, target_ulong resetvec) 226 { 227 #ifndef CONFIG_USER_ONLY 228 env->resetvec = resetvec; 229 #endif 230 } 231 232 static void riscv_any_cpu_init(Object *obj) 233 { 234 CPURISCVState *env = &RISCV_CPU(obj)->env; 235 #if defined(TARGET_RISCV32) 236 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 237 #elif defined(TARGET_RISCV64) 238 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 239 #endif 240 set_priv_version(env, PRIV_VERSION_1_12_0); 241 register_cpu_props(DEVICE(obj)); 242 } 243 244 #if defined(TARGET_RISCV64) 245 static void rv64_base_cpu_init(Object *obj) 246 { 247 CPURISCVState *env = &RISCV_CPU(obj)->env; 248 /* We set this in the realise function */ 249 set_misa(env, MXL_RV64, 0); 250 register_cpu_props(DEVICE(obj)); 251 /* Set latest version of privileged specification */ 252 set_priv_version(env, PRIV_VERSION_1_12_0); 253 } 254 255 static void rv64_sifive_u_cpu_init(Object *obj) 256 { 257 CPURISCVState *env = &RISCV_CPU(obj)->env; 258 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 259 set_priv_version(env, PRIV_VERSION_1_10_0); 260 } 261 262 static void rv64_sifive_e_cpu_init(Object *obj) 263 { 264 CPURISCVState *env = &RISCV_CPU(obj)->env; 265 RISCVCPU *cpu = RISCV_CPU(obj); 266 267 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 268 set_priv_version(env, PRIV_VERSION_1_10_0); 269 cpu->cfg.mmu = false; 270 } 271 272 static void rv128_base_cpu_init(Object *obj) 273 { 274 if (qemu_tcg_mttcg_enabled()) { 275 /* Missing 128-bit aligned atomics */ 276 error_report("128-bit RISC-V currently does not work with Multi " 277 "Threaded TCG. Please use: -accel tcg,thread=single"); 278 exit(EXIT_FAILURE); 279 } 280 CPURISCVState *env = &RISCV_CPU(obj)->env; 281 /* We set this in the realise function */ 282 set_misa(env, MXL_RV128, 0); 283 register_cpu_props(DEVICE(obj)); 284 /* Set latest version of privileged specification */ 285 set_priv_version(env, PRIV_VERSION_1_12_0); 286 } 287 #else 288 static void rv32_base_cpu_init(Object *obj) 289 { 290 CPURISCVState *env = &RISCV_CPU(obj)->env; 291 /* We set this in the realise function */ 292 set_misa(env, MXL_RV32, 0); 293 register_cpu_props(DEVICE(obj)); 294 /* Set latest version of privileged specification */ 295 set_priv_version(env, PRIV_VERSION_1_12_0); 296 } 297 298 static void rv32_sifive_u_cpu_init(Object *obj) 299 { 300 CPURISCVState *env = &RISCV_CPU(obj)->env; 301 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 302 set_priv_version(env, PRIV_VERSION_1_10_0); 303 } 304 305 static void rv32_sifive_e_cpu_init(Object *obj) 306 { 307 CPURISCVState *env = &RISCV_CPU(obj)->env; 308 RISCVCPU *cpu = RISCV_CPU(obj); 309 310 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 311 set_priv_version(env, PRIV_VERSION_1_10_0); 312 cpu->cfg.mmu = false; 313 } 314 315 static void rv32_ibex_cpu_init(Object *obj) 316 { 317 CPURISCVState *env = &RISCV_CPU(obj)->env; 318 RISCVCPU *cpu = RISCV_CPU(obj); 319 320 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 321 set_priv_version(env, PRIV_VERSION_1_11_0); 322 cpu->cfg.mmu = false; 323 cpu->cfg.epmp = true; 324 } 325 326 static void rv32_imafcu_nommu_cpu_init(Object *obj) 327 { 328 CPURISCVState *env = &RISCV_CPU(obj)->env; 329 RISCVCPU *cpu = RISCV_CPU(obj); 330 331 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 332 set_priv_version(env, PRIV_VERSION_1_10_0); 333 set_resetvec(env, DEFAULT_RSTVEC); 334 cpu->cfg.mmu = false; 335 } 336 #endif 337 338 #if defined(CONFIG_KVM) 339 static void riscv_host_cpu_init(Object *obj) 340 { 341 CPURISCVState *env = &RISCV_CPU(obj)->env; 342 #if defined(TARGET_RISCV32) 343 set_misa(env, MXL_RV32, 0); 344 #elif defined(TARGET_RISCV64) 345 set_misa(env, MXL_RV64, 0); 346 #endif 347 register_cpu_props(DEVICE(obj)); 348 } 349 #endif 350 351 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 352 { 353 ObjectClass *oc; 354 char *typename; 355 char **cpuname; 356 357 cpuname = g_strsplit(cpu_model, ",", 1); 358 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 359 oc = object_class_by_name(typename); 360 g_strfreev(cpuname); 361 g_free(typename); 362 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 363 object_class_is_abstract(oc)) { 364 return NULL; 365 } 366 return oc; 367 } 368 369 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 370 { 371 RISCVCPU *cpu = RISCV_CPU(cs); 372 CPURISCVState *env = &cpu->env; 373 int i; 374 375 #if !defined(CONFIG_USER_ONLY) 376 if (riscv_has_ext(env, RVH)) { 377 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 378 } 379 #endif 380 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 381 #ifndef CONFIG_USER_ONLY 382 { 383 static const int dump_csrs[] = { 384 CSR_MHARTID, 385 CSR_MSTATUS, 386 CSR_MSTATUSH, 387 CSR_HSTATUS, 388 CSR_VSSTATUS, 389 CSR_MIP, 390 CSR_MIE, 391 CSR_MIDELEG, 392 CSR_HIDELEG, 393 CSR_MEDELEG, 394 CSR_HEDELEG, 395 CSR_MTVEC, 396 CSR_STVEC, 397 CSR_VSTVEC, 398 CSR_MEPC, 399 CSR_SEPC, 400 CSR_VSEPC, 401 CSR_MCAUSE, 402 CSR_SCAUSE, 403 CSR_VSCAUSE, 404 CSR_MTVAL, 405 CSR_STVAL, 406 CSR_HTVAL, 407 CSR_MTVAL2, 408 CSR_MSCRATCH, 409 CSR_SSCRATCH, 410 CSR_SATP, 411 CSR_MMTE, 412 CSR_UPMBASE, 413 CSR_UPMMASK, 414 CSR_SPMBASE, 415 CSR_SPMMASK, 416 CSR_MPMBASE, 417 CSR_MPMMASK, 418 }; 419 420 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 421 int csrno = dump_csrs[i]; 422 target_ulong val = 0; 423 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 424 425 /* 426 * Rely on the smode, hmode, etc, predicates within csr.c 427 * to do the filtering of the registers that are present. 428 */ 429 if (res == RISCV_EXCP_NONE) { 430 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 431 csr_ops[csrno].name, val); 432 } 433 } 434 } 435 #endif 436 437 for (i = 0; i < 32; i++) { 438 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 439 riscv_int_regnames[i], env->gpr[i]); 440 if ((i & 3) == 3) { 441 qemu_fprintf(f, "\n"); 442 } 443 } 444 if (flags & CPU_DUMP_FPU) { 445 for (i = 0; i < 32; i++) { 446 qemu_fprintf(f, " %-8s %016" PRIx64, 447 riscv_fpr_regnames[i], env->fpr[i]); 448 if ((i & 3) == 3) { 449 qemu_fprintf(f, "\n"); 450 } 451 } 452 } 453 } 454 455 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 456 { 457 RISCVCPU *cpu = RISCV_CPU(cs); 458 CPURISCVState *env = &cpu->env; 459 460 if (env->xl == MXL_RV32) { 461 env->pc = (int32_t)value; 462 } else { 463 env->pc = value; 464 } 465 } 466 467 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 468 const TranslationBlock *tb) 469 { 470 RISCVCPU *cpu = RISCV_CPU(cs); 471 CPURISCVState *env = &cpu->env; 472 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 473 474 if (xl == MXL_RV32) { 475 env->pc = (int32_t)tb->pc; 476 } else { 477 env->pc = tb->pc; 478 } 479 } 480 481 static bool riscv_cpu_has_work(CPUState *cs) 482 { 483 #ifndef CONFIG_USER_ONLY 484 RISCVCPU *cpu = RISCV_CPU(cs); 485 CPURISCVState *env = &cpu->env; 486 /* 487 * Definition of the WFI instruction requires it to ignore the privilege 488 * mode and delegation registers, but respect individual enables 489 */ 490 return riscv_cpu_all_pending(env) != 0; 491 #else 492 return true; 493 #endif 494 } 495 496 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 497 target_ulong *data) 498 { 499 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 500 if (xl == MXL_RV32) { 501 env->pc = (int32_t)data[0]; 502 } else { 503 env->pc = data[0]; 504 } 505 env->bins = data[1]; 506 } 507 508 static void riscv_cpu_reset(DeviceState *dev) 509 { 510 #ifndef CONFIG_USER_ONLY 511 uint8_t iprio; 512 int i, irq, rdzero; 513 #endif 514 CPUState *cs = CPU(dev); 515 RISCVCPU *cpu = RISCV_CPU(cs); 516 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 517 CPURISCVState *env = &cpu->env; 518 519 mcc->parent_reset(dev); 520 #ifndef CONFIG_USER_ONLY 521 env->misa_mxl = env->misa_mxl_max; 522 env->priv = PRV_M; 523 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 524 if (env->misa_mxl > MXL_RV32) { 525 /* 526 * The reset status of SXL/UXL is undefined, but mstatus is WARL 527 * and we must ensure that the value after init is valid for read. 528 */ 529 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 530 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 531 if (riscv_has_ext(env, RVH)) { 532 env->vsstatus = set_field(env->vsstatus, 533 MSTATUS64_SXL, env->misa_mxl); 534 env->vsstatus = set_field(env->vsstatus, 535 MSTATUS64_UXL, env->misa_mxl); 536 env->mstatus_hs = set_field(env->mstatus_hs, 537 MSTATUS64_SXL, env->misa_mxl); 538 env->mstatus_hs = set_field(env->mstatus_hs, 539 MSTATUS64_UXL, env->misa_mxl); 540 } 541 } 542 env->mcause = 0; 543 env->miclaim = MIP_SGEIP; 544 env->pc = env->resetvec; 545 env->bins = 0; 546 env->two_stage_lookup = false; 547 548 /* Initialized default priorities of local interrupts. */ 549 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 550 iprio = riscv_cpu_default_priority(i); 551 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 552 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 553 env->hviprio[i] = 0; 554 } 555 i = 0; 556 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 557 if (!rdzero) { 558 env->hviprio[irq] = env->miprio[irq]; 559 } 560 i++; 561 } 562 /* mmte is supposed to have pm.current hardwired to 1 */ 563 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 564 #endif 565 env->xl = riscv_cpu_mxl(env); 566 riscv_cpu_update_mask(env); 567 cs->exception_index = RISCV_EXCP_NONE; 568 env->load_res = -1; 569 set_default_nan_mode(1, &env->fp_status); 570 571 #ifndef CONFIG_USER_ONLY 572 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 573 riscv_trigger_init(env); 574 } 575 576 if (kvm_enabled()) { 577 kvm_riscv_reset_vcpu(cpu); 578 } 579 #endif 580 } 581 582 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 583 { 584 RISCVCPU *cpu = RISCV_CPU(s); 585 586 switch (riscv_cpu_mxl(&cpu->env)) { 587 case MXL_RV32: 588 info->print_insn = print_insn_riscv32; 589 break; 590 case MXL_RV64: 591 info->print_insn = print_insn_riscv64; 592 break; 593 case MXL_RV128: 594 info->print_insn = print_insn_riscv128; 595 break; 596 default: 597 g_assert_not_reached(); 598 } 599 } 600 601 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 602 { 603 CPUState *cs = CPU(dev); 604 RISCVCPU *cpu = RISCV_CPU(dev); 605 CPURISCVState *env = &cpu->env; 606 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 607 CPUClass *cc = CPU_CLASS(mcc); 608 int i, priv_version = -1; 609 Error *local_err = NULL; 610 611 cpu_exec_realizefn(cs, &local_err); 612 if (local_err != NULL) { 613 error_propagate(errp, local_err); 614 return; 615 } 616 617 if (cpu->cfg.priv_spec) { 618 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 619 priv_version = PRIV_VERSION_1_12_0; 620 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 621 priv_version = PRIV_VERSION_1_11_0; 622 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 623 priv_version = PRIV_VERSION_1_10_0; 624 } else { 625 error_setg(errp, 626 "Unsupported privilege spec version '%s'", 627 cpu->cfg.priv_spec); 628 return; 629 } 630 } 631 632 if (priv_version >= PRIV_VERSION_1_10_0) { 633 set_priv_version(env, priv_version); 634 } 635 636 /* Force disable extensions if priv spec version does not match */ 637 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 638 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 639 (env->priv_ver < isa_edata_arr[i].min_version)) { 640 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 641 #ifndef CONFIG_USER_ONLY 642 warn_report("disabling %s extension for hart 0x%lx because " 643 "privilege spec version does not match", 644 isa_edata_arr[i].name, (unsigned long)env->mhartid); 645 #else 646 warn_report("disabling %s extension because " 647 "privilege spec version does not match", 648 isa_edata_arr[i].name); 649 #endif 650 } 651 } 652 653 if (cpu->cfg.mmu) { 654 riscv_set_feature(env, RISCV_FEATURE_MMU); 655 } 656 657 if (cpu->cfg.pmp) { 658 riscv_set_feature(env, RISCV_FEATURE_PMP); 659 660 /* 661 * Enhanced PMP should only be available 662 * on harts with PMP support 663 */ 664 if (cpu->cfg.epmp) { 665 riscv_set_feature(env, RISCV_FEATURE_EPMP); 666 } 667 } 668 669 if (cpu->cfg.aia) { 670 riscv_set_feature(env, RISCV_FEATURE_AIA); 671 } 672 673 if (cpu->cfg.debug) { 674 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 675 } 676 677 set_resetvec(env, cpu->cfg.resetvec); 678 679 /* Validate that MISA_MXL is set properly. */ 680 switch (env->misa_mxl_max) { 681 #ifdef TARGET_RISCV64 682 case MXL_RV64: 683 case MXL_RV128: 684 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 685 break; 686 #endif 687 case MXL_RV32: 688 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 689 break; 690 default: 691 g_assert_not_reached(); 692 } 693 assert(env->misa_mxl_max == env->misa_mxl); 694 695 /* If only MISA_EXT is unset for misa, then set it from properties */ 696 if (env->misa_ext == 0) { 697 uint32_t ext = 0; 698 699 /* Do some ISA extension error checking */ 700 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 701 cpu->cfg.ext_a && cpu->cfg.ext_f && 702 cpu->cfg.ext_d && 703 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 704 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 705 cpu->cfg.ext_i = true; 706 cpu->cfg.ext_m = true; 707 cpu->cfg.ext_a = true; 708 cpu->cfg.ext_f = true; 709 cpu->cfg.ext_d = true; 710 cpu->cfg.ext_icsr = true; 711 cpu->cfg.ext_ifencei = true; 712 } 713 714 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 715 error_setg(errp, 716 "I and E extensions are incompatible"); 717 return; 718 } 719 720 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 721 error_setg(errp, 722 "Either I or E extension must be set"); 723 return; 724 } 725 726 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 727 error_setg(errp, 728 "Setting S extension without U extension is illegal"); 729 return; 730 } 731 732 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { 733 error_setg(errp, 734 "H depends on an I base integer ISA with 32 x registers"); 735 return; 736 } 737 738 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 739 error_setg(errp, "H extension implicitly requires S-mode"); 740 return; 741 } 742 743 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 744 error_setg(errp, "F extension requires Zicsr"); 745 return; 746 } 747 748 if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { 749 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 750 return; 751 } 752 753 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 754 error_setg(errp, "D extension requires F extension"); 755 return; 756 } 757 758 if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { 759 error_setg(errp, "V extension requires D extension"); 760 return; 761 } 762 763 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 764 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 765 return; 766 } 767 768 /* Set the ISA extensions, checks should have happened above */ 769 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || 770 cpu->cfg.ext_zhinxmin) { 771 cpu->cfg.ext_zfinx = true; 772 } 773 774 if (cpu->cfg.ext_zfinx) { 775 if (!cpu->cfg.ext_icsr) { 776 error_setg(errp, "Zfinx extension requires Zicsr"); 777 return; 778 } 779 if (cpu->cfg.ext_f) { 780 error_setg(errp, 781 "Zfinx cannot be supported together with F extension"); 782 return; 783 } 784 } 785 786 if (cpu->cfg.ext_zk) { 787 cpu->cfg.ext_zkn = true; 788 cpu->cfg.ext_zkr = true; 789 cpu->cfg.ext_zkt = true; 790 } 791 792 if (cpu->cfg.ext_zkn) { 793 cpu->cfg.ext_zbkb = true; 794 cpu->cfg.ext_zbkc = true; 795 cpu->cfg.ext_zbkx = true; 796 cpu->cfg.ext_zkne = true; 797 cpu->cfg.ext_zknd = true; 798 cpu->cfg.ext_zknh = true; 799 } 800 801 if (cpu->cfg.ext_zks) { 802 cpu->cfg.ext_zbkb = true; 803 cpu->cfg.ext_zbkc = true; 804 cpu->cfg.ext_zbkx = true; 805 cpu->cfg.ext_zksed = true; 806 cpu->cfg.ext_zksh = true; 807 } 808 809 if (cpu->cfg.ext_i) { 810 ext |= RVI; 811 } 812 if (cpu->cfg.ext_e) { 813 ext |= RVE; 814 } 815 if (cpu->cfg.ext_m) { 816 ext |= RVM; 817 } 818 if (cpu->cfg.ext_a) { 819 ext |= RVA; 820 } 821 if (cpu->cfg.ext_f) { 822 ext |= RVF; 823 } 824 if (cpu->cfg.ext_d) { 825 ext |= RVD; 826 } 827 if (cpu->cfg.ext_c) { 828 ext |= RVC; 829 } 830 if (cpu->cfg.ext_s) { 831 ext |= RVS; 832 } 833 if (cpu->cfg.ext_u) { 834 ext |= RVU; 835 } 836 if (cpu->cfg.ext_h) { 837 ext |= RVH; 838 } 839 if (cpu->cfg.ext_v) { 840 int vext_version = VEXT_VERSION_1_00_0; 841 ext |= RVV; 842 if (!is_power_of_2(cpu->cfg.vlen)) { 843 error_setg(errp, 844 "Vector extension VLEN must be power of 2"); 845 return; 846 } 847 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 848 error_setg(errp, 849 "Vector extension implementation only supports VLEN " 850 "in the range [128, %d]", RV_VLEN_MAX); 851 return; 852 } 853 if (!is_power_of_2(cpu->cfg.elen)) { 854 error_setg(errp, 855 "Vector extension ELEN must be power of 2"); 856 return; 857 } 858 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 859 error_setg(errp, 860 "Vector extension implementation only supports ELEN " 861 "in the range [8, 64]"); 862 return; 863 } 864 if (cpu->cfg.vext_spec) { 865 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 866 vext_version = VEXT_VERSION_1_00_0; 867 } else { 868 error_setg(errp, 869 "Unsupported vector spec version '%s'", 870 cpu->cfg.vext_spec); 871 return; 872 } 873 } else { 874 qemu_log("vector version is not specified, " 875 "use the default value v1.0\n"); 876 } 877 set_vext_version(env, vext_version); 878 } 879 if (cpu->cfg.ext_j) { 880 ext |= RVJ; 881 } 882 883 set_misa(env, env->misa_mxl, ext); 884 } 885 886 riscv_cpu_register_gdb_regs_for_features(cs); 887 888 qemu_init_vcpu(cs); 889 cpu_reset(cs); 890 891 mcc->parent_realize(dev, errp); 892 } 893 894 #ifndef CONFIG_USER_ONLY 895 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 896 { 897 RISCVCPU *cpu = RISCV_CPU(opaque); 898 CPURISCVState *env = &cpu->env; 899 900 if (irq < IRQ_LOCAL_MAX) { 901 switch (irq) { 902 case IRQ_U_SOFT: 903 case IRQ_S_SOFT: 904 case IRQ_VS_SOFT: 905 case IRQ_M_SOFT: 906 case IRQ_U_TIMER: 907 case IRQ_S_TIMER: 908 case IRQ_VS_TIMER: 909 case IRQ_M_TIMER: 910 case IRQ_U_EXT: 911 case IRQ_VS_EXT: 912 case IRQ_M_EXT: 913 if (kvm_enabled()) { 914 kvm_riscv_set_irq(cpu, irq, level); 915 } else { 916 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 917 } 918 break; 919 case IRQ_S_EXT: 920 if (kvm_enabled()) { 921 kvm_riscv_set_irq(cpu, irq, level); 922 } else { 923 env->external_seip = level; 924 riscv_cpu_update_mip(cpu, 1 << irq, 925 BOOL_TO_MASK(level | env->software_seip)); 926 } 927 break; 928 default: 929 g_assert_not_reached(); 930 } 931 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 932 /* Require H-extension for handling guest local interrupts */ 933 if (!riscv_has_ext(env, RVH)) { 934 g_assert_not_reached(); 935 } 936 937 /* Compute bit position in HGEIP CSR */ 938 irq = irq - IRQ_LOCAL_MAX + 1; 939 if (env->geilen < irq) { 940 g_assert_not_reached(); 941 } 942 943 /* Update HGEIP CSR */ 944 env->hgeip &= ~((target_ulong)1 << irq); 945 if (level) { 946 env->hgeip |= (target_ulong)1 << irq; 947 } 948 949 /* Update mip.SGEIP bit */ 950 riscv_cpu_update_mip(cpu, MIP_SGEIP, 951 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 952 } else { 953 g_assert_not_reached(); 954 } 955 } 956 #endif /* CONFIG_USER_ONLY */ 957 958 static void riscv_cpu_init(Object *obj) 959 { 960 RISCVCPU *cpu = RISCV_CPU(obj); 961 962 cpu->cfg.ext_ifencei = true; 963 cpu->cfg.ext_icsr = true; 964 cpu->cfg.mmu = true; 965 cpu->cfg.pmp = true; 966 967 cpu_set_cpustate_pointers(cpu); 968 969 #ifndef CONFIG_USER_ONLY 970 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 971 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 972 #endif /* CONFIG_USER_ONLY */ 973 } 974 975 static Property riscv_cpu_extensions[] = { 976 /* Defaults for standard extensions */ 977 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 978 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 979 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 980 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 981 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 982 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 983 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 984 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 985 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 986 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 987 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 988 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 989 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 990 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 991 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 992 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 993 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 994 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 995 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 996 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 997 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 998 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 999 1000 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1001 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1002 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1003 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1004 1005 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1006 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1007 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1008 1009 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1010 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1011 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1012 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1013 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1014 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1015 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1016 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1017 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1018 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1019 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1020 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1021 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1022 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1023 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1024 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1025 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1026 1027 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1028 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1029 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1030 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1031 1032 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1033 1034 /* Vendor-specific custom extensions */ 1035 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1036 1037 /* These are experimental so mark with 'x-' */ 1038 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1039 /* ePMP 0.9.3 */ 1040 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1041 DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), 1042 1043 DEFINE_PROP_END_OF_LIST(), 1044 }; 1045 1046 static void register_cpu_props(DeviceState *dev) 1047 { 1048 Property *prop; 1049 1050 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1051 qdev_property_add_static(dev, prop); 1052 } 1053 } 1054 1055 static Property riscv_cpu_properties[] = { 1056 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1057 1058 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1059 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1060 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1061 1062 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 1063 1064 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1065 1066 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1067 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1068 DEFINE_PROP_END_OF_LIST(), 1069 }; 1070 1071 static gchar *riscv_gdb_arch_name(CPUState *cs) 1072 { 1073 RISCVCPU *cpu = RISCV_CPU(cs); 1074 CPURISCVState *env = &cpu->env; 1075 1076 switch (riscv_cpu_mxl(env)) { 1077 case MXL_RV32: 1078 return g_strdup("riscv:rv32"); 1079 case MXL_RV64: 1080 case MXL_RV128: 1081 return g_strdup("riscv:rv64"); 1082 default: 1083 g_assert_not_reached(); 1084 } 1085 } 1086 1087 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1088 { 1089 RISCVCPU *cpu = RISCV_CPU(cs); 1090 1091 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1092 return cpu->dyn_csr_xml; 1093 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1094 return cpu->dyn_vreg_xml; 1095 } 1096 1097 return NULL; 1098 } 1099 1100 #ifndef CONFIG_USER_ONLY 1101 #include "hw/core/sysemu-cpu-ops.h" 1102 1103 static const struct SysemuCPUOps riscv_sysemu_ops = { 1104 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1105 .write_elf64_note = riscv_cpu_write_elf64_note, 1106 .write_elf32_note = riscv_cpu_write_elf32_note, 1107 .legacy_vmsd = &vmstate_riscv_cpu, 1108 }; 1109 #endif 1110 1111 #include "hw/core/tcg-cpu-ops.h" 1112 1113 static const struct TCGCPUOps riscv_tcg_ops = { 1114 .initialize = riscv_translate_init, 1115 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1116 1117 #ifndef CONFIG_USER_ONLY 1118 .tlb_fill = riscv_cpu_tlb_fill, 1119 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1120 .do_interrupt = riscv_cpu_do_interrupt, 1121 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1122 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1123 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1124 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1125 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1126 #endif /* !CONFIG_USER_ONLY */ 1127 }; 1128 1129 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1130 { 1131 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1132 CPUClass *cc = CPU_CLASS(c); 1133 DeviceClass *dc = DEVICE_CLASS(c); 1134 1135 device_class_set_parent_realize(dc, riscv_cpu_realize, 1136 &mcc->parent_realize); 1137 1138 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 1139 1140 cc->class_by_name = riscv_cpu_class_by_name; 1141 cc->has_work = riscv_cpu_has_work; 1142 cc->dump_state = riscv_cpu_dump_state; 1143 cc->set_pc = riscv_cpu_set_pc; 1144 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1145 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1146 cc->gdb_num_core_regs = 33; 1147 cc->gdb_stop_before_watchpoint = true; 1148 cc->disas_set_info = riscv_cpu_disas_set_info; 1149 #ifndef CONFIG_USER_ONLY 1150 cc->sysemu_ops = &riscv_sysemu_ops; 1151 #endif 1152 cc->gdb_arch_name = riscv_gdb_arch_name; 1153 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1154 cc->tcg_ops = &riscv_tcg_ops; 1155 1156 device_class_set_props(dc, riscv_cpu_properties); 1157 } 1158 1159 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1160 { 1161 char *old = *isa_str; 1162 char *new = *isa_str; 1163 int i; 1164 1165 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1166 if (isa_edata_arr[i].multi_letter && 1167 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1168 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1169 g_free(old); 1170 old = new; 1171 } 1172 } 1173 1174 *isa_str = new; 1175 } 1176 1177 char *riscv_isa_string(RISCVCPU *cpu) 1178 { 1179 int i; 1180 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1181 char *isa_str = g_new(char, maxlen); 1182 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1183 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1184 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1185 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1186 } 1187 } 1188 *p = '\0'; 1189 if (!cpu->cfg.short_isa_string) { 1190 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1191 } 1192 return isa_str; 1193 } 1194 1195 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1196 { 1197 ObjectClass *class_a = (ObjectClass *)a; 1198 ObjectClass *class_b = (ObjectClass *)b; 1199 const char *name_a, *name_b; 1200 1201 name_a = object_class_get_name(class_a); 1202 name_b = object_class_get_name(class_b); 1203 return strcmp(name_a, name_b); 1204 } 1205 1206 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1207 { 1208 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1209 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1210 1211 qemu_printf("%.*s\n", len, typename); 1212 } 1213 1214 void riscv_cpu_list(void) 1215 { 1216 GSList *list; 1217 1218 list = object_class_get_list(TYPE_RISCV_CPU, false); 1219 list = g_slist_sort(list, riscv_cpu_list_compare); 1220 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1221 g_slist_free(list); 1222 } 1223 1224 #define DEFINE_CPU(type_name, initfn) \ 1225 { \ 1226 .name = type_name, \ 1227 .parent = TYPE_RISCV_CPU, \ 1228 .instance_init = initfn \ 1229 } 1230 1231 static const TypeInfo riscv_cpu_type_infos[] = { 1232 { 1233 .name = TYPE_RISCV_CPU, 1234 .parent = TYPE_CPU, 1235 .instance_size = sizeof(RISCVCPU), 1236 .instance_align = __alignof__(RISCVCPU), 1237 .instance_init = riscv_cpu_init, 1238 .abstract = true, 1239 .class_size = sizeof(RISCVCPUClass), 1240 .class_init = riscv_cpu_class_init, 1241 }, 1242 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1243 #if defined(CONFIG_KVM) 1244 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1245 #endif 1246 #if defined(TARGET_RISCV32) 1247 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1248 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1249 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1250 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1251 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1252 #elif defined(TARGET_RISCV64) 1253 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1254 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1255 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1256 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1257 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1258 #endif 1259 }; 1260 1261 DEFINE_TYPES(riscv_cpu_type_infos) 1262