1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "exec/exec-all.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "fpu/softfloat-helpers.h" 32 33 /* RISC-V CPU definitions */ 34 35 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 36 37 const char * const riscv_int_regnames[] = { 38 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 39 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 40 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 41 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 42 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 43 }; 44 45 const char * const riscv_fpr_regnames[] = { 46 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 47 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 48 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 49 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 50 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 51 "f30/ft10", "f31/ft11" 52 }; 53 54 static const char * const riscv_excp_names[] = { 55 "misaligned_fetch", 56 "fault_fetch", 57 "illegal_instruction", 58 "breakpoint", 59 "misaligned_load", 60 "fault_load", 61 "misaligned_store", 62 "fault_store", 63 "user_ecall", 64 "supervisor_ecall", 65 "hypervisor_ecall", 66 "machine_ecall", 67 "exec_page_fault", 68 "load_page_fault", 69 "reserved", 70 "store_page_fault", 71 "reserved", 72 "reserved", 73 "reserved", 74 "reserved", 75 "guest_exec_page_fault", 76 "guest_load_page_fault", 77 "reserved", 78 "guest_store_page_fault", 79 }; 80 81 static const char * const riscv_intr_names[] = { 82 "u_software", 83 "s_software", 84 "vs_software", 85 "m_software", 86 "u_timer", 87 "s_timer", 88 "vs_timer", 89 "m_timer", 90 "u_external", 91 "s_external", 92 "vs_external", 93 "m_external", 94 "reserved", 95 "reserved", 96 "reserved", 97 "reserved" 98 }; 99 100 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 101 { 102 if (async) { 103 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 104 riscv_intr_names[cause] : "(unknown)"; 105 } else { 106 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 107 riscv_excp_names[cause] : "(unknown)"; 108 } 109 } 110 111 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 112 { 113 env->misa_mxl_max = env->misa_mxl = mxl; 114 env->misa_ext_mask = env->misa_ext = ext; 115 } 116 117 static void set_priv_version(CPURISCVState *env, int priv_ver) 118 { 119 env->priv_ver = priv_ver; 120 } 121 122 static void set_vext_version(CPURISCVState *env, int vext_ver) 123 { 124 env->vext_ver = vext_ver; 125 } 126 127 static void set_feature(CPURISCVState *env, int feature) 128 { 129 env->features |= (1ULL << feature); 130 } 131 132 static void set_resetvec(CPURISCVState *env, target_ulong resetvec) 133 { 134 #ifndef CONFIG_USER_ONLY 135 env->resetvec = resetvec; 136 #endif 137 } 138 139 static void riscv_any_cpu_init(Object *obj) 140 { 141 CPURISCVState *env = &RISCV_CPU(obj)->env; 142 #if defined(TARGET_RISCV32) 143 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 144 #elif defined(TARGET_RISCV64) 145 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 146 #endif 147 set_priv_version(env, PRIV_VERSION_1_11_0); 148 } 149 150 #if defined(TARGET_RISCV64) 151 static void rv64_base_cpu_init(Object *obj) 152 { 153 CPURISCVState *env = &RISCV_CPU(obj)->env; 154 /* We set this in the realise function */ 155 set_misa(env, MXL_RV64, 0); 156 } 157 158 static void rv64_sifive_u_cpu_init(Object *obj) 159 { 160 CPURISCVState *env = &RISCV_CPU(obj)->env; 161 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 162 set_priv_version(env, PRIV_VERSION_1_10_0); 163 } 164 165 static void rv64_sifive_e_cpu_init(Object *obj) 166 { 167 CPURISCVState *env = &RISCV_CPU(obj)->env; 168 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 169 set_priv_version(env, PRIV_VERSION_1_10_0); 170 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 171 } 172 #else 173 static void rv32_base_cpu_init(Object *obj) 174 { 175 CPURISCVState *env = &RISCV_CPU(obj)->env; 176 /* We set this in the realise function */ 177 set_misa(env, MXL_RV32, 0); 178 } 179 180 static void rv32_sifive_u_cpu_init(Object *obj) 181 { 182 CPURISCVState *env = &RISCV_CPU(obj)->env; 183 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 184 set_priv_version(env, PRIV_VERSION_1_10_0); 185 } 186 187 static void rv32_sifive_e_cpu_init(Object *obj) 188 { 189 CPURISCVState *env = &RISCV_CPU(obj)->env; 190 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 191 set_priv_version(env, PRIV_VERSION_1_10_0); 192 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 193 } 194 195 static void rv32_ibex_cpu_init(Object *obj) 196 { 197 CPURISCVState *env = &RISCV_CPU(obj)->env; 198 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 199 set_priv_version(env, PRIV_VERSION_1_10_0); 200 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 201 qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); 202 } 203 204 static void rv32_imafcu_nommu_cpu_init(Object *obj) 205 { 206 CPURISCVState *env = &RISCV_CPU(obj)->env; 207 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 208 set_priv_version(env, PRIV_VERSION_1_10_0); 209 set_resetvec(env, DEFAULT_RSTVEC); 210 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 211 } 212 #endif 213 214 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 215 { 216 ObjectClass *oc; 217 char *typename; 218 char **cpuname; 219 220 cpuname = g_strsplit(cpu_model, ",", 1); 221 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 222 oc = object_class_by_name(typename); 223 g_strfreev(cpuname); 224 g_free(typename); 225 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 226 object_class_is_abstract(oc)) { 227 return NULL; 228 } 229 return oc; 230 } 231 232 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 233 { 234 RISCVCPU *cpu = RISCV_CPU(cs); 235 CPURISCVState *env = &cpu->env; 236 int i; 237 238 #if !defined(CONFIG_USER_ONLY) 239 if (riscv_has_ext(env, RVH)) { 240 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 241 } 242 #endif 243 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 244 #ifndef CONFIG_USER_ONLY 245 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); 246 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); 247 if (riscv_cpu_mxl(env) == MXL_RV32) { 248 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", 249 (target_ulong)(env->mstatus >> 32)); 250 } 251 if (riscv_has_ext(env, RVH)) { 252 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); 253 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus", 254 (target_ulong)env->vsstatus); 255 } 256 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); 257 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); 258 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); 259 if (riscv_has_ext(env, RVH)) { 260 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); 261 } 262 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); 263 if (riscv_has_ext(env, RVH)) { 264 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); 265 } 266 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); 267 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); 268 if (riscv_has_ext(env, RVH)) { 269 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); 270 } 271 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); 272 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); 273 if (riscv_has_ext(env, RVH)) { 274 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); 275 } 276 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); 277 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); 278 if (riscv_has_ext(env, RVH)) { 279 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); 280 } 281 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); 282 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); 283 if (riscv_has_ext(env, RVH)) { 284 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); 285 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); 286 } 287 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch); 288 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch); 289 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); 290 #endif 291 292 for (i = 0; i < 32; i++) { 293 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 294 riscv_int_regnames[i], env->gpr[i]); 295 if ((i & 3) == 3) { 296 qemu_fprintf(f, "\n"); 297 } 298 } 299 if (flags & CPU_DUMP_FPU) { 300 for (i = 0; i < 32; i++) { 301 qemu_fprintf(f, " %-8s %016" PRIx64, 302 riscv_fpr_regnames[i], env->fpr[i]); 303 if ((i & 3) == 3) { 304 qemu_fprintf(f, "\n"); 305 } 306 } 307 } 308 } 309 310 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 311 { 312 RISCVCPU *cpu = RISCV_CPU(cs); 313 CPURISCVState *env = &cpu->env; 314 env->pc = value; 315 } 316 317 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 318 const TranslationBlock *tb) 319 { 320 RISCVCPU *cpu = RISCV_CPU(cs); 321 CPURISCVState *env = &cpu->env; 322 env->pc = tb->pc; 323 } 324 325 static bool riscv_cpu_has_work(CPUState *cs) 326 { 327 #ifndef CONFIG_USER_ONLY 328 RISCVCPU *cpu = RISCV_CPU(cs); 329 CPURISCVState *env = &cpu->env; 330 /* 331 * Definition of the WFI instruction requires it to ignore the privilege 332 * mode and delegation registers, but respect individual enables 333 */ 334 return (env->mip & env->mie) != 0; 335 #else 336 return true; 337 #endif 338 } 339 340 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 341 target_ulong *data) 342 { 343 env->pc = data[0]; 344 } 345 346 static void riscv_cpu_reset(DeviceState *dev) 347 { 348 CPUState *cs = CPU(dev); 349 RISCVCPU *cpu = RISCV_CPU(cs); 350 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 351 CPURISCVState *env = &cpu->env; 352 353 mcc->parent_reset(dev); 354 #ifndef CONFIG_USER_ONLY 355 env->misa_mxl = env->misa_mxl_max; 356 env->priv = PRV_M; 357 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 358 env->mcause = 0; 359 env->pc = env->resetvec; 360 env->two_stage_lookup = false; 361 #endif 362 cs->exception_index = RISCV_EXCP_NONE; 363 env->load_res = -1; 364 set_default_nan_mode(1, &env->fp_status); 365 } 366 367 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 368 { 369 RISCVCPU *cpu = RISCV_CPU(s); 370 371 switch (riscv_cpu_mxl(&cpu->env)) { 372 case MXL_RV32: 373 info->print_insn = print_insn_riscv32; 374 break; 375 case MXL_RV64: 376 info->print_insn = print_insn_riscv64; 377 break; 378 default: 379 g_assert_not_reached(); 380 } 381 } 382 383 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 384 { 385 CPUState *cs = CPU(dev); 386 RISCVCPU *cpu = RISCV_CPU(dev); 387 CPURISCVState *env = &cpu->env; 388 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 389 int priv_version = 0; 390 Error *local_err = NULL; 391 392 cpu_exec_realizefn(cs, &local_err); 393 if (local_err != NULL) { 394 error_propagate(errp, local_err); 395 return; 396 } 397 398 if (cpu->cfg.priv_spec) { 399 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 400 priv_version = PRIV_VERSION_1_11_0; 401 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 402 priv_version = PRIV_VERSION_1_10_0; 403 } else { 404 error_setg(errp, 405 "Unsupported privilege spec version '%s'", 406 cpu->cfg.priv_spec); 407 return; 408 } 409 } 410 411 if (priv_version) { 412 set_priv_version(env, priv_version); 413 } else if (!env->priv_ver) { 414 set_priv_version(env, PRIV_VERSION_1_11_0); 415 } 416 417 if (cpu->cfg.mmu) { 418 set_feature(env, RISCV_FEATURE_MMU); 419 } 420 421 if (cpu->cfg.pmp) { 422 set_feature(env, RISCV_FEATURE_PMP); 423 424 /* 425 * Enhanced PMP should only be available 426 * on harts with PMP support 427 */ 428 if (cpu->cfg.epmp) { 429 set_feature(env, RISCV_FEATURE_EPMP); 430 } 431 } 432 433 set_resetvec(env, cpu->cfg.resetvec); 434 435 /* Validate that MISA_MXL is set properly. */ 436 switch (env->misa_mxl_max) { 437 #ifdef TARGET_RISCV64 438 case MXL_RV64: 439 break; 440 #endif 441 case MXL_RV32: 442 break; 443 default: 444 g_assert_not_reached(); 445 } 446 assert(env->misa_mxl_max == env->misa_mxl); 447 448 /* If only MISA_EXT is unset for misa, then set it from properties */ 449 if (env->misa_ext == 0) { 450 uint32_t ext = 0; 451 452 /* Do some ISA extension error checking */ 453 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 454 error_setg(errp, 455 "I and E extensions are incompatible"); 456 return; 457 } 458 459 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 460 error_setg(errp, 461 "Either I or E extension must be set"); 462 return; 463 } 464 465 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 466 cpu->cfg.ext_a & cpu->cfg.ext_f & 467 cpu->cfg.ext_d)) { 468 warn_report("Setting G will also set IMAFD"); 469 cpu->cfg.ext_i = true; 470 cpu->cfg.ext_m = true; 471 cpu->cfg.ext_a = true; 472 cpu->cfg.ext_f = true; 473 cpu->cfg.ext_d = true; 474 } 475 476 /* Set the ISA extensions, checks should have happened above */ 477 if (cpu->cfg.ext_i) { 478 ext |= RVI; 479 } 480 if (cpu->cfg.ext_e) { 481 ext |= RVE; 482 } 483 if (cpu->cfg.ext_m) { 484 ext |= RVM; 485 } 486 if (cpu->cfg.ext_a) { 487 ext |= RVA; 488 } 489 if (cpu->cfg.ext_f) { 490 ext |= RVF; 491 } 492 if (cpu->cfg.ext_d) { 493 ext |= RVD; 494 } 495 if (cpu->cfg.ext_c) { 496 ext |= RVC; 497 } 498 if (cpu->cfg.ext_s) { 499 ext |= RVS; 500 } 501 if (cpu->cfg.ext_u) { 502 ext |= RVU; 503 } 504 if (cpu->cfg.ext_h) { 505 ext |= RVH; 506 } 507 if (cpu->cfg.ext_v) { 508 int vext_version = VEXT_VERSION_0_07_1; 509 ext |= RVV; 510 if (!is_power_of_2(cpu->cfg.vlen)) { 511 error_setg(errp, 512 "Vector extension VLEN must be power of 2"); 513 return; 514 } 515 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 516 error_setg(errp, 517 "Vector extension implementation only supports VLEN " 518 "in the range [128, %d]", RV_VLEN_MAX); 519 return; 520 } 521 if (!is_power_of_2(cpu->cfg.elen)) { 522 error_setg(errp, 523 "Vector extension ELEN must be power of 2"); 524 return; 525 } 526 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 527 error_setg(errp, 528 "Vector extension implementation only supports ELEN " 529 "in the range [8, 64]"); 530 return; 531 } 532 if (cpu->cfg.vext_spec) { 533 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { 534 vext_version = VEXT_VERSION_0_07_1; 535 } else { 536 error_setg(errp, 537 "Unsupported vector spec version '%s'", 538 cpu->cfg.vext_spec); 539 return; 540 } 541 } else { 542 qemu_log("vector version is not specified, " 543 "use the default value v0.7.1\n"); 544 } 545 set_vext_version(env, vext_version); 546 } 547 548 set_misa(env, env->misa_mxl, ext); 549 } 550 551 riscv_cpu_register_gdb_regs_for_features(cs); 552 553 qemu_init_vcpu(cs); 554 cpu_reset(cs); 555 556 mcc->parent_realize(dev, errp); 557 } 558 559 #ifndef CONFIG_USER_ONLY 560 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 561 { 562 RISCVCPU *cpu = RISCV_CPU(opaque); 563 564 switch (irq) { 565 case IRQ_U_SOFT: 566 case IRQ_S_SOFT: 567 case IRQ_VS_SOFT: 568 case IRQ_M_SOFT: 569 case IRQ_U_TIMER: 570 case IRQ_S_TIMER: 571 case IRQ_VS_TIMER: 572 case IRQ_M_TIMER: 573 case IRQ_U_EXT: 574 case IRQ_S_EXT: 575 case IRQ_VS_EXT: 576 case IRQ_M_EXT: 577 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 578 break; 579 default: 580 g_assert_not_reached(); 581 } 582 } 583 #endif /* CONFIG_USER_ONLY */ 584 585 static void riscv_cpu_init(Object *obj) 586 { 587 RISCVCPU *cpu = RISCV_CPU(obj); 588 589 cpu_set_cpustate_pointers(cpu); 590 591 #ifndef CONFIG_USER_ONLY 592 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); 593 #endif /* CONFIG_USER_ONLY */ 594 } 595 596 static Property riscv_cpu_properties[] = { 597 /* Defaults for standard extensions */ 598 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 599 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 600 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 601 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 602 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 603 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 604 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 605 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 606 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 607 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 608 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 609 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 610 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 611 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 612 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 613 614 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 615 616 /* These are experimental so mark with 'x-' */ 617 DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), 618 DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), 619 DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), 620 DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), 621 DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), 622 DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), 623 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 624 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 625 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 626 /* ePMP 0.9.3 */ 627 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 628 629 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 630 DEFINE_PROP_END_OF_LIST(), 631 }; 632 633 static gchar *riscv_gdb_arch_name(CPUState *cs) 634 { 635 RISCVCPU *cpu = RISCV_CPU(cs); 636 CPURISCVState *env = &cpu->env; 637 638 switch (riscv_cpu_mxl(env)) { 639 case MXL_RV32: 640 return g_strdup("riscv:rv32"); 641 case MXL_RV64: 642 return g_strdup("riscv:rv64"); 643 default: 644 g_assert_not_reached(); 645 } 646 } 647 648 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 649 { 650 RISCVCPU *cpu = RISCV_CPU(cs); 651 652 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 653 return cpu->dyn_csr_xml; 654 } 655 656 return NULL; 657 } 658 659 #ifndef CONFIG_USER_ONLY 660 #include "hw/core/sysemu-cpu-ops.h" 661 662 static const struct SysemuCPUOps riscv_sysemu_ops = { 663 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 664 .write_elf64_note = riscv_cpu_write_elf64_note, 665 .write_elf32_note = riscv_cpu_write_elf32_note, 666 .legacy_vmsd = &vmstate_riscv_cpu, 667 }; 668 #endif 669 670 #include "hw/core/tcg-cpu-ops.h" 671 672 static const struct TCGCPUOps riscv_tcg_ops = { 673 .initialize = riscv_translate_init, 674 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 675 .tlb_fill = riscv_cpu_tlb_fill, 676 677 #ifndef CONFIG_USER_ONLY 678 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 679 .do_interrupt = riscv_cpu_do_interrupt, 680 .do_transaction_failed = riscv_cpu_do_transaction_failed, 681 .do_unaligned_access = riscv_cpu_do_unaligned_access, 682 #endif /* !CONFIG_USER_ONLY */ 683 }; 684 685 static void riscv_cpu_class_init(ObjectClass *c, void *data) 686 { 687 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 688 CPUClass *cc = CPU_CLASS(c); 689 DeviceClass *dc = DEVICE_CLASS(c); 690 691 device_class_set_parent_realize(dc, riscv_cpu_realize, 692 &mcc->parent_realize); 693 694 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 695 696 cc->class_by_name = riscv_cpu_class_by_name; 697 cc->has_work = riscv_cpu_has_work; 698 cc->dump_state = riscv_cpu_dump_state; 699 cc->set_pc = riscv_cpu_set_pc; 700 cc->gdb_read_register = riscv_cpu_gdb_read_register; 701 cc->gdb_write_register = riscv_cpu_gdb_write_register; 702 cc->gdb_num_core_regs = 33; 703 #if defined(TARGET_RISCV32) 704 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 705 #elif defined(TARGET_RISCV64) 706 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 707 #endif 708 cc->gdb_stop_before_watchpoint = true; 709 cc->disas_set_info = riscv_cpu_disas_set_info; 710 #ifndef CONFIG_USER_ONLY 711 cc->sysemu_ops = &riscv_sysemu_ops; 712 #endif 713 cc->gdb_arch_name = riscv_gdb_arch_name; 714 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 715 cc->tcg_ops = &riscv_tcg_ops; 716 717 device_class_set_props(dc, riscv_cpu_properties); 718 } 719 720 char *riscv_isa_string(RISCVCPU *cpu) 721 { 722 int i; 723 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 724 char *isa_str = g_new(char, maxlen); 725 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 726 for (i = 0; i < sizeof(riscv_exts); i++) { 727 if (cpu->env.misa_ext & RV(riscv_exts[i])) { 728 *p++ = qemu_tolower(riscv_exts[i]); 729 } 730 } 731 *p = '\0'; 732 return isa_str; 733 } 734 735 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 736 { 737 ObjectClass *class_a = (ObjectClass *)a; 738 ObjectClass *class_b = (ObjectClass *)b; 739 const char *name_a, *name_b; 740 741 name_a = object_class_get_name(class_a); 742 name_b = object_class_get_name(class_b); 743 return strcmp(name_a, name_b); 744 } 745 746 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 747 { 748 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 749 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 750 751 qemu_printf("%.*s\n", len, typename); 752 } 753 754 void riscv_cpu_list(void) 755 { 756 GSList *list; 757 758 list = object_class_get_list(TYPE_RISCV_CPU, false); 759 list = g_slist_sort(list, riscv_cpu_list_compare); 760 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 761 g_slist_free(list); 762 } 763 764 #define DEFINE_CPU(type_name, initfn) \ 765 { \ 766 .name = type_name, \ 767 .parent = TYPE_RISCV_CPU, \ 768 .instance_init = initfn \ 769 } 770 771 static const TypeInfo riscv_cpu_type_infos[] = { 772 { 773 .name = TYPE_RISCV_CPU, 774 .parent = TYPE_CPU, 775 .instance_size = sizeof(RISCVCPU), 776 .instance_align = __alignof__(RISCVCPU), 777 .instance_init = riscv_cpu_init, 778 .abstract = true, 779 .class_size = sizeof(RISCVCPUClass), 780 .class_init = riscv_cpu_class_init, 781 }, 782 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 783 #if defined(TARGET_RISCV32) 784 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 785 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 786 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 787 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 788 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 789 #elif defined(TARGET_RISCV64) 790 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 791 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 792 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 793 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 794 #endif 795 }; 796 797 DEFINE_TYPES(riscv_cpu_type_infos) 798