1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "exec/exec-all.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "fpu/softfloat-helpers.h" 32 #include "sysemu/kvm.h" 33 #include "kvm_riscv.h" 34 35 /* RISC-V CPU definitions */ 36 37 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 38 (QEMU_VERSION_MINOR << 8) | \ 39 (QEMU_VERSION_MICRO)) 40 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 41 42 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 43 44 struct isa_ext_data { 45 const char *name; 46 bool enabled; 47 }; 48 49 const char * const riscv_int_regnames[] = { 50 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 51 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 52 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 53 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 54 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 55 }; 56 57 const char * const riscv_int_regnamesh[] = { 58 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 59 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 60 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 61 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 62 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 63 "x30h/t5h", "x31h/t6h" 64 }; 65 66 const char * const riscv_fpr_regnames[] = { 67 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 68 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 69 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 70 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 71 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 72 "f30/ft10", "f31/ft11" 73 }; 74 75 static const char * const riscv_excp_names[] = { 76 "misaligned_fetch", 77 "fault_fetch", 78 "illegal_instruction", 79 "breakpoint", 80 "misaligned_load", 81 "fault_load", 82 "misaligned_store", 83 "fault_store", 84 "user_ecall", 85 "supervisor_ecall", 86 "hypervisor_ecall", 87 "machine_ecall", 88 "exec_page_fault", 89 "load_page_fault", 90 "reserved", 91 "store_page_fault", 92 "reserved", 93 "reserved", 94 "reserved", 95 "reserved", 96 "guest_exec_page_fault", 97 "guest_load_page_fault", 98 "reserved", 99 "guest_store_page_fault", 100 }; 101 102 static const char * const riscv_intr_names[] = { 103 "u_software", 104 "s_software", 105 "vs_software", 106 "m_software", 107 "u_timer", 108 "s_timer", 109 "vs_timer", 110 "m_timer", 111 "u_external", 112 "s_external", 113 "vs_external", 114 "m_external", 115 "reserved", 116 "reserved", 117 "reserved", 118 "reserved" 119 }; 120 121 static void register_cpu_props(DeviceState *dev); 122 123 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 124 { 125 if (async) { 126 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 127 riscv_intr_names[cause] : "(unknown)"; 128 } else { 129 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 130 riscv_excp_names[cause] : "(unknown)"; 131 } 132 } 133 134 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 135 { 136 env->misa_mxl_max = env->misa_mxl = mxl; 137 env->misa_ext_mask = env->misa_ext = ext; 138 } 139 140 static void set_priv_version(CPURISCVState *env, int priv_ver) 141 { 142 env->priv_ver = priv_ver; 143 } 144 145 static void set_vext_version(CPURISCVState *env, int vext_ver) 146 { 147 env->vext_ver = vext_ver; 148 } 149 150 static void set_resetvec(CPURISCVState *env, target_ulong resetvec) 151 { 152 #ifndef CONFIG_USER_ONLY 153 env->resetvec = resetvec; 154 #endif 155 } 156 157 static void riscv_any_cpu_init(Object *obj) 158 { 159 CPURISCVState *env = &RISCV_CPU(obj)->env; 160 #if defined(TARGET_RISCV32) 161 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 162 #elif defined(TARGET_RISCV64) 163 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 164 #endif 165 set_priv_version(env, PRIV_VERSION_1_12_0); 166 register_cpu_props(DEVICE(obj)); 167 } 168 169 #if defined(TARGET_RISCV64) 170 static void rv64_base_cpu_init(Object *obj) 171 { 172 CPURISCVState *env = &RISCV_CPU(obj)->env; 173 /* We set this in the realise function */ 174 set_misa(env, MXL_RV64, 0); 175 register_cpu_props(DEVICE(obj)); 176 } 177 178 static void rv64_sifive_u_cpu_init(Object *obj) 179 { 180 CPURISCVState *env = &RISCV_CPU(obj)->env; 181 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 182 set_priv_version(env, PRIV_VERSION_1_10_0); 183 } 184 185 static void rv64_sifive_e_cpu_init(Object *obj) 186 { 187 CPURISCVState *env = &RISCV_CPU(obj)->env; 188 RISCVCPU *cpu = RISCV_CPU(obj); 189 190 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 191 set_priv_version(env, PRIV_VERSION_1_10_0); 192 cpu->cfg.mmu = false; 193 } 194 195 static void rv128_base_cpu_init(Object *obj) 196 { 197 if (qemu_tcg_mttcg_enabled()) { 198 /* Missing 128-bit aligned atomics */ 199 error_report("128-bit RISC-V currently does not work with Multi " 200 "Threaded TCG. Please use: -accel tcg,thread=single"); 201 exit(EXIT_FAILURE); 202 } 203 CPURISCVState *env = &RISCV_CPU(obj)->env; 204 /* We set this in the realise function */ 205 set_misa(env, MXL_RV128, 0); 206 register_cpu_props(DEVICE(obj)); 207 } 208 #else 209 static void rv32_base_cpu_init(Object *obj) 210 { 211 CPURISCVState *env = &RISCV_CPU(obj)->env; 212 /* We set this in the realise function */ 213 set_misa(env, MXL_RV32, 0); 214 register_cpu_props(DEVICE(obj)); 215 } 216 217 static void rv32_sifive_u_cpu_init(Object *obj) 218 { 219 CPURISCVState *env = &RISCV_CPU(obj)->env; 220 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 221 set_priv_version(env, PRIV_VERSION_1_10_0); 222 } 223 224 static void rv32_sifive_e_cpu_init(Object *obj) 225 { 226 CPURISCVState *env = &RISCV_CPU(obj)->env; 227 RISCVCPU *cpu = RISCV_CPU(obj); 228 229 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 230 set_priv_version(env, PRIV_VERSION_1_10_0); 231 cpu->cfg.mmu = false; 232 } 233 234 static void rv32_ibex_cpu_init(Object *obj) 235 { 236 CPURISCVState *env = &RISCV_CPU(obj)->env; 237 RISCVCPU *cpu = RISCV_CPU(obj); 238 239 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 240 set_priv_version(env, PRIV_VERSION_1_10_0); 241 cpu->cfg.mmu = false; 242 cpu->cfg.epmp = true; 243 } 244 245 static void rv32_imafcu_nommu_cpu_init(Object *obj) 246 { 247 CPURISCVState *env = &RISCV_CPU(obj)->env; 248 RISCVCPU *cpu = RISCV_CPU(obj); 249 250 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 251 set_priv_version(env, PRIV_VERSION_1_10_0); 252 set_resetvec(env, DEFAULT_RSTVEC); 253 cpu->cfg.mmu = false; 254 } 255 #endif 256 257 #if defined(CONFIG_KVM) 258 static void riscv_host_cpu_init(Object *obj) 259 { 260 CPURISCVState *env = &RISCV_CPU(obj)->env; 261 #if defined(TARGET_RISCV32) 262 set_misa(env, MXL_RV32, 0); 263 #elif defined(TARGET_RISCV64) 264 set_misa(env, MXL_RV64, 0); 265 #endif 266 register_cpu_props(DEVICE(obj)); 267 } 268 #endif 269 270 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 271 { 272 ObjectClass *oc; 273 char *typename; 274 char **cpuname; 275 276 cpuname = g_strsplit(cpu_model, ",", 1); 277 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 278 oc = object_class_by_name(typename); 279 g_strfreev(cpuname); 280 g_free(typename); 281 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 282 object_class_is_abstract(oc)) { 283 return NULL; 284 } 285 return oc; 286 } 287 288 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 289 { 290 RISCVCPU *cpu = RISCV_CPU(cs); 291 CPURISCVState *env = &cpu->env; 292 int i; 293 294 #if !defined(CONFIG_USER_ONLY) 295 if (riscv_has_ext(env, RVH)) { 296 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 297 } 298 #endif 299 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 300 #ifndef CONFIG_USER_ONLY 301 { 302 static const int dump_csrs[] = { 303 CSR_MHARTID, 304 CSR_MSTATUS, 305 CSR_MSTATUSH, 306 CSR_HSTATUS, 307 CSR_VSSTATUS, 308 CSR_MIP, 309 CSR_MIE, 310 CSR_MIDELEG, 311 CSR_HIDELEG, 312 CSR_MEDELEG, 313 CSR_HEDELEG, 314 CSR_MTVEC, 315 CSR_STVEC, 316 CSR_VSTVEC, 317 CSR_MEPC, 318 CSR_SEPC, 319 CSR_VSEPC, 320 CSR_MCAUSE, 321 CSR_SCAUSE, 322 CSR_VSCAUSE, 323 CSR_MTVAL, 324 CSR_STVAL, 325 CSR_HTVAL, 326 CSR_MTVAL2, 327 CSR_MSCRATCH, 328 CSR_SSCRATCH, 329 CSR_SATP, 330 CSR_MMTE, 331 CSR_UPMBASE, 332 CSR_UPMMASK, 333 CSR_SPMBASE, 334 CSR_SPMMASK, 335 CSR_MPMBASE, 336 CSR_MPMMASK, 337 }; 338 339 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 340 int csrno = dump_csrs[i]; 341 target_ulong val = 0; 342 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 343 344 /* 345 * Rely on the smode, hmode, etc, predicates within csr.c 346 * to do the filtering of the registers that are present. 347 */ 348 if (res == RISCV_EXCP_NONE) { 349 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 350 csr_ops[csrno].name, val); 351 } 352 } 353 } 354 #endif 355 356 for (i = 0; i < 32; i++) { 357 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 358 riscv_int_regnames[i], env->gpr[i]); 359 if ((i & 3) == 3) { 360 qemu_fprintf(f, "\n"); 361 } 362 } 363 if (flags & CPU_DUMP_FPU) { 364 for (i = 0; i < 32; i++) { 365 qemu_fprintf(f, " %-8s %016" PRIx64, 366 riscv_fpr_regnames[i], env->fpr[i]); 367 if ((i & 3) == 3) { 368 qemu_fprintf(f, "\n"); 369 } 370 } 371 } 372 } 373 374 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 375 { 376 RISCVCPU *cpu = RISCV_CPU(cs); 377 CPURISCVState *env = &cpu->env; 378 379 if (env->xl == MXL_RV32) { 380 env->pc = (int32_t)value; 381 } else { 382 env->pc = value; 383 } 384 } 385 386 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 387 const TranslationBlock *tb) 388 { 389 RISCVCPU *cpu = RISCV_CPU(cs); 390 CPURISCVState *env = &cpu->env; 391 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 392 393 if (xl == MXL_RV32) { 394 env->pc = (int32_t)tb->pc; 395 } else { 396 env->pc = tb->pc; 397 } 398 } 399 400 static bool riscv_cpu_has_work(CPUState *cs) 401 { 402 #ifndef CONFIG_USER_ONLY 403 RISCVCPU *cpu = RISCV_CPU(cs); 404 CPURISCVState *env = &cpu->env; 405 /* 406 * Definition of the WFI instruction requires it to ignore the privilege 407 * mode and delegation registers, but respect individual enables 408 */ 409 return riscv_cpu_all_pending(env) != 0; 410 #else 411 return true; 412 #endif 413 } 414 415 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 416 target_ulong *data) 417 { 418 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 419 if (xl == MXL_RV32) { 420 env->pc = (int32_t)data[0]; 421 } else { 422 env->pc = data[0]; 423 } 424 env->bins = data[1]; 425 } 426 427 static void riscv_cpu_reset(DeviceState *dev) 428 { 429 #ifndef CONFIG_USER_ONLY 430 uint8_t iprio; 431 int i, irq, rdzero; 432 #endif 433 CPUState *cs = CPU(dev); 434 RISCVCPU *cpu = RISCV_CPU(cs); 435 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 436 CPURISCVState *env = &cpu->env; 437 438 mcc->parent_reset(dev); 439 #ifndef CONFIG_USER_ONLY 440 env->misa_mxl = env->misa_mxl_max; 441 env->priv = PRV_M; 442 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 443 if (env->misa_mxl > MXL_RV32) { 444 /* 445 * The reset status of SXL/UXL is undefined, but mstatus is WARL 446 * and we must ensure that the value after init is valid for read. 447 */ 448 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 449 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 450 if (riscv_has_ext(env, RVH)) { 451 env->vsstatus = set_field(env->vsstatus, 452 MSTATUS64_SXL, env->misa_mxl); 453 env->vsstatus = set_field(env->vsstatus, 454 MSTATUS64_UXL, env->misa_mxl); 455 env->mstatus_hs = set_field(env->mstatus_hs, 456 MSTATUS64_SXL, env->misa_mxl); 457 env->mstatus_hs = set_field(env->mstatus_hs, 458 MSTATUS64_UXL, env->misa_mxl); 459 } 460 } 461 env->mcause = 0; 462 env->miclaim = MIP_SGEIP; 463 env->pc = env->resetvec; 464 env->bins = 0; 465 env->two_stage_lookup = false; 466 467 /* Initialized default priorities of local interrupts. */ 468 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 469 iprio = riscv_cpu_default_priority(i); 470 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 471 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 472 env->hviprio[i] = 0; 473 } 474 i = 0; 475 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 476 if (!rdzero) { 477 env->hviprio[irq] = env->miprio[irq]; 478 } 479 i++; 480 } 481 /* mmte is supposed to have pm.current hardwired to 1 */ 482 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 483 #endif 484 env->xl = riscv_cpu_mxl(env); 485 riscv_cpu_update_mask(env); 486 cs->exception_index = RISCV_EXCP_NONE; 487 env->load_res = -1; 488 set_default_nan_mode(1, &env->fp_status); 489 490 #ifndef CONFIG_USER_ONLY 491 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 492 riscv_trigger_init(env); 493 } 494 495 if (kvm_enabled()) { 496 kvm_riscv_reset_vcpu(cpu); 497 } 498 #endif 499 } 500 501 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 502 { 503 RISCVCPU *cpu = RISCV_CPU(s); 504 505 switch (riscv_cpu_mxl(&cpu->env)) { 506 case MXL_RV32: 507 info->print_insn = print_insn_riscv32; 508 break; 509 case MXL_RV64: 510 info->print_insn = print_insn_riscv64; 511 break; 512 case MXL_RV128: 513 info->print_insn = print_insn_riscv128; 514 break; 515 default: 516 g_assert_not_reached(); 517 } 518 } 519 520 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 521 { 522 CPUState *cs = CPU(dev); 523 RISCVCPU *cpu = RISCV_CPU(dev); 524 CPURISCVState *env = &cpu->env; 525 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 526 CPUClass *cc = CPU_CLASS(mcc); 527 int priv_version = 0; 528 Error *local_err = NULL; 529 530 cpu_exec_realizefn(cs, &local_err); 531 if (local_err != NULL) { 532 error_propagate(errp, local_err); 533 return; 534 } 535 536 if (cpu->cfg.priv_spec) { 537 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 538 priv_version = PRIV_VERSION_1_12_0; 539 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 540 priv_version = PRIV_VERSION_1_11_0; 541 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 542 priv_version = PRIV_VERSION_1_10_0; 543 } else { 544 error_setg(errp, 545 "Unsupported privilege spec version '%s'", 546 cpu->cfg.priv_spec); 547 return; 548 } 549 } 550 551 if (priv_version) { 552 set_priv_version(env, priv_version); 553 } else if (!env->priv_ver) { 554 set_priv_version(env, PRIV_VERSION_1_12_0); 555 } 556 557 if (cpu->cfg.mmu) { 558 riscv_set_feature(env, RISCV_FEATURE_MMU); 559 } 560 561 if (cpu->cfg.pmp) { 562 riscv_set_feature(env, RISCV_FEATURE_PMP); 563 564 /* 565 * Enhanced PMP should only be available 566 * on harts with PMP support 567 */ 568 if (cpu->cfg.epmp) { 569 riscv_set_feature(env, RISCV_FEATURE_EPMP); 570 } 571 } 572 573 if (cpu->cfg.aia) { 574 riscv_set_feature(env, RISCV_FEATURE_AIA); 575 } 576 577 if (cpu->cfg.debug) { 578 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 579 } 580 581 set_resetvec(env, cpu->cfg.resetvec); 582 583 /* Validate that MISA_MXL is set properly. */ 584 switch (env->misa_mxl_max) { 585 #ifdef TARGET_RISCV64 586 case MXL_RV64: 587 case MXL_RV128: 588 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 589 break; 590 #endif 591 case MXL_RV32: 592 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 593 break; 594 default: 595 g_assert_not_reached(); 596 } 597 assert(env->misa_mxl_max == env->misa_mxl); 598 599 /* If only MISA_EXT is unset for misa, then set it from properties */ 600 if (env->misa_ext == 0) { 601 uint32_t ext = 0; 602 603 /* Do some ISA extension error checking */ 604 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 605 cpu->cfg.ext_a && cpu->cfg.ext_f && 606 cpu->cfg.ext_d && 607 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 608 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 609 cpu->cfg.ext_i = true; 610 cpu->cfg.ext_m = true; 611 cpu->cfg.ext_a = true; 612 cpu->cfg.ext_f = true; 613 cpu->cfg.ext_d = true; 614 cpu->cfg.ext_icsr = true; 615 cpu->cfg.ext_ifencei = true; 616 } 617 618 if (cpu->cfg.ext_m && cpu->cfg.ext_zmmul) { 619 warn_report("Zmmul will override M"); 620 cpu->cfg.ext_m = false; 621 } 622 623 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 624 error_setg(errp, 625 "I and E extensions are incompatible"); 626 return; 627 } 628 629 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 630 error_setg(errp, 631 "Either I or E extension must be set"); 632 return; 633 } 634 635 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 636 error_setg(errp, "F extension requires Zicsr"); 637 return; 638 } 639 640 if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { 641 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 642 return; 643 } 644 645 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 646 error_setg(errp, "D extension requires F extension"); 647 return; 648 } 649 650 if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { 651 error_setg(errp, "V extension requires D extension"); 652 return; 653 } 654 655 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 656 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 657 return; 658 } 659 660 /* Set the ISA extensions, checks should have happened above */ 661 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || 662 cpu->cfg.ext_zhinxmin) { 663 cpu->cfg.ext_zfinx = true; 664 } 665 666 if (cpu->cfg.ext_zfinx) { 667 if (!cpu->cfg.ext_icsr) { 668 error_setg(errp, "Zfinx extension requires Zicsr"); 669 return; 670 } 671 if (cpu->cfg.ext_f) { 672 error_setg(errp, 673 "Zfinx cannot be supported together with F extension"); 674 return; 675 } 676 } 677 678 if (cpu->cfg.ext_zk) { 679 cpu->cfg.ext_zkn = true; 680 cpu->cfg.ext_zkr = true; 681 cpu->cfg.ext_zkt = true; 682 } 683 684 if (cpu->cfg.ext_zkn) { 685 cpu->cfg.ext_zbkb = true; 686 cpu->cfg.ext_zbkc = true; 687 cpu->cfg.ext_zbkx = true; 688 cpu->cfg.ext_zkne = true; 689 cpu->cfg.ext_zknd = true; 690 cpu->cfg.ext_zknh = true; 691 } 692 693 if (cpu->cfg.ext_zks) { 694 cpu->cfg.ext_zbkb = true; 695 cpu->cfg.ext_zbkc = true; 696 cpu->cfg.ext_zbkx = true; 697 cpu->cfg.ext_zksed = true; 698 cpu->cfg.ext_zksh = true; 699 } 700 701 if (cpu->cfg.ext_i) { 702 ext |= RVI; 703 } 704 if (cpu->cfg.ext_e) { 705 ext |= RVE; 706 } 707 if (cpu->cfg.ext_m) { 708 ext |= RVM; 709 } 710 if (cpu->cfg.ext_a) { 711 ext |= RVA; 712 } 713 if (cpu->cfg.ext_f) { 714 ext |= RVF; 715 } 716 if (cpu->cfg.ext_d) { 717 ext |= RVD; 718 } 719 if (cpu->cfg.ext_c) { 720 ext |= RVC; 721 } 722 if (cpu->cfg.ext_s) { 723 ext |= RVS; 724 } 725 if (cpu->cfg.ext_u) { 726 ext |= RVU; 727 } 728 if (cpu->cfg.ext_h) { 729 ext |= RVH; 730 } 731 if (cpu->cfg.ext_v) { 732 int vext_version = VEXT_VERSION_1_00_0; 733 ext |= RVV; 734 if (!is_power_of_2(cpu->cfg.vlen)) { 735 error_setg(errp, 736 "Vector extension VLEN must be power of 2"); 737 return; 738 } 739 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 740 error_setg(errp, 741 "Vector extension implementation only supports VLEN " 742 "in the range [128, %d]", RV_VLEN_MAX); 743 return; 744 } 745 if (!is_power_of_2(cpu->cfg.elen)) { 746 error_setg(errp, 747 "Vector extension ELEN must be power of 2"); 748 return; 749 } 750 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 751 error_setg(errp, 752 "Vector extension implementation only supports ELEN " 753 "in the range [8, 64]"); 754 return; 755 } 756 if (cpu->cfg.vext_spec) { 757 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 758 vext_version = VEXT_VERSION_1_00_0; 759 } else { 760 error_setg(errp, 761 "Unsupported vector spec version '%s'", 762 cpu->cfg.vext_spec); 763 return; 764 } 765 } else { 766 qemu_log("vector version is not specified, " 767 "use the default value v1.0\n"); 768 } 769 set_vext_version(env, vext_version); 770 } 771 if (cpu->cfg.ext_j) { 772 ext |= RVJ; 773 } 774 775 set_misa(env, env->misa_mxl, ext); 776 } 777 778 riscv_cpu_register_gdb_regs_for_features(cs); 779 780 qemu_init_vcpu(cs); 781 cpu_reset(cs); 782 783 mcc->parent_realize(dev, errp); 784 } 785 786 #ifndef CONFIG_USER_ONLY 787 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 788 { 789 RISCVCPU *cpu = RISCV_CPU(opaque); 790 CPURISCVState *env = &cpu->env; 791 792 if (irq < IRQ_LOCAL_MAX) { 793 switch (irq) { 794 case IRQ_U_SOFT: 795 case IRQ_S_SOFT: 796 case IRQ_VS_SOFT: 797 case IRQ_M_SOFT: 798 case IRQ_U_TIMER: 799 case IRQ_S_TIMER: 800 case IRQ_VS_TIMER: 801 case IRQ_M_TIMER: 802 case IRQ_U_EXT: 803 case IRQ_VS_EXT: 804 case IRQ_M_EXT: 805 if (kvm_enabled()) { 806 kvm_riscv_set_irq(cpu, irq, level); 807 } else { 808 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 809 } 810 break; 811 case IRQ_S_EXT: 812 if (kvm_enabled()) { 813 kvm_riscv_set_irq(cpu, irq, level); 814 } else { 815 env->external_seip = level; 816 riscv_cpu_update_mip(cpu, 1 << irq, 817 BOOL_TO_MASK(level | env->software_seip)); 818 } 819 break; 820 default: 821 g_assert_not_reached(); 822 } 823 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 824 /* Require H-extension for handling guest local interrupts */ 825 if (!riscv_has_ext(env, RVH)) { 826 g_assert_not_reached(); 827 } 828 829 /* Compute bit position in HGEIP CSR */ 830 irq = irq - IRQ_LOCAL_MAX + 1; 831 if (env->geilen < irq) { 832 g_assert_not_reached(); 833 } 834 835 /* Update HGEIP CSR */ 836 env->hgeip &= ~((target_ulong)1 << irq); 837 if (level) { 838 env->hgeip |= (target_ulong)1 << irq; 839 } 840 841 /* Update mip.SGEIP bit */ 842 riscv_cpu_update_mip(cpu, MIP_SGEIP, 843 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 844 } else { 845 g_assert_not_reached(); 846 } 847 } 848 #endif /* CONFIG_USER_ONLY */ 849 850 static void riscv_cpu_init(Object *obj) 851 { 852 RISCVCPU *cpu = RISCV_CPU(obj); 853 854 cpu->cfg.ext_pmu = true; 855 cpu->cfg.ext_ifencei = true; 856 cpu->cfg.ext_icsr = true; 857 cpu->cfg.mmu = true; 858 cpu->cfg.pmp = true; 859 860 cpu_set_cpustate_pointers(cpu); 861 862 #ifndef CONFIG_USER_ONLY 863 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 864 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 865 #endif /* CONFIG_USER_ONLY */ 866 } 867 868 static Property riscv_cpu_extensions[] = { 869 /* Defaults for standard extensions */ 870 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 871 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 872 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 873 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 874 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 875 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 876 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 877 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 878 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 879 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 880 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 881 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 882 DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true), 883 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 884 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 885 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 886 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 887 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 888 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 889 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 890 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 891 892 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 893 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 894 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 895 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 896 897 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 898 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 899 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 900 901 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 902 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 903 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 904 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 905 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 906 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 907 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 908 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 909 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 910 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 911 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 912 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 913 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 914 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 915 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 916 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 917 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 918 919 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 920 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 921 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 922 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 923 924 /* Vendor-specific custom extensions */ 925 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 926 927 /* These are experimental so mark with 'x-' */ 928 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 929 DEFINE_PROP_BOOL("x-zmmul", RISCVCPU, cfg.ext_zmmul, false), 930 /* ePMP 0.9.3 */ 931 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 932 DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), 933 934 DEFINE_PROP_END_OF_LIST(), 935 }; 936 937 static void register_cpu_props(DeviceState *dev) 938 { 939 Property *prop; 940 941 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 942 qdev_property_add_static(dev, prop); 943 } 944 } 945 946 static Property riscv_cpu_properties[] = { 947 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 948 949 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 950 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 951 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 952 953 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 954 955 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 956 957 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 958 DEFINE_PROP_END_OF_LIST(), 959 }; 960 961 static gchar *riscv_gdb_arch_name(CPUState *cs) 962 { 963 RISCVCPU *cpu = RISCV_CPU(cs); 964 CPURISCVState *env = &cpu->env; 965 966 switch (riscv_cpu_mxl(env)) { 967 case MXL_RV32: 968 return g_strdup("riscv:rv32"); 969 case MXL_RV64: 970 case MXL_RV128: 971 return g_strdup("riscv:rv64"); 972 default: 973 g_assert_not_reached(); 974 } 975 } 976 977 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 978 { 979 RISCVCPU *cpu = RISCV_CPU(cs); 980 981 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 982 return cpu->dyn_csr_xml; 983 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 984 return cpu->dyn_vreg_xml; 985 } 986 987 return NULL; 988 } 989 990 #ifndef CONFIG_USER_ONLY 991 #include "hw/core/sysemu-cpu-ops.h" 992 993 static const struct SysemuCPUOps riscv_sysemu_ops = { 994 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 995 .write_elf64_note = riscv_cpu_write_elf64_note, 996 .write_elf32_note = riscv_cpu_write_elf32_note, 997 .legacy_vmsd = &vmstate_riscv_cpu, 998 }; 999 #endif 1000 1001 #include "hw/core/tcg-cpu-ops.h" 1002 1003 static const struct TCGCPUOps riscv_tcg_ops = { 1004 .initialize = riscv_translate_init, 1005 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1006 1007 #ifndef CONFIG_USER_ONLY 1008 .tlb_fill = riscv_cpu_tlb_fill, 1009 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1010 .do_interrupt = riscv_cpu_do_interrupt, 1011 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1012 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1013 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1014 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1015 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1016 #endif /* !CONFIG_USER_ONLY */ 1017 }; 1018 1019 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1020 { 1021 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1022 CPUClass *cc = CPU_CLASS(c); 1023 DeviceClass *dc = DEVICE_CLASS(c); 1024 1025 device_class_set_parent_realize(dc, riscv_cpu_realize, 1026 &mcc->parent_realize); 1027 1028 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 1029 1030 cc->class_by_name = riscv_cpu_class_by_name; 1031 cc->has_work = riscv_cpu_has_work; 1032 cc->dump_state = riscv_cpu_dump_state; 1033 cc->set_pc = riscv_cpu_set_pc; 1034 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1035 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1036 cc->gdb_num_core_regs = 33; 1037 cc->gdb_stop_before_watchpoint = true; 1038 cc->disas_set_info = riscv_cpu_disas_set_info; 1039 #ifndef CONFIG_USER_ONLY 1040 cc->sysemu_ops = &riscv_sysemu_ops; 1041 #endif 1042 cc->gdb_arch_name = riscv_gdb_arch_name; 1043 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1044 cc->tcg_ops = &riscv_tcg_ops; 1045 1046 device_class_set_props(dc, riscv_cpu_properties); 1047 } 1048 1049 #define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop} 1050 1051 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1052 { 1053 char *old = *isa_str; 1054 char *new = *isa_str; 1055 int i; 1056 1057 /** 1058 * Here are the ordering rules of extension naming defined by RISC-V 1059 * specification : 1060 * 1. All extensions should be separated from other multi-letter extensions 1061 * by an underscore. 1062 * 2. The first letter following the 'Z' conventionally indicates the most 1063 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 1064 * If multiple 'Z' extensions are named, they should be ordered first 1065 * by category, then alphabetically within a category. 1066 * 3. Standard supervisor-level extensions (starts with 'S') should be 1067 * listed after standard unprivileged extensions. If multiple 1068 * supervisor-level extensions are listed, they should be ordered 1069 * alphabetically. 1070 * 4. Non-standard extensions (starts with 'X') must be listed after all 1071 * standard extensions. They must be separated from other multi-letter 1072 * extensions by an underscore. 1073 */ 1074 struct isa_ext_data isa_edata_arr[] = { 1075 ISA_EDATA_ENTRY(zicsr, ext_icsr), 1076 ISA_EDATA_ENTRY(zifencei, ext_ifencei), 1077 ISA_EDATA_ENTRY(zmmul, ext_zmmul), 1078 ISA_EDATA_ENTRY(zfh, ext_zfh), 1079 ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), 1080 ISA_EDATA_ENTRY(zfinx, ext_zfinx), 1081 ISA_EDATA_ENTRY(zdinx, ext_zdinx), 1082 ISA_EDATA_ENTRY(zba, ext_zba), 1083 ISA_EDATA_ENTRY(zbb, ext_zbb), 1084 ISA_EDATA_ENTRY(zbc, ext_zbc), 1085 ISA_EDATA_ENTRY(zbkb, ext_zbkb), 1086 ISA_EDATA_ENTRY(zbkc, ext_zbkc), 1087 ISA_EDATA_ENTRY(zbkx, ext_zbkx), 1088 ISA_EDATA_ENTRY(zbs, ext_zbs), 1089 ISA_EDATA_ENTRY(zk, ext_zk), 1090 ISA_EDATA_ENTRY(zkn, ext_zkn), 1091 ISA_EDATA_ENTRY(zknd, ext_zknd), 1092 ISA_EDATA_ENTRY(zkne, ext_zkne), 1093 ISA_EDATA_ENTRY(zknh, ext_zknh), 1094 ISA_EDATA_ENTRY(zkr, ext_zkr), 1095 ISA_EDATA_ENTRY(zks, ext_zks), 1096 ISA_EDATA_ENTRY(zksed, ext_zksed), 1097 ISA_EDATA_ENTRY(zksh, ext_zksh), 1098 ISA_EDATA_ENTRY(zkt, ext_zkt), 1099 ISA_EDATA_ENTRY(zve32f, ext_zve32f), 1100 ISA_EDATA_ENTRY(zve64f, ext_zve64f), 1101 ISA_EDATA_ENTRY(zhinx, ext_zhinx), 1102 ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), 1103 ISA_EDATA_ENTRY(svinval, ext_svinval), 1104 ISA_EDATA_ENTRY(svnapot, ext_svnapot), 1105 ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), 1106 }; 1107 1108 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1109 if (isa_edata_arr[i].enabled) { 1110 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1111 g_free(old); 1112 old = new; 1113 } 1114 } 1115 1116 *isa_str = new; 1117 } 1118 1119 char *riscv_isa_string(RISCVCPU *cpu) 1120 { 1121 int i; 1122 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1123 char *isa_str = g_new(char, maxlen); 1124 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1125 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1126 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1127 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1128 } 1129 } 1130 *p = '\0'; 1131 if (!cpu->cfg.short_isa_string) { 1132 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1133 } 1134 return isa_str; 1135 } 1136 1137 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1138 { 1139 ObjectClass *class_a = (ObjectClass *)a; 1140 ObjectClass *class_b = (ObjectClass *)b; 1141 const char *name_a, *name_b; 1142 1143 name_a = object_class_get_name(class_a); 1144 name_b = object_class_get_name(class_b); 1145 return strcmp(name_a, name_b); 1146 } 1147 1148 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1149 { 1150 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1151 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1152 1153 qemu_printf("%.*s\n", len, typename); 1154 } 1155 1156 void riscv_cpu_list(void) 1157 { 1158 GSList *list; 1159 1160 list = object_class_get_list(TYPE_RISCV_CPU, false); 1161 list = g_slist_sort(list, riscv_cpu_list_compare); 1162 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1163 g_slist_free(list); 1164 } 1165 1166 #define DEFINE_CPU(type_name, initfn) \ 1167 { \ 1168 .name = type_name, \ 1169 .parent = TYPE_RISCV_CPU, \ 1170 .instance_init = initfn \ 1171 } 1172 1173 static const TypeInfo riscv_cpu_type_infos[] = { 1174 { 1175 .name = TYPE_RISCV_CPU, 1176 .parent = TYPE_CPU, 1177 .instance_size = sizeof(RISCVCPU), 1178 .instance_align = __alignof__(RISCVCPU), 1179 .instance_init = riscv_cpu_init, 1180 .abstract = true, 1181 .class_size = sizeof(RISCVCPUClass), 1182 .class_init = riscv_cpu_class_init, 1183 }, 1184 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1185 #if defined(CONFIG_KVM) 1186 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1187 #endif 1188 #if defined(TARGET_RISCV32) 1189 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1190 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1191 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1192 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1193 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1194 #elif defined(TARGET_RISCV64) 1195 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1196 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1197 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1198 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1199 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1200 #endif 1201 }; 1202 1203 DEFINE_TYPES(riscv_cpu_type_infos) 1204