1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "exec/exec-all.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "fpu/softfloat-helpers.h" 32 #include "sysemu/kvm.h" 33 #include "kvm_riscv.h" 34 35 /* RISC-V CPU definitions */ 36 37 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 38 39 const char * const riscv_int_regnames[] = { 40 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 41 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 42 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 43 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 44 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 45 }; 46 47 const char * const riscv_int_regnamesh[] = { 48 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 49 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 50 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 51 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 52 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 53 "x30h/t5h", "x31h/t6h" 54 }; 55 56 const char * const riscv_fpr_regnames[] = { 57 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 58 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 59 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 60 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 61 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 62 "f30/ft10", "f31/ft11" 63 }; 64 65 static const char * const riscv_excp_names[] = { 66 "misaligned_fetch", 67 "fault_fetch", 68 "illegal_instruction", 69 "breakpoint", 70 "misaligned_load", 71 "fault_load", 72 "misaligned_store", 73 "fault_store", 74 "user_ecall", 75 "supervisor_ecall", 76 "hypervisor_ecall", 77 "machine_ecall", 78 "exec_page_fault", 79 "load_page_fault", 80 "reserved", 81 "store_page_fault", 82 "reserved", 83 "reserved", 84 "reserved", 85 "reserved", 86 "guest_exec_page_fault", 87 "guest_load_page_fault", 88 "reserved", 89 "guest_store_page_fault", 90 }; 91 92 static const char * const riscv_intr_names[] = { 93 "u_software", 94 "s_software", 95 "vs_software", 96 "m_software", 97 "u_timer", 98 "s_timer", 99 "vs_timer", 100 "m_timer", 101 "u_external", 102 "s_external", 103 "vs_external", 104 "m_external", 105 "reserved", 106 "reserved", 107 "reserved", 108 "reserved" 109 }; 110 111 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 112 { 113 if (async) { 114 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 115 riscv_intr_names[cause] : "(unknown)"; 116 } else { 117 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 118 riscv_excp_names[cause] : "(unknown)"; 119 } 120 } 121 122 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 123 { 124 env->misa_mxl_max = env->misa_mxl = mxl; 125 env->misa_ext_mask = env->misa_ext = ext; 126 } 127 128 static void set_priv_version(CPURISCVState *env, int priv_ver) 129 { 130 env->priv_ver = priv_ver; 131 } 132 133 static void set_vext_version(CPURISCVState *env, int vext_ver) 134 { 135 env->vext_ver = vext_ver; 136 } 137 138 static void set_feature(CPURISCVState *env, int feature) 139 { 140 env->features |= (1ULL << feature); 141 } 142 143 static void set_resetvec(CPURISCVState *env, target_ulong resetvec) 144 { 145 #ifndef CONFIG_USER_ONLY 146 env->resetvec = resetvec; 147 #endif 148 } 149 150 static void riscv_any_cpu_init(Object *obj) 151 { 152 CPURISCVState *env = &RISCV_CPU(obj)->env; 153 #if defined(TARGET_RISCV32) 154 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 155 #elif defined(TARGET_RISCV64) 156 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 157 #endif 158 set_priv_version(env, PRIV_VERSION_1_11_0); 159 } 160 161 #if defined(TARGET_RISCV64) 162 static void rv64_base_cpu_init(Object *obj) 163 { 164 CPURISCVState *env = &RISCV_CPU(obj)->env; 165 /* We set this in the realise function */ 166 set_misa(env, MXL_RV64, 0); 167 } 168 169 static void rv64_sifive_u_cpu_init(Object *obj) 170 { 171 CPURISCVState *env = &RISCV_CPU(obj)->env; 172 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 173 set_priv_version(env, PRIV_VERSION_1_10_0); 174 } 175 176 static void rv64_sifive_e_cpu_init(Object *obj) 177 { 178 CPURISCVState *env = &RISCV_CPU(obj)->env; 179 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 180 set_priv_version(env, PRIV_VERSION_1_10_0); 181 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 182 } 183 184 static void rv128_base_cpu_init(Object *obj) 185 { 186 if (qemu_tcg_mttcg_enabled()) { 187 /* Missing 128-bit aligned atomics */ 188 error_report("128-bit RISC-V currently does not work with Multi " 189 "Threaded TCG. Please use: -accel tcg,thread=single"); 190 exit(EXIT_FAILURE); 191 } 192 CPURISCVState *env = &RISCV_CPU(obj)->env; 193 /* We set this in the realise function */ 194 set_misa(env, MXL_RV128, 0); 195 } 196 #else 197 static void rv32_base_cpu_init(Object *obj) 198 { 199 CPURISCVState *env = &RISCV_CPU(obj)->env; 200 /* We set this in the realise function */ 201 set_misa(env, MXL_RV32, 0); 202 } 203 204 static void rv32_sifive_u_cpu_init(Object *obj) 205 { 206 CPURISCVState *env = &RISCV_CPU(obj)->env; 207 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 208 set_priv_version(env, PRIV_VERSION_1_10_0); 209 } 210 211 static void rv32_sifive_e_cpu_init(Object *obj) 212 { 213 CPURISCVState *env = &RISCV_CPU(obj)->env; 214 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 215 set_priv_version(env, PRIV_VERSION_1_10_0); 216 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 217 } 218 219 static void rv32_ibex_cpu_init(Object *obj) 220 { 221 CPURISCVState *env = &RISCV_CPU(obj)->env; 222 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 223 set_priv_version(env, PRIV_VERSION_1_10_0); 224 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 225 qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); 226 } 227 228 static void rv32_imafcu_nommu_cpu_init(Object *obj) 229 { 230 CPURISCVState *env = &RISCV_CPU(obj)->env; 231 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 232 set_priv_version(env, PRIV_VERSION_1_10_0); 233 set_resetvec(env, DEFAULT_RSTVEC); 234 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 235 } 236 #endif 237 238 #if defined(CONFIG_KVM) 239 static void riscv_host_cpu_init(Object *obj) 240 { 241 CPURISCVState *env = &RISCV_CPU(obj)->env; 242 #if defined(TARGET_RISCV32) 243 set_misa(env, MXL_RV32, 0); 244 #elif defined(TARGET_RISCV64) 245 set_misa(env, MXL_RV64, 0); 246 #endif 247 } 248 #endif 249 250 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 251 { 252 ObjectClass *oc; 253 char *typename; 254 char **cpuname; 255 256 cpuname = g_strsplit(cpu_model, ",", 1); 257 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 258 oc = object_class_by_name(typename); 259 g_strfreev(cpuname); 260 g_free(typename); 261 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 262 object_class_is_abstract(oc)) { 263 return NULL; 264 } 265 return oc; 266 } 267 268 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 269 { 270 RISCVCPU *cpu = RISCV_CPU(cs); 271 CPURISCVState *env = &cpu->env; 272 int i; 273 274 #if !defined(CONFIG_USER_ONLY) 275 if (riscv_has_ext(env, RVH)) { 276 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 277 } 278 #endif 279 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 280 #ifndef CONFIG_USER_ONLY 281 { 282 static const int dump_csrs[] = { 283 CSR_MHARTID, 284 CSR_MSTATUS, 285 CSR_MSTATUSH, 286 CSR_HSTATUS, 287 CSR_VSSTATUS, 288 CSR_MIP, 289 CSR_MIE, 290 CSR_MIDELEG, 291 CSR_HIDELEG, 292 CSR_MEDELEG, 293 CSR_HEDELEG, 294 CSR_MTVEC, 295 CSR_STVEC, 296 CSR_VSTVEC, 297 CSR_MEPC, 298 CSR_SEPC, 299 CSR_VSEPC, 300 CSR_MCAUSE, 301 CSR_SCAUSE, 302 CSR_VSCAUSE, 303 CSR_MTVAL, 304 CSR_STVAL, 305 CSR_HTVAL, 306 CSR_MTVAL2, 307 CSR_MSCRATCH, 308 CSR_SSCRATCH, 309 CSR_SATP, 310 CSR_MMTE, 311 CSR_UPMBASE, 312 CSR_UPMMASK, 313 CSR_SPMBASE, 314 CSR_SPMMASK, 315 CSR_MPMBASE, 316 CSR_MPMMASK, 317 }; 318 319 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 320 int csrno = dump_csrs[i]; 321 target_ulong val = 0; 322 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 323 324 /* 325 * Rely on the smode, hmode, etc, predicates within csr.c 326 * to do the filtering of the registers that are present. 327 */ 328 if (res == RISCV_EXCP_NONE) { 329 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 330 csr_ops[csrno].name, val); 331 } 332 } 333 } 334 #endif 335 336 for (i = 0; i < 32; i++) { 337 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 338 riscv_int_regnames[i], env->gpr[i]); 339 if ((i & 3) == 3) { 340 qemu_fprintf(f, "\n"); 341 } 342 } 343 if (flags & CPU_DUMP_FPU) { 344 for (i = 0; i < 32; i++) { 345 qemu_fprintf(f, " %-8s %016" PRIx64, 346 riscv_fpr_regnames[i], env->fpr[i]); 347 if ((i & 3) == 3) { 348 qemu_fprintf(f, "\n"); 349 } 350 } 351 } 352 } 353 354 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 355 { 356 RISCVCPU *cpu = RISCV_CPU(cs); 357 CPURISCVState *env = &cpu->env; 358 359 if (env->xl == MXL_RV32) { 360 env->pc = (int32_t)value; 361 } else { 362 env->pc = value; 363 } 364 } 365 366 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 367 const TranslationBlock *tb) 368 { 369 RISCVCPU *cpu = RISCV_CPU(cs); 370 CPURISCVState *env = &cpu->env; 371 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 372 373 if (xl == MXL_RV32) { 374 env->pc = (int32_t)tb->pc; 375 } else { 376 env->pc = tb->pc; 377 } 378 } 379 380 static bool riscv_cpu_has_work(CPUState *cs) 381 { 382 #ifndef CONFIG_USER_ONLY 383 RISCVCPU *cpu = RISCV_CPU(cs); 384 CPURISCVState *env = &cpu->env; 385 /* 386 * Definition of the WFI instruction requires it to ignore the privilege 387 * mode and delegation registers, but respect individual enables 388 */ 389 return (env->mip & env->mie) != 0; 390 #else 391 return true; 392 #endif 393 } 394 395 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 396 target_ulong *data) 397 { 398 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 399 if (xl == MXL_RV32) { 400 env->pc = (int32_t)data[0]; 401 } else { 402 env->pc = data[0]; 403 } 404 } 405 406 static void riscv_cpu_reset(DeviceState *dev) 407 { 408 CPUState *cs = CPU(dev); 409 RISCVCPU *cpu = RISCV_CPU(cs); 410 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 411 CPURISCVState *env = &cpu->env; 412 413 mcc->parent_reset(dev); 414 #ifndef CONFIG_USER_ONLY 415 env->misa_mxl = env->misa_mxl_max; 416 env->priv = PRV_M; 417 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 418 if (env->misa_mxl > MXL_RV32) { 419 /* 420 * The reset status of SXL/UXL is undefined, but mstatus is WARL 421 * and we must ensure that the value after init is valid for read. 422 */ 423 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 424 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 425 if (riscv_has_ext(env, RVH)) { 426 env->vsstatus = set_field(env->vsstatus, 427 MSTATUS64_SXL, env->misa_mxl); 428 env->vsstatus = set_field(env->vsstatus, 429 MSTATUS64_UXL, env->misa_mxl); 430 env->mstatus_hs = set_field(env->mstatus_hs, 431 MSTATUS64_SXL, env->misa_mxl); 432 env->mstatus_hs = set_field(env->mstatus_hs, 433 MSTATUS64_UXL, env->misa_mxl); 434 } 435 } 436 env->mcause = 0; 437 env->miclaim = MIP_SGEIP; 438 env->pc = env->resetvec; 439 env->two_stage_lookup = false; 440 /* mmte is supposed to have pm.current hardwired to 1 */ 441 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 442 #endif 443 env->xl = riscv_cpu_mxl(env); 444 riscv_cpu_update_mask(env); 445 cs->exception_index = RISCV_EXCP_NONE; 446 env->load_res = -1; 447 set_default_nan_mode(1, &env->fp_status); 448 449 #ifndef CONFIG_USER_ONLY 450 if (kvm_enabled()) { 451 kvm_riscv_reset_vcpu(cpu); 452 } 453 #endif 454 } 455 456 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 457 { 458 RISCVCPU *cpu = RISCV_CPU(s); 459 460 switch (riscv_cpu_mxl(&cpu->env)) { 461 case MXL_RV32: 462 info->print_insn = print_insn_riscv32; 463 break; 464 case MXL_RV64: 465 info->print_insn = print_insn_riscv64; 466 break; 467 case MXL_RV128: 468 info->print_insn = print_insn_riscv128; 469 break; 470 default: 471 g_assert_not_reached(); 472 } 473 } 474 475 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 476 { 477 CPUState *cs = CPU(dev); 478 RISCVCPU *cpu = RISCV_CPU(dev); 479 CPURISCVState *env = &cpu->env; 480 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 481 CPUClass *cc = CPU_CLASS(mcc); 482 int priv_version = 0; 483 Error *local_err = NULL; 484 485 cpu_exec_realizefn(cs, &local_err); 486 if (local_err != NULL) { 487 error_propagate(errp, local_err); 488 return; 489 } 490 491 if (cpu->cfg.priv_spec) { 492 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 493 priv_version = PRIV_VERSION_1_11_0; 494 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 495 priv_version = PRIV_VERSION_1_10_0; 496 } else { 497 error_setg(errp, 498 "Unsupported privilege spec version '%s'", 499 cpu->cfg.priv_spec); 500 return; 501 } 502 } 503 504 if (priv_version) { 505 set_priv_version(env, priv_version); 506 } else if (!env->priv_ver) { 507 set_priv_version(env, PRIV_VERSION_1_11_0); 508 } 509 510 if (cpu->cfg.mmu) { 511 set_feature(env, RISCV_FEATURE_MMU); 512 } 513 514 if (cpu->cfg.pmp) { 515 set_feature(env, RISCV_FEATURE_PMP); 516 517 /* 518 * Enhanced PMP should only be available 519 * on harts with PMP support 520 */ 521 if (cpu->cfg.epmp) { 522 set_feature(env, RISCV_FEATURE_EPMP); 523 } 524 } 525 526 set_resetvec(env, cpu->cfg.resetvec); 527 528 /* Validate that MISA_MXL is set properly. */ 529 switch (env->misa_mxl_max) { 530 #ifdef TARGET_RISCV64 531 case MXL_RV64: 532 case MXL_RV128: 533 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 534 break; 535 #endif 536 case MXL_RV32: 537 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 538 break; 539 default: 540 g_assert_not_reached(); 541 } 542 assert(env->misa_mxl_max == env->misa_mxl); 543 544 /* If only MISA_EXT is unset for misa, then set it from properties */ 545 if (env->misa_ext == 0) { 546 uint32_t ext = 0; 547 548 /* Do some ISA extension error checking */ 549 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 550 error_setg(errp, 551 "I and E extensions are incompatible"); 552 return; 553 } 554 555 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 556 error_setg(errp, 557 "Either I or E extension must be set"); 558 return; 559 } 560 561 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 562 cpu->cfg.ext_a & cpu->cfg.ext_f & 563 cpu->cfg.ext_d)) { 564 warn_report("Setting G will also set IMAFD"); 565 cpu->cfg.ext_i = true; 566 cpu->cfg.ext_m = true; 567 cpu->cfg.ext_a = true; 568 cpu->cfg.ext_f = true; 569 cpu->cfg.ext_d = true; 570 } 571 572 /* Set the ISA extensions, checks should have happened above */ 573 if (cpu->cfg.ext_i) { 574 ext |= RVI; 575 } 576 if (cpu->cfg.ext_e) { 577 ext |= RVE; 578 } 579 if (cpu->cfg.ext_m) { 580 ext |= RVM; 581 } 582 if (cpu->cfg.ext_a) { 583 ext |= RVA; 584 } 585 if (cpu->cfg.ext_f) { 586 ext |= RVF; 587 } 588 if (cpu->cfg.ext_d) { 589 ext |= RVD; 590 } 591 if (cpu->cfg.ext_c) { 592 ext |= RVC; 593 } 594 if (cpu->cfg.ext_s) { 595 ext |= RVS; 596 } 597 if (cpu->cfg.ext_u) { 598 ext |= RVU; 599 } 600 if (cpu->cfg.ext_h) { 601 ext |= RVH; 602 } 603 if (cpu->cfg.ext_v) { 604 int vext_version = VEXT_VERSION_1_00_0; 605 ext |= RVV; 606 if (!is_power_of_2(cpu->cfg.vlen)) { 607 error_setg(errp, 608 "Vector extension VLEN must be power of 2"); 609 return; 610 } 611 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 612 error_setg(errp, 613 "Vector extension implementation only supports VLEN " 614 "in the range [128, %d]", RV_VLEN_MAX); 615 return; 616 } 617 if (!is_power_of_2(cpu->cfg.elen)) { 618 error_setg(errp, 619 "Vector extension ELEN must be power of 2"); 620 return; 621 } 622 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 623 error_setg(errp, 624 "Vector extension implementation only supports ELEN " 625 "in the range [8, 64]"); 626 return; 627 } 628 if (cpu->cfg.vext_spec) { 629 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 630 vext_version = VEXT_VERSION_1_00_0; 631 } else { 632 error_setg(errp, 633 "Unsupported vector spec version '%s'", 634 cpu->cfg.vext_spec); 635 return; 636 } 637 } else { 638 qemu_log("vector version is not specified, " 639 "use the default value v1.0\n"); 640 } 641 set_vext_version(env, vext_version); 642 } 643 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 644 error_setg(errp, "Zve32f/Zve64f extension depends upon RVF."); 645 return; 646 } 647 if (cpu->cfg.ext_j) { 648 ext |= RVJ; 649 } 650 651 set_misa(env, env->misa_mxl, ext); 652 } 653 654 riscv_cpu_register_gdb_regs_for_features(cs); 655 656 qemu_init_vcpu(cs); 657 cpu_reset(cs); 658 659 mcc->parent_realize(dev, errp); 660 } 661 662 #ifndef CONFIG_USER_ONLY 663 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 664 { 665 RISCVCPU *cpu = RISCV_CPU(opaque); 666 CPURISCVState *env = &cpu->env; 667 668 if (irq < IRQ_LOCAL_MAX) { 669 switch (irq) { 670 case IRQ_U_SOFT: 671 case IRQ_S_SOFT: 672 case IRQ_VS_SOFT: 673 case IRQ_M_SOFT: 674 case IRQ_U_TIMER: 675 case IRQ_S_TIMER: 676 case IRQ_VS_TIMER: 677 case IRQ_M_TIMER: 678 case IRQ_U_EXT: 679 case IRQ_S_EXT: 680 case IRQ_VS_EXT: 681 case IRQ_M_EXT: 682 if (kvm_enabled()) { 683 kvm_riscv_set_irq(cpu, irq, level); 684 } else { 685 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 686 } 687 break; 688 default: 689 g_assert_not_reached(); 690 } 691 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 692 /* Require H-extension for handling guest local interrupts */ 693 if (!riscv_has_ext(env, RVH)) { 694 g_assert_not_reached(); 695 } 696 697 /* Compute bit position in HGEIP CSR */ 698 irq = irq - IRQ_LOCAL_MAX + 1; 699 if (env->geilen < irq) { 700 g_assert_not_reached(); 701 } 702 703 /* Update HGEIP CSR */ 704 env->hgeip &= ~((target_ulong)1 << irq); 705 if (level) { 706 env->hgeip |= (target_ulong)1 << irq; 707 } 708 709 /* Update mip.SGEIP bit */ 710 riscv_cpu_update_mip(cpu, MIP_SGEIP, 711 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 712 } else { 713 g_assert_not_reached(); 714 } 715 } 716 #endif /* CONFIG_USER_ONLY */ 717 718 static void riscv_cpu_init(Object *obj) 719 { 720 RISCVCPU *cpu = RISCV_CPU(obj); 721 722 cpu_set_cpustate_pointers(cpu); 723 724 #ifndef CONFIG_USER_ONLY 725 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 726 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 727 #endif /* CONFIG_USER_ONLY */ 728 } 729 730 static Property riscv_cpu_properties[] = { 731 /* Defaults for standard extensions */ 732 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 733 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 734 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 735 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 736 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 737 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 738 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 739 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 740 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 741 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 742 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 743 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 744 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 745 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 746 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 747 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 748 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 749 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 750 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 751 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 752 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 753 754 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 755 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 756 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 757 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 758 759 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 760 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 761 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 762 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 763 764 /* Vendor-specific custom extensions */ 765 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 766 767 /* These are experimental so mark with 'x-' */ 768 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 769 /* ePMP 0.9.3 */ 770 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 771 772 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 773 DEFINE_PROP_END_OF_LIST(), 774 }; 775 776 static gchar *riscv_gdb_arch_name(CPUState *cs) 777 { 778 RISCVCPU *cpu = RISCV_CPU(cs); 779 CPURISCVState *env = &cpu->env; 780 781 switch (riscv_cpu_mxl(env)) { 782 case MXL_RV32: 783 return g_strdup("riscv:rv32"); 784 case MXL_RV64: 785 case MXL_RV128: 786 return g_strdup("riscv:rv64"); 787 default: 788 g_assert_not_reached(); 789 } 790 } 791 792 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 793 { 794 RISCVCPU *cpu = RISCV_CPU(cs); 795 796 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 797 return cpu->dyn_csr_xml; 798 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 799 return cpu->dyn_vreg_xml; 800 } 801 802 return NULL; 803 } 804 805 #ifndef CONFIG_USER_ONLY 806 #include "hw/core/sysemu-cpu-ops.h" 807 808 static const struct SysemuCPUOps riscv_sysemu_ops = { 809 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 810 .write_elf64_note = riscv_cpu_write_elf64_note, 811 .write_elf32_note = riscv_cpu_write_elf32_note, 812 .legacy_vmsd = &vmstate_riscv_cpu, 813 }; 814 #endif 815 816 #include "hw/core/tcg-cpu-ops.h" 817 818 static const struct TCGCPUOps riscv_tcg_ops = { 819 .initialize = riscv_translate_init, 820 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 821 822 #ifndef CONFIG_USER_ONLY 823 .tlb_fill = riscv_cpu_tlb_fill, 824 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 825 .do_interrupt = riscv_cpu_do_interrupt, 826 .do_transaction_failed = riscv_cpu_do_transaction_failed, 827 .do_unaligned_access = riscv_cpu_do_unaligned_access, 828 #endif /* !CONFIG_USER_ONLY */ 829 }; 830 831 static void riscv_cpu_class_init(ObjectClass *c, void *data) 832 { 833 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 834 CPUClass *cc = CPU_CLASS(c); 835 DeviceClass *dc = DEVICE_CLASS(c); 836 837 device_class_set_parent_realize(dc, riscv_cpu_realize, 838 &mcc->parent_realize); 839 840 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 841 842 cc->class_by_name = riscv_cpu_class_by_name; 843 cc->has_work = riscv_cpu_has_work; 844 cc->dump_state = riscv_cpu_dump_state; 845 cc->set_pc = riscv_cpu_set_pc; 846 cc->gdb_read_register = riscv_cpu_gdb_read_register; 847 cc->gdb_write_register = riscv_cpu_gdb_write_register; 848 cc->gdb_num_core_regs = 33; 849 cc->gdb_stop_before_watchpoint = true; 850 cc->disas_set_info = riscv_cpu_disas_set_info; 851 #ifndef CONFIG_USER_ONLY 852 cc->sysemu_ops = &riscv_sysemu_ops; 853 #endif 854 cc->gdb_arch_name = riscv_gdb_arch_name; 855 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 856 cc->tcg_ops = &riscv_tcg_ops; 857 858 device_class_set_props(dc, riscv_cpu_properties); 859 } 860 861 char *riscv_isa_string(RISCVCPU *cpu) 862 { 863 int i; 864 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 865 char *isa_str = g_new(char, maxlen); 866 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 867 for (i = 0; i < sizeof(riscv_exts); i++) { 868 if (cpu->env.misa_ext & RV(riscv_exts[i])) { 869 *p++ = qemu_tolower(riscv_exts[i]); 870 } 871 } 872 *p = '\0'; 873 return isa_str; 874 } 875 876 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 877 { 878 ObjectClass *class_a = (ObjectClass *)a; 879 ObjectClass *class_b = (ObjectClass *)b; 880 const char *name_a, *name_b; 881 882 name_a = object_class_get_name(class_a); 883 name_b = object_class_get_name(class_b); 884 return strcmp(name_a, name_b); 885 } 886 887 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 888 { 889 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 890 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 891 892 qemu_printf("%.*s\n", len, typename); 893 } 894 895 void riscv_cpu_list(void) 896 { 897 GSList *list; 898 899 list = object_class_get_list(TYPE_RISCV_CPU, false); 900 list = g_slist_sort(list, riscv_cpu_list_compare); 901 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 902 g_slist_free(list); 903 } 904 905 #define DEFINE_CPU(type_name, initfn) \ 906 { \ 907 .name = type_name, \ 908 .parent = TYPE_RISCV_CPU, \ 909 .instance_init = initfn \ 910 } 911 912 static const TypeInfo riscv_cpu_type_infos[] = { 913 { 914 .name = TYPE_RISCV_CPU, 915 .parent = TYPE_CPU, 916 .instance_size = sizeof(RISCVCPU), 917 .instance_align = __alignof__(RISCVCPU), 918 .instance_init = riscv_cpu_init, 919 .abstract = true, 920 .class_size = sizeof(RISCVCPUClass), 921 .class_init = riscv_cpu_class_init, 922 }, 923 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 924 #if defined(CONFIG_KVM) 925 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 926 #endif 927 #if defined(TARGET_RISCV32) 928 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 929 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 930 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 931 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 932 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 933 #elif defined(TARGET_RISCV64) 934 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 935 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 936 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 937 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 938 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 939 #endif 940 }; 941 942 DEFINE_TYPES(riscv_cpu_type_infos) 943