xref: /openbmc/qemu/target/riscv/cpu.c (revision ca5aa28e)
1 /*
2  * QEMU RISC-V CPU
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
23 #include "qemu/log.h"
24 #include "cpu.h"
25 #include "cpu_vendorid.h"
26 #include "internals.h"
27 #include "exec/exec-all.h"
28 #include "qapi/error.h"
29 #include "qapi/visitor.h"
30 #include "qemu/error-report.h"
31 #include "hw/qdev-properties.h"
32 #include "hw/core/qdev-prop-internal.h"
33 #include "migration/vmstate.h"
34 #include "fpu/softfloat-helpers.h"
35 #include "sysemu/device_tree.h"
36 #include "sysemu/kvm.h"
37 #include "sysemu/tcg.h"
38 #include "kvm/kvm_riscv.h"
39 #include "tcg/tcg-cpu.h"
40 #include "tcg/tcg.h"
41 
42 /* RISC-V CPU definitions */
43 static const char riscv_single_letter_exts[] = "IEMAFDQCBPVH";
44 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
45                               RVC, RVS, RVU, RVH, RVJ, RVG, RVB, 0};
46 
47 /*
48  * From vector_helper.c
49  * Note that vector data is stored in host-endian 64-bit chunks,
50  * so addressing bytes needs a host-endian fixup.
51  */
52 #if HOST_BIG_ENDIAN
53 #define BYTE(x)   ((x) ^ 7)
54 #else
55 #define BYTE(x)   (x)
56 #endif
57 
58 bool riscv_cpu_is_32bit(RISCVCPU *cpu)
59 {
60     return riscv_cpu_mxl(&cpu->env) == MXL_RV32;
61 }
62 
63 /* Hash that stores general user set numeric options */
64 static GHashTable *general_user_opts;
65 
66 static void cpu_option_add_user_setting(const char *optname, uint32_t value)
67 {
68     g_hash_table_insert(general_user_opts, (gpointer)optname,
69                         GUINT_TO_POINTER(value));
70 }
71 
72 bool riscv_cpu_option_set(const char *optname)
73 {
74     return g_hash_table_contains(general_user_opts, optname);
75 }
76 
77 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
78     {#_name, _min_ver, CPU_CFG_OFFSET(_prop)}
79 
80 /*
81  * Here are the ordering rules of extension naming defined by RISC-V
82  * specification :
83  * 1. All extensions should be separated from other multi-letter extensions
84  *    by an underscore.
85  * 2. The first letter following the 'Z' conventionally indicates the most
86  *    closely related alphabetical extension category, IMAFDQLCBKJTPVH.
87  *    If multiple 'Z' extensions are named, they should be ordered first
88  *    by category, then alphabetically within a category.
89  * 3. Standard supervisor-level extensions (starts with 'S') should be
90  *    listed after standard unprivileged extensions.  If multiple
91  *    supervisor-level extensions are listed, they should be ordered
92  *    alphabetically.
93  * 4. Non-standard extensions (starts with 'X') must be listed after all
94  *    standard extensions. They must be separated from other multi-letter
95  *    extensions by an underscore.
96  *
97  * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
98  * instead.
99  */
100 const RISCVIsaExtData isa_edata_arr[] = {
101     ISA_EXT_DATA_ENTRY(zic64b, PRIV_VERSION_1_12_0, ext_zic64b),
102     ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_zicbom),
103     ISA_EXT_DATA_ENTRY(zicbop, PRIV_VERSION_1_12_0, ext_zicbop),
104     ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_zicboz),
105     ISA_EXT_DATA_ENTRY(ziccamoa, PRIV_VERSION_1_11_0, has_priv_1_11),
106     ISA_EXT_DATA_ENTRY(ziccif, PRIV_VERSION_1_11_0, has_priv_1_11),
107     ISA_EXT_DATA_ENTRY(zicclsm, PRIV_VERSION_1_11_0, has_priv_1_11),
108     ISA_EXT_DATA_ENTRY(ziccrse, PRIV_VERSION_1_11_0, has_priv_1_11),
109     ISA_EXT_DATA_ENTRY(zicfilp, PRIV_VERSION_1_12_0, ext_zicfilp),
110     ISA_EXT_DATA_ENTRY(zicfiss, PRIV_VERSION_1_13_0, ext_zicfiss),
111     ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
112     ISA_EXT_DATA_ENTRY(zicntr, PRIV_VERSION_1_12_0, ext_zicntr),
113     ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_zicsr),
114     ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_zifencei),
115     ISA_EXT_DATA_ENTRY(zihintntl, PRIV_VERSION_1_10_0, ext_zihintntl),
116     ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
117     ISA_EXT_DATA_ENTRY(zihpm, PRIV_VERSION_1_12_0, ext_zihpm),
118     ISA_EXT_DATA_ENTRY(zimop, PRIV_VERSION_1_13_0, ext_zimop),
119     ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul),
120     ISA_EXT_DATA_ENTRY(za64rs, PRIV_VERSION_1_12_0, has_priv_1_12),
121     ISA_EXT_DATA_ENTRY(zaamo, PRIV_VERSION_1_12_0, ext_zaamo),
122     ISA_EXT_DATA_ENTRY(zabha, PRIV_VERSION_1_13_0, ext_zabha),
123     ISA_EXT_DATA_ENTRY(zacas, PRIV_VERSION_1_12_0, ext_zacas),
124     ISA_EXT_DATA_ENTRY(zama16b, PRIV_VERSION_1_13_0, ext_zama16b),
125     ISA_EXT_DATA_ENTRY(zalrsc, PRIV_VERSION_1_12_0, ext_zalrsc),
126     ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
127     ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa),
128     ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin),
129     ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh),
130     ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin),
131     ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx),
132     ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx),
133     ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca),
134     ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb),
135     ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf),
136     ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd),
137     ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce),
138     ISA_EXT_DATA_ENTRY(zcmop, PRIV_VERSION_1_13_0, ext_zcmop),
139     ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp),
140     ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt),
141     ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba),
142     ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb),
143     ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc),
144     ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb),
145     ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc),
146     ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx),
147     ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs),
148     ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk),
149     ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn),
150     ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd),
151     ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne),
152     ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh),
153     ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr),
154     ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks),
155     ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
156     ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
157     ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
158     ISA_EXT_DATA_ENTRY(ztso, PRIV_VERSION_1_12_0, ext_ztso),
159     ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb),
160     ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc),
161     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
162     ISA_EXT_DATA_ENTRY(zve32x, PRIV_VERSION_1_10_0, ext_zve32x),
163     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
164     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
165     ISA_EXT_DATA_ENTRY(zve64x, PRIV_VERSION_1_10_0, ext_zve64x),
166     ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin),
167     ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma),
168     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
169     ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
170     ISA_EXT_DATA_ENTRY(zvkb, PRIV_VERSION_1_12_0, ext_zvkb),
171     ISA_EXT_DATA_ENTRY(zvkg, PRIV_VERSION_1_12_0, ext_zvkg),
172     ISA_EXT_DATA_ENTRY(zvkn, PRIV_VERSION_1_12_0, ext_zvkn),
173     ISA_EXT_DATA_ENTRY(zvknc, PRIV_VERSION_1_12_0, ext_zvknc),
174     ISA_EXT_DATA_ENTRY(zvkned, PRIV_VERSION_1_12_0, ext_zvkned),
175     ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng),
176     ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha),
177     ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb),
178     ISA_EXT_DATA_ENTRY(zvks, PRIV_VERSION_1_12_0, ext_zvks),
179     ISA_EXT_DATA_ENTRY(zvksc, PRIV_VERSION_1_12_0, ext_zvksc),
180     ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed),
181     ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg),
182     ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh),
183     ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt),
184     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
185     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
186     ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
187     ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf),
188     ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp),
189     ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
190     ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
191     ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11),
192     ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
193     ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12),
194     ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
195     ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12),
196     ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12),
197     ISA_EXT_DATA_ENTRY(svade, PRIV_VERSION_1_11_0, ext_svade),
198     ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
199     ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
200     ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
201     ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
202     ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc),
203     ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
204     ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
205     ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
206     ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo),
207     ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
208     ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
209     ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv),
210     ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac),
211     ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
212     ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
213     ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
214     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
215 
216     DEFINE_PROP_END_OF_LIST(),
217 };
218 
219 bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset)
220 {
221     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
222 
223     return *ext_enabled;
224 }
225 
226 void isa_ext_update_enabled(RISCVCPU *cpu, uint32_t ext_offset, bool en)
227 {
228     bool *ext_enabled = (void *)&cpu->cfg + ext_offset;
229 
230     *ext_enabled = en;
231 }
232 
233 bool riscv_cpu_is_vendor(Object *cpu_obj)
234 {
235     return object_dynamic_cast(cpu_obj, TYPE_RISCV_VENDOR_CPU) != NULL;
236 }
237 
238 const char * const riscv_int_regnames[] = {
239     "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
240     "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
241     "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
242     "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
243     "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
244 };
245 
246 const char * const riscv_int_regnamesh[] = {
247     "x0h/zeroh", "x1h/rah",  "x2h/sph",   "x3h/gph",   "x4h/tph",  "x5h/t0h",
248     "x6h/t1h",   "x7h/t2h",  "x8h/s0h",   "x9h/s1h",   "x10h/a0h", "x11h/a1h",
249     "x12h/a2h",  "x13h/a3h", "x14h/a4h",  "x15h/a5h",  "x16h/a6h", "x17h/a7h",
250     "x18h/s2h",  "x19h/s3h", "x20h/s4h",  "x21h/s5h",  "x22h/s6h", "x23h/s7h",
251     "x24h/s8h",  "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
252     "x30h/t5h",  "x31h/t6h"
253 };
254 
255 const char * const riscv_fpr_regnames[] = {
256     "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
257     "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
258     "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
259     "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
260     "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
261     "f30/ft10", "f31/ft11"
262 };
263 
264 const char * const riscv_rvv_regnames[] = {
265   "v0",  "v1",  "v2",  "v3",  "v4",  "v5",  "v6",
266   "v7",  "v8",  "v9",  "v10", "v11", "v12", "v13",
267   "v14", "v15", "v16", "v17", "v18", "v19", "v20",
268   "v21", "v22", "v23", "v24", "v25", "v26", "v27",
269   "v28", "v29", "v30", "v31"
270 };
271 
272 static const char * const riscv_excp_names[] = {
273     "misaligned_fetch",
274     "fault_fetch",
275     "illegal_instruction",
276     "breakpoint",
277     "misaligned_load",
278     "fault_load",
279     "misaligned_store",
280     "fault_store",
281     "user_ecall",
282     "supervisor_ecall",
283     "hypervisor_ecall",
284     "machine_ecall",
285     "exec_page_fault",
286     "load_page_fault",
287     "reserved",
288     "store_page_fault",
289     "reserved",
290     "reserved",
291     "reserved",
292     "reserved",
293     "guest_exec_page_fault",
294     "guest_load_page_fault",
295     "reserved",
296     "guest_store_page_fault",
297 };
298 
299 static const char * const riscv_intr_names[] = {
300     "u_software",
301     "s_software",
302     "vs_software",
303     "m_software",
304     "u_timer",
305     "s_timer",
306     "vs_timer",
307     "m_timer",
308     "u_external",
309     "s_external",
310     "vs_external",
311     "m_external",
312     "reserved",
313     "reserved",
314     "reserved",
315     "reserved"
316 };
317 
318 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
319 {
320     if (async) {
321         return (cause < ARRAY_SIZE(riscv_intr_names)) ?
322                riscv_intr_names[cause] : "(unknown)";
323     } else {
324         return (cause < ARRAY_SIZE(riscv_excp_names)) ?
325                riscv_excp_names[cause] : "(unknown)";
326     }
327 }
328 
329 void riscv_cpu_set_misa_ext(CPURISCVState *env, uint32_t ext)
330 {
331     env->misa_ext_mask = env->misa_ext = ext;
332 }
333 
334 int riscv_cpu_max_xlen(RISCVCPUClass *mcc)
335 {
336     return 16 << mcc->misa_mxl_max;
337 }
338 
339 #ifndef CONFIG_USER_ONLY
340 static uint8_t satp_mode_from_str(const char *satp_mode_str)
341 {
342     if (!strncmp(satp_mode_str, "mbare", 5)) {
343         return VM_1_10_MBARE;
344     }
345 
346     if (!strncmp(satp_mode_str, "sv32", 4)) {
347         return VM_1_10_SV32;
348     }
349 
350     if (!strncmp(satp_mode_str, "sv39", 4)) {
351         return VM_1_10_SV39;
352     }
353 
354     if (!strncmp(satp_mode_str, "sv48", 4)) {
355         return VM_1_10_SV48;
356     }
357 
358     if (!strncmp(satp_mode_str, "sv57", 4)) {
359         return VM_1_10_SV57;
360     }
361 
362     if (!strncmp(satp_mode_str, "sv64", 4)) {
363         return VM_1_10_SV64;
364     }
365 
366     g_assert_not_reached();
367 }
368 
369 uint8_t satp_mode_max_from_map(uint32_t map)
370 {
371     /*
372      * 'map = 0' will make us return (31 - 32), which C will
373      * happily overflow to UINT_MAX. There's no good result to
374      * return if 'map = 0' (e.g. returning 0 will be ambiguous
375      * with the result for 'map = 1').
376      *
377      * Assert out if map = 0. Callers will have to deal with
378      * it outside of this function.
379      */
380     g_assert(map > 0);
381 
382     /* map here has at least one bit set, so no problem with clz */
383     return 31 - __builtin_clz(map);
384 }
385 
386 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
387 {
388     if (is_32_bit) {
389         switch (satp_mode) {
390         case VM_1_10_SV32:
391             return "sv32";
392         case VM_1_10_MBARE:
393             return "none";
394         }
395     } else {
396         switch (satp_mode) {
397         case VM_1_10_SV64:
398             return "sv64";
399         case VM_1_10_SV57:
400             return "sv57";
401         case VM_1_10_SV48:
402             return "sv48";
403         case VM_1_10_SV39:
404             return "sv39";
405         case VM_1_10_MBARE:
406             return "none";
407         }
408     }
409 
410     g_assert_not_reached();
411 }
412 
413 static void set_satp_mode_max_supported(RISCVCPU *cpu,
414                                         uint8_t satp_mode)
415 {
416     bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
417     const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
418 
419     for (int i = 0; i <= satp_mode; ++i) {
420         if (valid_vm[i]) {
421             cpu->cfg.satp_mode.supported |= (1 << i);
422         }
423     }
424 }
425 
426 /* Set the satp mode to the max supported */
427 static void set_satp_mode_default_map(RISCVCPU *cpu)
428 {
429     /*
430      * Bare CPUs do not default to the max available.
431      * Users must set a valid satp_mode in the command
432      * line.
433      */
434     if (object_dynamic_cast(OBJECT(cpu), TYPE_RISCV_BARE_CPU) != NULL) {
435         warn_report("No satp mode set. Defaulting to 'bare'");
436         cpu->cfg.satp_mode.map = (1 << VM_1_10_MBARE);
437         return;
438     }
439 
440     cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;
441 }
442 #endif
443 
444 static void riscv_max_cpu_init(Object *obj)
445 {
446     RISCVCPU *cpu = RISCV_CPU(obj);
447     CPURISCVState *env = &cpu->env;
448 
449     cpu->cfg.mmu = true;
450     cpu->cfg.pmp = true;
451 
452     env->priv_ver = PRIV_VERSION_LATEST;
453 #ifndef CONFIG_USER_ONLY
454     set_satp_mode_max_supported(RISCV_CPU(obj),
455         riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
456         VM_1_10_SV32 : VM_1_10_SV57);
457 #endif
458 }
459 
460 #if defined(TARGET_RISCV64)
461 static void rv64_base_cpu_init(Object *obj)
462 {
463     RISCVCPU *cpu = RISCV_CPU(obj);
464     CPURISCVState *env = &cpu->env;
465 
466     cpu->cfg.mmu = true;
467     cpu->cfg.pmp = true;
468 
469     /* Set latest version of privileged specification */
470     env->priv_ver = PRIV_VERSION_LATEST;
471 #ifndef CONFIG_USER_ONLY
472     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
473 #endif
474 }
475 
476 static void rv64_sifive_u_cpu_init(Object *obj)
477 {
478     RISCVCPU *cpu = RISCV_CPU(obj);
479     CPURISCVState *env = &cpu->env;
480     riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
481     env->priv_ver = PRIV_VERSION_1_10_0;
482 #ifndef CONFIG_USER_ONLY
483     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
484 #endif
485 
486     /* inherited from parent obj via riscv_cpu_init() */
487     cpu->cfg.ext_zifencei = true;
488     cpu->cfg.ext_zicsr = true;
489     cpu->cfg.mmu = true;
490     cpu->cfg.pmp = true;
491 }
492 
493 static void rv64_sifive_e_cpu_init(Object *obj)
494 {
495     CPURISCVState *env = &RISCV_CPU(obj)->env;
496     RISCVCPU *cpu = RISCV_CPU(obj);
497 
498     riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
499     env->priv_ver = PRIV_VERSION_1_10_0;
500 #ifndef CONFIG_USER_ONLY
501     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
502 #endif
503 
504     /* inherited from parent obj via riscv_cpu_init() */
505     cpu->cfg.ext_zifencei = true;
506     cpu->cfg.ext_zicsr = true;
507     cpu->cfg.pmp = true;
508 }
509 
510 static void rv64_thead_c906_cpu_init(Object *obj)
511 {
512     CPURISCVState *env = &RISCV_CPU(obj)->env;
513     RISCVCPU *cpu = RISCV_CPU(obj);
514 
515     riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU);
516     env->priv_ver = PRIV_VERSION_1_11_0;
517 
518     cpu->cfg.ext_zfa = true;
519     cpu->cfg.ext_zfh = true;
520     cpu->cfg.mmu = true;
521     cpu->cfg.ext_xtheadba = true;
522     cpu->cfg.ext_xtheadbb = true;
523     cpu->cfg.ext_xtheadbs = true;
524     cpu->cfg.ext_xtheadcmo = true;
525     cpu->cfg.ext_xtheadcondmov = true;
526     cpu->cfg.ext_xtheadfmemidx = true;
527     cpu->cfg.ext_xtheadmac = true;
528     cpu->cfg.ext_xtheadmemidx = true;
529     cpu->cfg.ext_xtheadmempair = true;
530     cpu->cfg.ext_xtheadsync = true;
531 
532     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
533 #ifndef CONFIG_USER_ONLY
534     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
535     th_register_custom_csrs(cpu);
536 #endif
537 
538     /* inherited from parent obj via riscv_cpu_init() */
539     cpu->cfg.pmp = true;
540 }
541 
542 static void rv64_veyron_v1_cpu_init(Object *obj)
543 {
544     CPURISCVState *env = &RISCV_CPU(obj)->env;
545     RISCVCPU *cpu = RISCV_CPU(obj);
546 
547     riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH);
548     env->priv_ver = PRIV_VERSION_1_12_0;
549 
550     /* Enable ISA extensions */
551     cpu->cfg.mmu = true;
552     cpu->cfg.ext_zifencei = true;
553     cpu->cfg.ext_zicsr = true;
554     cpu->cfg.pmp = true;
555     cpu->cfg.ext_zicbom = true;
556     cpu->cfg.cbom_blocksize = 64;
557     cpu->cfg.cboz_blocksize = 64;
558     cpu->cfg.ext_zicboz = true;
559     cpu->cfg.ext_smaia = true;
560     cpu->cfg.ext_ssaia = true;
561     cpu->cfg.ext_sscofpmf = true;
562     cpu->cfg.ext_sstc = true;
563     cpu->cfg.ext_svinval = true;
564     cpu->cfg.ext_svnapot = true;
565     cpu->cfg.ext_svpbmt = true;
566     cpu->cfg.ext_smstateen = true;
567     cpu->cfg.ext_zba = true;
568     cpu->cfg.ext_zbb = true;
569     cpu->cfg.ext_zbc = true;
570     cpu->cfg.ext_zbs = true;
571     cpu->cfg.ext_XVentanaCondOps = true;
572 
573     cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
574     cpu->cfg.marchid = VEYRON_V1_MARCHID;
575     cpu->cfg.mimpid = VEYRON_V1_MIMPID;
576 
577 #ifndef CONFIG_USER_ONLY
578     set_satp_mode_max_supported(cpu, VM_1_10_SV48);
579 #endif
580 }
581 
582 #ifdef CONFIG_TCG
583 static void rv128_base_cpu_init(Object *obj)
584 {
585     RISCVCPU *cpu = RISCV_CPU(obj);
586     CPURISCVState *env = &cpu->env;
587 
588     if (qemu_tcg_mttcg_enabled()) {
589         /* Missing 128-bit aligned atomics */
590         error_report("128-bit RISC-V currently does not work with Multi "
591                      "Threaded TCG. Please use: -accel tcg,thread=single");
592         exit(EXIT_FAILURE);
593     }
594 
595     cpu->cfg.mmu = true;
596     cpu->cfg.pmp = true;
597 
598     /* Set latest version of privileged specification */
599     env->priv_ver = PRIV_VERSION_LATEST;
600 #ifndef CONFIG_USER_ONLY
601     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
602 #endif
603 }
604 #endif /* CONFIG_TCG */
605 
606 static void rv64i_bare_cpu_init(Object *obj)
607 {
608     CPURISCVState *env = &RISCV_CPU(obj)->env;
609     riscv_cpu_set_misa_ext(env, RVI);
610 }
611 
612 static void rv64e_bare_cpu_init(Object *obj)
613 {
614     CPURISCVState *env = &RISCV_CPU(obj)->env;
615     riscv_cpu_set_misa_ext(env, RVE);
616 }
617 
618 #endif /* !TARGET_RISCV64 */
619 
620 #if defined(TARGET_RISCV32) || \
621     (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
622 
623 static void rv32_base_cpu_init(Object *obj)
624 {
625     RISCVCPU *cpu = RISCV_CPU(obj);
626     CPURISCVState *env = &cpu->env;
627 
628     cpu->cfg.mmu = true;
629     cpu->cfg.pmp = true;
630 
631     /* Set latest version of privileged specification */
632     env->priv_ver = PRIV_VERSION_LATEST;
633 #ifndef CONFIG_USER_ONLY
634     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
635 #endif
636 }
637 
638 static void rv32_sifive_u_cpu_init(Object *obj)
639 {
640     RISCVCPU *cpu = RISCV_CPU(obj);
641     CPURISCVState *env = &cpu->env;
642     riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
643     env->priv_ver = PRIV_VERSION_1_10_0;
644 #ifndef CONFIG_USER_ONLY
645     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
646 #endif
647 
648     /* inherited from parent obj via riscv_cpu_init() */
649     cpu->cfg.ext_zifencei = true;
650     cpu->cfg.ext_zicsr = true;
651     cpu->cfg.mmu = true;
652     cpu->cfg.pmp = true;
653 }
654 
655 static void rv32_sifive_e_cpu_init(Object *obj)
656 {
657     CPURISCVState *env = &RISCV_CPU(obj)->env;
658     RISCVCPU *cpu = RISCV_CPU(obj);
659 
660     riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVC | RVU);
661     env->priv_ver = PRIV_VERSION_1_10_0;
662 #ifndef CONFIG_USER_ONLY
663     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
664 #endif
665 
666     /* inherited from parent obj via riscv_cpu_init() */
667     cpu->cfg.ext_zifencei = true;
668     cpu->cfg.ext_zicsr = true;
669     cpu->cfg.pmp = true;
670 }
671 
672 static void rv32_ibex_cpu_init(Object *obj)
673 {
674     CPURISCVState *env = &RISCV_CPU(obj)->env;
675     RISCVCPU *cpu = RISCV_CPU(obj);
676 
677     riscv_cpu_set_misa_ext(env, RVI | RVM | RVC | RVU);
678     env->priv_ver = PRIV_VERSION_1_12_0;
679 #ifndef CONFIG_USER_ONLY
680     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
681 #endif
682     /* inherited from parent obj via riscv_cpu_init() */
683     cpu->cfg.ext_zifencei = true;
684     cpu->cfg.ext_zicsr = true;
685     cpu->cfg.pmp = true;
686     cpu->cfg.ext_smepmp = true;
687 
688     cpu->cfg.ext_zba = true;
689     cpu->cfg.ext_zbb = true;
690     cpu->cfg.ext_zbc = true;
691     cpu->cfg.ext_zbs = true;
692 }
693 
694 static void rv32_imafcu_nommu_cpu_init(Object *obj)
695 {
696     CPURISCVState *env = &RISCV_CPU(obj)->env;
697     RISCVCPU *cpu = RISCV_CPU(obj);
698 
699     riscv_cpu_set_misa_ext(env, RVI | RVM | RVA | RVF | RVC | RVU);
700     env->priv_ver = PRIV_VERSION_1_10_0;
701 #ifndef CONFIG_USER_ONLY
702     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
703 #endif
704 
705     /* inherited from parent obj via riscv_cpu_init() */
706     cpu->cfg.ext_zifencei = true;
707     cpu->cfg.ext_zicsr = true;
708     cpu->cfg.pmp = true;
709 }
710 
711 static void rv32i_bare_cpu_init(Object *obj)
712 {
713     CPURISCVState *env = &RISCV_CPU(obj)->env;
714     riscv_cpu_set_misa_ext(env, RVI);
715 }
716 
717 static void rv32e_bare_cpu_init(Object *obj)
718 {
719     CPURISCVState *env = &RISCV_CPU(obj)->env;
720     riscv_cpu_set_misa_ext(env, RVE);
721 }
722 #endif
723 
724 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
725 {
726     ObjectClass *oc;
727     char *typename;
728     char **cpuname;
729 
730     cpuname = g_strsplit(cpu_model, ",", 1);
731     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
732     oc = object_class_by_name(typename);
733     g_strfreev(cpuname);
734     g_free(typename);
735 
736     return oc;
737 }
738 
739 char *riscv_cpu_get_name(RISCVCPU *cpu)
740 {
741     RISCVCPUClass *rcc = RISCV_CPU_GET_CLASS(cpu);
742     const char *typename = object_class_get_name(OBJECT_CLASS(rcc));
743 
744     g_assert(g_str_has_suffix(typename, RISCV_CPU_TYPE_SUFFIX));
745 
746     return cpu_model_from_type(typename);
747 }
748 
749 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
750 {
751     RISCVCPU *cpu = RISCV_CPU(cs);
752     CPURISCVState *env = &cpu->env;
753     int i, j;
754     uint8_t *p;
755 
756 #if !defined(CONFIG_USER_ONLY)
757     if (riscv_has_ext(env, RVH)) {
758         qemu_fprintf(f, " %s %d\n", "V      =  ", env->virt_enabled);
759     }
760 #endif
761     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
762 #ifndef CONFIG_USER_ONLY
763     {
764         static const int dump_csrs[] = {
765             CSR_MHARTID,
766             CSR_MSTATUS,
767             CSR_MSTATUSH,
768             /*
769              * CSR_SSTATUS is intentionally omitted here as its value
770              * can be figured out by looking at CSR_MSTATUS
771              */
772             CSR_HSTATUS,
773             CSR_VSSTATUS,
774             CSR_MIP,
775             CSR_MIE,
776             CSR_MIDELEG,
777             CSR_HIDELEG,
778             CSR_MEDELEG,
779             CSR_HEDELEG,
780             CSR_MTVEC,
781             CSR_STVEC,
782             CSR_VSTVEC,
783             CSR_MEPC,
784             CSR_SEPC,
785             CSR_VSEPC,
786             CSR_MCAUSE,
787             CSR_SCAUSE,
788             CSR_VSCAUSE,
789             CSR_MTVAL,
790             CSR_STVAL,
791             CSR_HTVAL,
792             CSR_MTVAL2,
793             CSR_MSCRATCH,
794             CSR_SSCRATCH,
795             CSR_SATP,
796             CSR_MMTE,
797             CSR_UPMBASE,
798             CSR_UPMMASK,
799             CSR_SPMBASE,
800             CSR_SPMMASK,
801             CSR_MPMBASE,
802             CSR_MPMMASK,
803         };
804 
805         for (i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
806             int csrno = dump_csrs[i];
807             target_ulong val = 0;
808             RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
809 
810             /*
811              * Rely on the smode, hmode, etc, predicates within csr.c
812              * to do the filtering of the registers that are present.
813              */
814             if (res == RISCV_EXCP_NONE) {
815                 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
816                              csr_ops[csrno].name, val);
817             }
818         }
819     }
820 #endif
821 
822     for (i = 0; i < 32; i++) {
823         qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
824                      riscv_int_regnames[i], env->gpr[i]);
825         if ((i & 3) == 3) {
826             qemu_fprintf(f, "\n");
827         }
828     }
829     if (flags & CPU_DUMP_FPU) {
830         target_ulong val = 0;
831         RISCVException res = riscv_csrrw_debug(env, CSR_FCSR, &val, 0, 0);
832         if (res == RISCV_EXCP_NONE) {
833             qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
834                     csr_ops[CSR_FCSR].name, val);
835         }
836         for (i = 0; i < 32; i++) {
837             qemu_fprintf(f, " %-8s %016" PRIx64,
838                          riscv_fpr_regnames[i], env->fpr[i]);
839             if ((i & 3) == 3) {
840                 qemu_fprintf(f, "\n");
841             }
842         }
843     }
844     if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) {
845         static const int dump_rvv_csrs[] = {
846                     CSR_VSTART,
847                     CSR_VXSAT,
848                     CSR_VXRM,
849                     CSR_VCSR,
850                     CSR_VL,
851                     CSR_VTYPE,
852                     CSR_VLENB,
853                 };
854         for (i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) {
855             int csrno = dump_rvv_csrs[i];
856             target_ulong val = 0;
857             RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
858 
859             /*
860              * Rely on the smode, hmode, etc, predicates within csr.c
861              * to do the filtering of the registers that are present.
862              */
863             if (res == RISCV_EXCP_NONE) {
864                 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
865                              csr_ops[csrno].name, val);
866             }
867         }
868         uint16_t vlenb = cpu->cfg.vlenb;
869 
870         for (i = 0; i < 32; i++) {
871             qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]);
872             p = (uint8_t *)env->vreg;
873             for (j = vlenb - 1 ; j >= 0; j--) {
874                 qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j)));
875             }
876             qemu_fprintf(f, "\n");
877         }
878     }
879 }
880 
881 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
882 {
883     RISCVCPU *cpu = RISCV_CPU(cs);
884     CPURISCVState *env = &cpu->env;
885 
886     if (env->xl == MXL_RV32) {
887         env->pc = (int32_t)value;
888     } else {
889         env->pc = value;
890     }
891 }
892 
893 static vaddr riscv_cpu_get_pc(CPUState *cs)
894 {
895     RISCVCPU *cpu = RISCV_CPU(cs);
896     CPURISCVState *env = &cpu->env;
897 
898     /* Match cpu_get_tb_cpu_state. */
899     if (env->xl == MXL_RV32) {
900         return env->pc & UINT32_MAX;
901     }
902     return env->pc;
903 }
904 
905 bool riscv_cpu_has_work(CPUState *cs)
906 {
907 #ifndef CONFIG_USER_ONLY
908     RISCVCPU *cpu = RISCV_CPU(cs);
909     CPURISCVState *env = &cpu->env;
910     /*
911      * Definition of the WFI instruction requires it to ignore the privilege
912      * mode and delegation registers, but respect individual enables
913      */
914     return riscv_cpu_all_pending(env) != 0 ||
915         riscv_cpu_sirq_pending(env) != RISCV_EXCP_NONE ||
916         riscv_cpu_vsirq_pending(env) != RISCV_EXCP_NONE;
917 #else
918     return true;
919 #endif
920 }
921 
922 static int riscv_cpu_mmu_index(CPUState *cs, bool ifetch)
923 {
924     return riscv_env_mmu_index(cpu_env(cs), ifetch);
925 }
926 
927 static void riscv_cpu_reset_hold(Object *obj, ResetType type)
928 {
929 #ifndef CONFIG_USER_ONLY
930     uint8_t iprio;
931     int i, irq, rdzero;
932 #endif
933     CPUState *cs = CPU(obj);
934     RISCVCPU *cpu = RISCV_CPU(cs);
935     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
936     CPURISCVState *env = &cpu->env;
937 
938     if (mcc->parent_phases.hold) {
939         mcc->parent_phases.hold(obj, type);
940     }
941 #ifndef CONFIG_USER_ONLY
942     env->misa_mxl = mcc->misa_mxl_max;
943     env->priv = PRV_M;
944     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
945     if (env->misa_mxl > MXL_RV32) {
946         /*
947          * The reset status of SXL/UXL is undefined, but mstatus is WARL
948          * and we must ensure that the value after init is valid for read.
949          */
950         env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
951         env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
952         if (riscv_has_ext(env, RVH)) {
953             env->vsstatus = set_field(env->vsstatus,
954                                       MSTATUS64_SXL, env->misa_mxl);
955             env->vsstatus = set_field(env->vsstatus,
956                                       MSTATUS64_UXL, env->misa_mxl);
957             env->mstatus_hs = set_field(env->mstatus_hs,
958                                         MSTATUS64_SXL, env->misa_mxl);
959             env->mstatus_hs = set_field(env->mstatus_hs,
960                                         MSTATUS64_UXL, env->misa_mxl);
961         }
962     }
963     env->mcause = 0;
964     env->miclaim = MIP_SGEIP;
965     env->pc = env->resetvec;
966     env->bins = 0;
967     env->two_stage_lookup = false;
968 
969     env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
970                    (!cpu->cfg.ext_svade && cpu->cfg.ext_svadu ?
971                     MENVCFG_ADUE : 0);
972     env->henvcfg = 0;
973 
974     /* Initialized default priorities of local interrupts. */
975     for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
976         iprio = riscv_cpu_default_priority(i);
977         env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
978         env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
979         env->hviprio[i] = 0;
980     }
981     i = 0;
982     while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) {
983         if (!rdzero) {
984             env->hviprio[irq] = env->miprio[irq];
985         }
986         i++;
987     }
988     /* mmte is supposed to have pm.current hardwired to 1 */
989     env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
990 
991     /*
992      * Bits 10, 6, 2 and 12 of mideleg are read only 1 when the Hypervisor
993      * extension is enabled.
994      */
995     if (riscv_has_ext(env, RVH)) {
996         env->mideleg |= HS_MODE_INTERRUPTS;
997     }
998 
999     /*
1000      * Clear mseccfg and unlock all the PMP entries upon reset.
1001      * This is allowed as per the priv and smepmp specifications
1002      * and is needed to clear stale entries across reboots.
1003      */
1004     if (riscv_cpu_cfg(env)->ext_smepmp) {
1005         env->mseccfg = 0;
1006     }
1007 
1008     pmp_unlock_entries(env);
1009 #else
1010     env->priv = PRV_U;
1011     env->senvcfg = 0;
1012     env->menvcfg = 0;
1013 #endif
1014 
1015     /* on reset elp is clear */
1016     env->elp = false;
1017     /* on reset ssp is set to 0 */
1018     env->ssp = 0;
1019 
1020     env->xl = riscv_cpu_mxl(env);
1021     riscv_cpu_update_mask(env);
1022     cs->exception_index = RISCV_EXCP_NONE;
1023     env->load_res = -1;
1024     set_default_nan_mode(1, &env->fp_status);
1025     env->vill = true;
1026 
1027 #ifndef CONFIG_USER_ONLY
1028     if (cpu->cfg.debug) {
1029         riscv_trigger_reset_hold(env);
1030     }
1031 
1032     if (kvm_enabled()) {
1033         kvm_riscv_reset_vcpu(cpu);
1034     }
1035 #endif
1036 }
1037 
1038 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
1039 {
1040     RISCVCPU *cpu = RISCV_CPU(s);
1041     CPURISCVState *env = &cpu->env;
1042     info->target_info = &cpu->cfg;
1043 
1044     switch (env->xl) {
1045     case MXL_RV32:
1046         info->print_insn = print_insn_riscv32;
1047         break;
1048     case MXL_RV64:
1049         info->print_insn = print_insn_riscv64;
1050         break;
1051     case MXL_RV128:
1052         info->print_insn = print_insn_riscv128;
1053         break;
1054     default:
1055         g_assert_not_reached();
1056     }
1057 }
1058 
1059 #ifndef CONFIG_USER_ONLY
1060 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
1061 {
1062     bool rv32 = riscv_cpu_is_32bit(cpu);
1063     uint8_t satp_mode_map_max, satp_mode_supported_max;
1064 
1065     /* The CPU wants the OS to decide which satp mode to use */
1066     if (cpu->cfg.satp_mode.supported == 0) {
1067         return;
1068     }
1069 
1070     satp_mode_supported_max =
1071                     satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
1072 
1073     if (cpu->cfg.satp_mode.map == 0) {
1074         if (cpu->cfg.satp_mode.init == 0) {
1075             /* If unset by the user, we fallback to the default satp mode. */
1076             set_satp_mode_default_map(cpu);
1077         } else {
1078             /*
1079              * Find the lowest level that was disabled and then enable the
1080              * first valid level below which can be found in
1081              * valid_vm_1_10_32/64.
1082              */
1083             for (int i = 1; i < 16; ++i) {
1084                 if ((cpu->cfg.satp_mode.init & (1 << i)) &&
1085                     (cpu->cfg.satp_mode.supported & (1 << i))) {
1086                     for (int j = i - 1; j >= 0; --j) {
1087                         if (cpu->cfg.satp_mode.supported & (1 << j)) {
1088                             cpu->cfg.satp_mode.map |= (1 << j);
1089                             break;
1090                         }
1091                     }
1092                     break;
1093                 }
1094             }
1095         }
1096     }
1097 
1098     satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
1099 
1100     /* Make sure the user asked for a supported configuration (HW and qemu) */
1101     if (satp_mode_map_max > satp_mode_supported_max) {
1102         error_setg(errp, "satp_mode %s is higher than hw max capability %s",
1103                    satp_mode_str(satp_mode_map_max, rv32),
1104                    satp_mode_str(satp_mode_supported_max, rv32));
1105         return;
1106     }
1107 
1108     /*
1109      * Make sure the user did not ask for an invalid configuration as per
1110      * the specification.
1111      */
1112     if (!rv32) {
1113         for (int i = satp_mode_map_max - 1; i >= 0; --i) {
1114             if (!(cpu->cfg.satp_mode.map & (1 << i)) &&
1115                 (cpu->cfg.satp_mode.init & (1 << i)) &&
1116                 (cpu->cfg.satp_mode.supported & (1 << i))) {
1117                 error_setg(errp, "cannot disable %s satp mode if %s "
1118                            "is enabled", satp_mode_str(i, false),
1119                            satp_mode_str(satp_mode_map_max, false));
1120                 return;
1121             }
1122         }
1123     }
1124 
1125     /* Finally expand the map so that all valid modes are set */
1126     for (int i = satp_mode_map_max - 1; i >= 0; --i) {
1127         if (cpu->cfg.satp_mode.supported & (1 << i)) {
1128             cpu->cfg.satp_mode.map |= (1 << i);
1129         }
1130     }
1131 }
1132 #endif
1133 
1134 void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
1135 {
1136     Error *local_err = NULL;
1137 
1138 #ifndef CONFIG_USER_ONLY
1139     riscv_cpu_satp_mode_finalize(cpu, &local_err);
1140     if (local_err != NULL) {
1141         error_propagate(errp, local_err);
1142         return;
1143     }
1144 #endif
1145 
1146     if (tcg_enabled()) {
1147         riscv_tcg_cpu_finalize_features(cpu, &local_err);
1148         if (local_err != NULL) {
1149             error_propagate(errp, local_err);
1150             return;
1151         }
1152         riscv_tcg_cpu_finalize_dynamic_decoder(cpu);
1153     } else if (kvm_enabled()) {
1154         riscv_kvm_cpu_finalize_features(cpu, &local_err);
1155         if (local_err != NULL) {
1156             error_propagate(errp, local_err);
1157             return;
1158         }
1159     }
1160 }
1161 
1162 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
1163 {
1164     CPUState *cs = CPU(dev);
1165     RISCVCPU *cpu = RISCV_CPU(dev);
1166     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
1167     Error *local_err = NULL;
1168 
1169     cpu_exec_realizefn(cs, &local_err);
1170     if (local_err != NULL) {
1171         error_propagate(errp, local_err);
1172         return;
1173     }
1174 
1175     riscv_cpu_finalize_features(cpu, &local_err);
1176     if (local_err != NULL) {
1177         error_propagate(errp, local_err);
1178         return;
1179     }
1180 
1181     riscv_cpu_register_gdb_regs_for_features(cs);
1182 
1183 #ifndef CONFIG_USER_ONLY
1184     if (cpu->cfg.debug) {
1185         riscv_trigger_realize(&cpu->env);
1186     }
1187 #endif
1188 
1189     qemu_init_vcpu(cs);
1190     cpu_reset(cs);
1191 
1192     mcc->parent_realize(dev, errp);
1193 }
1194 
1195 bool riscv_cpu_accelerator_compatible(RISCVCPU *cpu)
1196 {
1197     if (tcg_enabled()) {
1198         return riscv_cpu_tcg_compatible(cpu);
1199     }
1200 
1201     return true;
1202 }
1203 
1204 #ifndef CONFIG_USER_ONLY
1205 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name,
1206                                void *opaque, Error **errp)
1207 {
1208     RISCVSATPMap *satp_map = opaque;
1209     uint8_t satp = satp_mode_from_str(name);
1210     bool value;
1211 
1212     value = satp_map->map & (1 << satp);
1213 
1214     visit_type_bool(v, name, &value, errp);
1215 }
1216 
1217 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
1218                                void *opaque, Error **errp)
1219 {
1220     RISCVSATPMap *satp_map = opaque;
1221     uint8_t satp = satp_mode_from_str(name);
1222     bool value;
1223 
1224     if (!visit_type_bool(v, name, &value, errp)) {
1225         return;
1226     }
1227 
1228     satp_map->map = deposit32(satp_map->map, satp, 1, value);
1229     satp_map->init |= 1 << satp;
1230 }
1231 
1232 void riscv_add_satp_mode_properties(Object *obj)
1233 {
1234     RISCVCPU *cpu = RISCV_CPU(obj);
1235 
1236     if (cpu->env.misa_mxl == MXL_RV32) {
1237         object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp,
1238                             cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1239     } else {
1240         object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp,
1241                             cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1242         object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp,
1243                             cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1244         object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp,
1245                             cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1246         object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp,
1247                             cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1248     }
1249 }
1250 
1251 static void riscv_cpu_set_irq(void *opaque, int irq, int level)
1252 {
1253     RISCVCPU *cpu = RISCV_CPU(opaque);
1254     CPURISCVState *env = &cpu->env;
1255 
1256     if (irq < IRQ_LOCAL_MAX) {
1257         switch (irq) {
1258         case IRQ_U_SOFT:
1259         case IRQ_S_SOFT:
1260         case IRQ_VS_SOFT:
1261         case IRQ_M_SOFT:
1262         case IRQ_U_TIMER:
1263         case IRQ_S_TIMER:
1264         case IRQ_VS_TIMER:
1265         case IRQ_M_TIMER:
1266         case IRQ_U_EXT:
1267         case IRQ_VS_EXT:
1268         case IRQ_M_EXT:
1269             if (kvm_enabled()) {
1270                 kvm_riscv_set_irq(cpu, irq, level);
1271             } else {
1272                 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
1273             }
1274              break;
1275         case IRQ_S_EXT:
1276             if (kvm_enabled()) {
1277                 kvm_riscv_set_irq(cpu, irq, level);
1278             } else {
1279                 env->external_seip = level;
1280                 riscv_cpu_update_mip(env, 1 << irq,
1281                                      BOOL_TO_MASK(level | env->software_seip));
1282             }
1283             break;
1284         default:
1285             g_assert_not_reached();
1286         }
1287     } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
1288         /* Require H-extension for handling guest local interrupts */
1289         if (!riscv_has_ext(env, RVH)) {
1290             g_assert_not_reached();
1291         }
1292 
1293         /* Compute bit position in HGEIP CSR */
1294         irq = irq - IRQ_LOCAL_MAX + 1;
1295         if (env->geilen < irq) {
1296             g_assert_not_reached();
1297         }
1298 
1299         /* Update HGEIP CSR */
1300         env->hgeip &= ~((target_ulong)1 << irq);
1301         if (level) {
1302             env->hgeip |= (target_ulong)1 << irq;
1303         }
1304 
1305         /* Update mip.SGEIP bit */
1306         riscv_cpu_update_mip(env, MIP_SGEIP,
1307                              BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
1308     } else {
1309         g_assert_not_reached();
1310     }
1311 }
1312 #endif /* CONFIG_USER_ONLY */
1313 
1314 static bool riscv_cpu_is_dynamic(Object *cpu_obj)
1315 {
1316     return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL;
1317 }
1318 
1319 static void riscv_cpu_post_init(Object *obj)
1320 {
1321     accel_cpu_instance_init(CPU(obj));
1322 }
1323 
1324 static void riscv_cpu_init(Object *obj)
1325 {
1326     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(obj);
1327     RISCVCPU *cpu = RISCV_CPU(obj);
1328     CPURISCVState *env = &cpu->env;
1329 
1330     env->misa_mxl = mcc->misa_mxl_max;
1331 
1332 #ifndef CONFIG_USER_ONLY
1333     qdev_init_gpio_in(DEVICE(obj), riscv_cpu_set_irq,
1334                       IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
1335 #endif /* CONFIG_USER_ONLY */
1336 
1337     general_user_opts = g_hash_table_new(g_str_hash, g_str_equal);
1338 
1339     /*
1340      * The timer and performance counters extensions were supported
1341      * in QEMU before they were added as discrete extensions in the
1342      * ISA. To keep compatibility we'll always default them to 'true'
1343      * for all CPUs. Each accelerator will decide what to do when
1344      * users disable them.
1345      */
1346     RISCV_CPU(obj)->cfg.ext_zicntr = true;
1347     RISCV_CPU(obj)->cfg.ext_zihpm = true;
1348 
1349     /* Default values for non-bool cpu properties */
1350     cpu->cfg.pmu_mask = MAKE_64BIT_MASK(3, 16);
1351     cpu->cfg.vlenb = 128 >> 3;
1352     cpu->cfg.elen = 64;
1353     cpu->cfg.cbom_blocksize = 64;
1354     cpu->cfg.cbop_blocksize = 64;
1355     cpu->cfg.cboz_blocksize = 64;
1356     cpu->env.vext_ver = VEXT_VERSION_1_00_0;
1357 }
1358 
1359 static void riscv_bare_cpu_init(Object *obj)
1360 {
1361     RISCVCPU *cpu = RISCV_CPU(obj);
1362 
1363     /*
1364      * Bare CPUs do not inherit the timer and performance
1365      * counters from the parent class (see riscv_cpu_init()
1366      * for info on why the parent enables them).
1367      *
1368      * Users have to explicitly enable these counters for
1369      * bare CPUs.
1370      */
1371     cpu->cfg.ext_zicntr = false;
1372     cpu->cfg.ext_zihpm = false;
1373 
1374     /* Set to QEMU's first supported priv version */
1375     cpu->env.priv_ver = PRIV_VERSION_1_10_0;
1376 
1377     /*
1378      * Support all available satp_mode settings. The default
1379      * value will be set to MBARE if the user doesn't set
1380      * satp_mode manually (see set_satp_mode_default()).
1381      */
1382 #ifndef CONFIG_USER_ONLY
1383     set_satp_mode_max_supported(cpu, VM_1_10_SV64);
1384 #endif
1385 }
1386 
1387 typedef struct misa_ext_info {
1388     const char *name;
1389     const char *description;
1390 } MISAExtInfo;
1391 
1392 #define MISA_INFO_IDX(_bit) \
1393     __builtin_ctz(_bit)
1394 
1395 #define MISA_EXT_INFO(_bit, _propname, _descr) \
1396     [MISA_INFO_IDX(_bit)] = {.name = _propname, .description = _descr}
1397 
1398 static const MISAExtInfo misa_ext_info_arr[] = {
1399     MISA_EXT_INFO(RVA, "a", "Atomic instructions"),
1400     MISA_EXT_INFO(RVC, "c", "Compressed instructions"),
1401     MISA_EXT_INFO(RVD, "d", "Double-precision float point"),
1402     MISA_EXT_INFO(RVF, "f", "Single-precision float point"),
1403     MISA_EXT_INFO(RVI, "i", "Base integer instruction set"),
1404     MISA_EXT_INFO(RVE, "e", "Base integer instruction set (embedded)"),
1405     MISA_EXT_INFO(RVM, "m", "Integer multiplication and division"),
1406     MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"),
1407     MISA_EXT_INFO(RVU, "u", "User-level instructions"),
1408     MISA_EXT_INFO(RVH, "h", "Hypervisor"),
1409     MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"),
1410     MISA_EXT_INFO(RVV, "v", "Vector operations"),
1411     MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"),
1412     MISA_EXT_INFO(RVB, "b", "Bit manipulation (Zba_Zbb_Zbs)")
1413 };
1414 
1415 static void riscv_cpu_validate_misa_mxl(RISCVCPUClass *mcc)
1416 {
1417     CPUClass *cc = CPU_CLASS(mcc);
1418 
1419     /* Validate that MISA_MXL is set properly. */
1420     switch (mcc->misa_mxl_max) {
1421 #ifdef TARGET_RISCV64
1422     case MXL_RV64:
1423     case MXL_RV128:
1424         cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
1425         break;
1426 #endif
1427     case MXL_RV32:
1428         cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
1429         break;
1430     default:
1431         g_assert_not_reached();
1432     }
1433 }
1434 
1435 static int riscv_validate_misa_info_idx(uint32_t bit)
1436 {
1437     int idx;
1438 
1439     /*
1440      * Our lowest valid input (RVA) is 1 and
1441      * __builtin_ctz() is UB with zero.
1442      */
1443     g_assert(bit != 0);
1444     idx = MISA_INFO_IDX(bit);
1445 
1446     g_assert(idx < ARRAY_SIZE(misa_ext_info_arr));
1447     return idx;
1448 }
1449 
1450 const char *riscv_get_misa_ext_name(uint32_t bit)
1451 {
1452     int idx = riscv_validate_misa_info_idx(bit);
1453     const char *val = misa_ext_info_arr[idx].name;
1454 
1455     g_assert(val != NULL);
1456     return val;
1457 }
1458 
1459 const char *riscv_get_misa_ext_description(uint32_t bit)
1460 {
1461     int idx = riscv_validate_misa_info_idx(bit);
1462     const char *val = misa_ext_info_arr[idx].description;
1463 
1464     g_assert(val != NULL);
1465     return val;
1466 }
1467 
1468 #define MULTI_EXT_CFG_BOOL(_name, _prop, _defval) \
1469     {.name = _name, .offset = CPU_CFG_OFFSET(_prop), \
1470      .enabled = _defval}
1471 
1472 const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = {
1473     /* Defaults for standard extensions */
1474     MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false),
1475     MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false),
1476     MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true),
1477     MULTI_EXT_CFG_BOOL("zicfilp", ext_zicfilp, false),
1478     MULTI_EXT_CFG_BOOL("zicfiss", ext_zicfiss, false),
1479     MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true),
1480     MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true),
1481     MULTI_EXT_CFG_BOOL("zihintpause", ext_zihintpause, true),
1482     MULTI_EXT_CFG_BOOL("zimop", ext_zimop, false),
1483     MULTI_EXT_CFG_BOOL("zcmop", ext_zcmop, false),
1484     MULTI_EXT_CFG_BOOL("zacas", ext_zacas, false),
1485     MULTI_EXT_CFG_BOOL("zama16b", ext_zama16b, false),
1486     MULTI_EXT_CFG_BOOL("zabha", ext_zabha, false),
1487     MULTI_EXT_CFG_BOOL("zaamo", ext_zaamo, false),
1488     MULTI_EXT_CFG_BOOL("zalrsc", ext_zalrsc, false),
1489     MULTI_EXT_CFG_BOOL("zawrs", ext_zawrs, true),
1490     MULTI_EXT_CFG_BOOL("zfa", ext_zfa, true),
1491     MULTI_EXT_CFG_BOOL("zfbfmin", ext_zfbfmin, false),
1492     MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false),
1493     MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false),
1494     MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false),
1495     MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false),
1496     MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false),
1497     MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false),
1498     MULTI_EXT_CFG_BOOL("zve64x", ext_zve64x, false),
1499     MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false),
1500     MULTI_EXT_CFG_BOOL("zvfbfwma", ext_zvfbfwma, false),
1501     MULTI_EXT_CFG_BOOL("zvfh", ext_zvfh, false),
1502     MULTI_EXT_CFG_BOOL("zvfhmin", ext_zvfhmin, false),
1503     MULTI_EXT_CFG_BOOL("sstc", ext_sstc, true),
1504 
1505     MULTI_EXT_CFG_BOOL("smaia", ext_smaia, false),
1506     MULTI_EXT_CFG_BOOL("smepmp", ext_smepmp, false),
1507     MULTI_EXT_CFG_BOOL("smstateen", ext_smstateen, false),
1508     MULTI_EXT_CFG_BOOL("ssaia", ext_ssaia, false),
1509     MULTI_EXT_CFG_BOOL("svade", ext_svade, false),
1510     MULTI_EXT_CFG_BOOL("svadu", ext_svadu, true),
1511     MULTI_EXT_CFG_BOOL("svinval", ext_svinval, false),
1512     MULTI_EXT_CFG_BOOL("svnapot", ext_svnapot, false),
1513     MULTI_EXT_CFG_BOOL("svpbmt", ext_svpbmt, false),
1514     MULTI_EXT_CFG_BOOL("svvptc", ext_svvptc, true),
1515 
1516     MULTI_EXT_CFG_BOOL("zicntr", ext_zicntr, true),
1517     MULTI_EXT_CFG_BOOL("zihpm", ext_zihpm, true),
1518 
1519     MULTI_EXT_CFG_BOOL("zba", ext_zba, true),
1520     MULTI_EXT_CFG_BOOL("zbb", ext_zbb, true),
1521     MULTI_EXT_CFG_BOOL("zbc", ext_zbc, true),
1522     MULTI_EXT_CFG_BOOL("zbkb", ext_zbkb, false),
1523     MULTI_EXT_CFG_BOOL("zbkc", ext_zbkc, false),
1524     MULTI_EXT_CFG_BOOL("zbkx", ext_zbkx, false),
1525     MULTI_EXT_CFG_BOOL("zbs", ext_zbs, true),
1526     MULTI_EXT_CFG_BOOL("zk", ext_zk, false),
1527     MULTI_EXT_CFG_BOOL("zkn", ext_zkn, false),
1528     MULTI_EXT_CFG_BOOL("zknd", ext_zknd, false),
1529     MULTI_EXT_CFG_BOOL("zkne", ext_zkne, false),
1530     MULTI_EXT_CFG_BOOL("zknh", ext_zknh, false),
1531     MULTI_EXT_CFG_BOOL("zkr", ext_zkr, false),
1532     MULTI_EXT_CFG_BOOL("zks", ext_zks, false),
1533     MULTI_EXT_CFG_BOOL("zksed", ext_zksed, false),
1534     MULTI_EXT_CFG_BOOL("zksh", ext_zksh, false),
1535     MULTI_EXT_CFG_BOOL("zkt", ext_zkt, false),
1536     MULTI_EXT_CFG_BOOL("ztso", ext_ztso, false),
1537 
1538     MULTI_EXT_CFG_BOOL("zdinx", ext_zdinx, false),
1539     MULTI_EXT_CFG_BOOL("zfinx", ext_zfinx, false),
1540     MULTI_EXT_CFG_BOOL("zhinx", ext_zhinx, false),
1541     MULTI_EXT_CFG_BOOL("zhinxmin", ext_zhinxmin, false),
1542 
1543     MULTI_EXT_CFG_BOOL("zicbom", ext_zicbom, true),
1544     MULTI_EXT_CFG_BOOL("zicbop", ext_zicbop, true),
1545     MULTI_EXT_CFG_BOOL("zicboz", ext_zicboz, true),
1546 
1547     MULTI_EXT_CFG_BOOL("zmmul", ext_zmmul, false),
1548 
1549     MULTI_EXT_CFG_BOOL("zca", ext_zca, false),
1550     MULTI_EXT_CFG_BOOL("zcb", ext_zcb, false),
1551     MULTI_EXT_CFG_BOOL("zcd", ext_zcd, false),
1552     MULTI_EXT_CFG_BOOL("zce", ext_zce, false),
1553     MULTI_EXT_CFG_BOOL("zcf", ext_zcf, false),
1554     MULTI_EXT_CFG_BOOL("zcmp", ext_zcmp, false),
1555     MULTI_EXT_CFG_BOOL("zcmt", ext_zcmt, false),
1556     MULTI_EXT_CFG_BOOL("zicond", ext_zicond, false),
1557 
1558     /* Vector cryptography extensions */
1559     MULTI_EXT_CFG_BOOL("zvbb", ext_zvbb, false),
1560     MULTI_EXT_CFG_BOOL("zvbc", ext_zvbc, false),
1561     MULTI_EXT_CFG_BOOL("zvkb", ext_zvkb, false),
1562     MULTI_EXT_CFG_BOOL("zvkg", ext_zvkg, false),
1563     MULTI_EXT_CFG_BOOL("zvkned", ext_zvkned, false),
1564     MULTI_EXT_CFG_BOOL("zvknha", ext_zvknha, false),
1565     MULTI_EXT_CFG_BOOL("zvknhb", ext_zvknhb, false),
1566     MULTI_EXT_CFG_BOOL("zvksed", ext_zvksed, false),
1567     MULTI_EXT_CFG_BOOL("zvksh", ext_zvksh, false),
1568     MULTI_EXT_CFG_BOOL("zvkt", ext_zvkt, false),
1569     MULTI_EXT_CFG_BOOL("zvkn", ext_zvkn, false),
1570     MULTI_EXT_CFG_BOOL("zvknc", ext_zvknc, false),
1571     MULTI_EXT_CFG_BOOL("zvkng", ext_zvkng, false),
1572     MULTI_EXT_CFG_BOOL("zvks", ext_zvks, false),
1573     MULTI_EXT_CFG_BOOL("zvksc", ext_zvksc, false),
1574     MULTI_EXT_CFG_BOOL("zvksg", ext_zvksg, false),
1575 
1576     DEFINE_PROP_END_OF_LIST(),
1577 };
1578 
1579 const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = {
1580     MULTI_EXT_CFG_BOOL("xtheadba", ext_xtheadba, false),
1581     MULTI_EXT_CFG_BOOL("xtheadbb", ext_xtheadbb, false),
1582     MULTI_EXT_CFG_BOOL("xtheadbs", ext_xtheadbs, false),
1583     MULTI_EXT_CFG_BOOL("xtheadcmo", ext_xtheadcmo, false),
1584     MULTI_EXT_CFG_BOOL("xtheadcondmov", ext_xtheadcondmov, false),
1585     MULTI_EXT_CFG_BOOL("xtheadfmemidx", ext_xtheadfmemidx, false),
1586     MULTI_EXT_CFG_BOOL("xtheadfmv", ext_xtheadfmv, false),
1587     MULTI_EXT_CFG_BOOL("xtheadmac", ext_xtheadmac, false),
1588     MULTI_EXT_CFG_BOOL("xtheadmemidx", ext_xtheadmemidx, false),
1589     MULTI_EXT_CFG_BOOL("xtheadmempair", ext_xtheadmempair, false),
1590     MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false),
1591     MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false),
1592 
1593     DEFINE_PROP_END_OF_LIST(),
1594 };
1595 
1596 /* These are experimental so mark with 'x-' */
1597 const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = {
1598     DEFINE_PROP_END_OF_LIST(),
1599 };
1600 
1601 /*
1602  * 'Named features' is the name we give to extensions that we
1603  * don't want to expose to users. They are either immutable
1604  * (always enabled/disable) or they'll vary depending on
1605  * the resulting CPU state. They have riscv,isa strings
1606  * and priv_ver like regular extensions.
1607  */
1608 const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = {
1609     MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true),
1610 
1611     DEFINE_PROP_END_OF_LIST(),
1612 };
1613 
1614 /* Deprecated entries marked for future removal */
1615 const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = {
1616     MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true),
1617     MULTI_EXT_CFG_BOOL("Zicsr", ext_zicsr, true),
1618     MULTI_EXT_CFG_BOOL("Zihintntl", ext_zihintntl, true),
1619     MULTI_EXT_CFG_BOOL("Zihintpause", ext_zihintpause, true),
1620     MULTI_EXT_CFG_BOOL("Zawrs", ext_zawrs, true),
1621     MULTI_EXT_CFG_BOOL("Zfa", ext_zfa, true),
1622     MULTI_EXT_CFG_BOOL("Zfh", ext_zfh, false),
1623     MULTI_EXT_CFG_BOOL("Zfhmin", ext_zfhmin, false),
1624     MULTI_EXT_CFG_BOOL("Zve32f", ext_zve32f, false),
1625     MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false),
1626     MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false),
1627 
1628     DEFINE_PROP_END_OF_LIST(),
1629 };
1630 
1631 static void cpu_set_prop_err(RISCVCPU *cpu, const char *propname,
1632                              Error **errp)
1633 {
1634     g_autofree char *cpuname = riscv_cpu_get_name(cpu);
1635     error_setg(errp, "CPU '%s' does not allow changing the value of '%s'",
1636                cpuname, propname);
1637 }
1638 
1639 static void prop_pmu_num_set(Object *obj, Visitor *v, const char *name,
1640                              void *opaque, Error **errp)
1641 {
1642     RISCVCPU *cpu = RISCV_CPU(obj);
1643     uint8_t pmu_num, curr_pmu_num;
1644     uint32_t pmu_mask;
1645 
1646     visit_type_uint8(v, name, &pmu_num, errp);
1647 
1648     curr_pmu_num = ctpop32(cpu->cfg.pmu_mask);
1649 
1650     if (pmu_num != curr_pmu_num && riscv_cpu_is_vendor(obj)) {
1651         cpu_set_prop_err(cpu, name, errp);
1652         error_append_hint(errp, "Current '%s' val: %u\n",
1653                           name, curr_pmu_num);
1654         return;
1655     }
1656 
1657     if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) {
1658         error_setg(errp, "Number of counters exceeds maximum available");
1659         return;
1660     }
1661 
1662     if (pmu_num == 0) {
1663         pmu_mask = 0;
1664     } else {
1665         pmu_mask = MAKE_64BIT_MASK(3, pmu_num);
1666     }
1667 
1668     warn_report("\"pmu-num\" property is deprecated; use \"pmu-mask\"");
1669     cpu->cfg.pmu_mask = pmu_mask;
1670     cpu_option_add_user_setting("pmu-mask", pmu_mask);
1671 }
1672 
1673 static void prop_pmu_num_get(Object *obj, Visitor *v, const char *name,
1674                              void *opaque, Error **errp)
1675 {
1676     RISCVCPU *cpu = RISCV_CPU(obj);
1677     uint8_t pmu_num = ctpop32(cpu->cfg.pmu_mask);
1678 
1679     visit_type_uint8(v, name, &pmu_num, errp);
1680 }
1681 
1682 static const PropertyInfo prop_pmu_num = {
1683     .name = "pmu-num",
1684     .get = prop_pmu_num_get,
1685     .set = prop_pmu_num_set,
1686 };
1687 
1688 static void prop_pmu_mask_set(Object *obj, Visitor *v, const char *name,
1689                              void *opaque, Error **errp)
1690 {
1691     RISCVCPU *cpu = RISCV_CPU(obj);
1692     uint32_t value;
1693     uint8_t pmu_num;
1694 
1695     visit_type_uint32(v, name, &value, errp);
1696 
1697     if (value != cpu->cfg.pmu_mask && riscv_cpu_is_vendor(obj)) {
1698         cpu_set_prop_err(cpu, name, errp);
1699         error_append_hint(errp, "Current '%s' val: %x\n",
1700                           name, cpu->cfg.pmu_mask);
1701         return;
1702     }
1703 
1704     pmu_num = ctpop32(value);
1705 
1706     if (pmu_num > (RV_MAX_MHPMCOUNTERS - 3)) {
1707         error_setg(errp, "Number of counters exceeds maximum available");
1708         return;
1709     }
1710 
1711     cpu_option_add_user_setting(name, value);
1712     cpu->cfg.pmu_mask = value;
1713 }
1714 
1715 static void prop_pmu_mask_get(Object *obj, Visitor *v, const char *name,
1716                              void *opaque, Error **errp)
1717 {
1718     uint8_t pmu_mask = RISCV_CPU(obj)->cfg.pmu_mask;
1719 
1720     visit_type_uint8(v, name, &pmu_mask, errp);
1721 }
1722 
1723 static const PropertyInfo prop_pmu_mask = {
1724     .name = "pmu-mask",
1725     .get = prop_pmu_mask_get,
1726     .set = prop_pmu_mask_set,
1727 };
1728 
1729 static void prop_mmu_set(Object *obj, Visitor *v, const char *name,
1730                          void *opaque, Error **errp)
1731 {
1732     RISCVCPU *cpu = RISCV_CPU(obj);
1733     bool value;
1734 
1735     visit_type_bool(v, name, &value, errp);
1736 
1737     if (cpu->cfg.mmu != value && riscv_cpu_is_vendor(obj)) {
1738         cpu_set_prop_err(cpu, "mmu", errp);
1739         return;
1740     }
1741 
1742     cpu_option_add_user_setting(name, value);
1743     cpu->cfg.mmu = value;
1744 }
1745 
1746 static void prop_mmu_get(Object *obj, Visitor *v, const char *name,
1747                          void *opaque, Error **errp)
1748 {
1749     bool value = RISCV_CPU(obj)->cfg.mmu;
1750 
1751     visit_type_bool(v, name, &value, errp);
1752 }
1753 
1754 static const PropertyInfo prop_mmu = {
1755     .name = "mmu",
1756     .get = prop_mmu_get,
1757     .set = prop_mmu_set,
1758 };
1759 
1760 static void prop_pmp_set(Object *obj, Visitor *v, const char *name,
1761                          void *opaque, Error **errp)
1762 {
1763     RISCVCPU *cpu = RISCV_CPU(obj);
1764     bool value;
1765 
1766     visit_type_bool(v, name, &value, errp);
1767 
1768     if (cpu->cfg.pmp != value && riscv_cpu_is_vendor(obj)) {
1769         cpu_set_prop_err(cpu, name, errp);
1770         return;
1771     }
1772 
1773     cpu_option_add_user_setting(name, value);
1774     cpu->cfg.pmp = value;
1775 }
1776 
1777 static void prop_pmp_get(Object *obj, Visitor *v, const char *name,
1778                          void *opaque, Error **errp)
1779 {
1780     bool value = RISCV_CPU(obj)->cfg.pmp;
1781 
1782     visit_type_bool(v, name, &value, errp);
1783 }
1784 
1785 static const PropertyInfo prop_pmp = {
1786     .name = "pmp",
1787     .get = prop_pmp_get,
1788     .set = prop_pmp_set,
1789 };
1790 
1791 static int priv_spec_from_str(const char *priv_spec_str)
1792 {
1793     int priv_version = -1;
1794 
1795     if (!g_strcmp0(priv_spec_str, PRIV_VER_1_13_0_STR)) {
1796         priv_version = PRIV_VERSION_1_13_0;
1797     } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_12_0_STR)) {
1798         priv_version = PRIV_VERSION_1_12_0;
1799     } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_11_0_STR)) {
1800         priv_version = PRIV_VERSION_1_11_0;
1801     } else if (!g_strcmp0(priv_spec_str, PRIV_VER_1_10_0_STR)) {
1802         priv_version = PRIV_VERSION_1_10_0;
1803     }
1804 
1805     return priv_version;
1806 }
1807 
1808 const char *priv_spec_to_str(int priv_version)
1809 {
1810     switch (priv_version) {
1811     case PRIV_VERSION_1_10_0:
1812         return PRIV_VER_1_10_0_STR;
1813     case PRIV_VERSION_1_11_0:
1814         return PRIV_VER_1_11_0_STR;
1815     case PRIV_VERSION_1_12_0:
1816         return PRIV_VER_1_12_0_STR;
1817     case PRIV_VERSION_1_13_0:
1818         return PRIV_VER_1_13_0_STR;
1819     default:
1820         return NULL;
1821     }
1822 }
1823 
1824 static void prop_priv_spec_set(Object *obj, Visitor *v, const char *name,
1825                                void *opaque, Error **errp)
1826 {
1827     RISCVCPU *cpu = RISCV_CPU(obj);
1828     g_autofree char *value = NULL;
1829     int priv_version = -1;
1830 
1831     visit_type_str(v, name, &value, errp);
1832 
1833     priv_version = priv_spec_from_str(value);
1834     if (priv_version < 0) {
1835         error_setg(errp, "Unsupported privilege spec version '%s'", value);
1836         return;
1837     }
1838 
1839     if (priv_version != cpu->env.priv_ver && riscv_cpu_is_vendor(obj)) {
1840         cpu_set_prop_err(cpu, name, errp);
1841         error_append_hint(errp, "Current '%s' val: %s\n", name,
1842                           object_property_get_str(obj, name, NULL));
1843         return;
1844     }
1845 
1846     cpu_option_add_user_setting(name, priv_version);
1847     cpu->env.priv_ver = priv_version;
1848 }
1849 
1850 static void prop_priv_spec_get(Object *obj, Visitor *v, const char *name,
1851                                void *opaque, Error **errp)
1852 {
1853     RISCVCPU *cpu = RISCV_CPU(obj);
1854     const char *value = priv_spec_to_str(cpu->env.priv_ver);
1855 
1856     visit_type_str(v, name, (char **)&value, errp);
1857 }
1858 
1859 static const PropertyInfo prop_priv_spec = {
1860     .name = "priv_spec",
1861     .get = prop_priv_spec_get,
1862     .set = prop_priv_spec_set,
1863 };
1864 
1865 static void prop_vext_spec_set(Object *obj, Visitor *v, const char *name,
1866                                void *opaque, Error **errp)
1867 {
1868     RISCVCPU *cpu = RISCV_CPU(obj);
1869     g_autofree char *value = NULL;
1870 
1871     visit_type_str(v, name, &value, errp);
1872 
1873     if (g_strcmp0(value, VEXT_VER_1_00_0_STR) != 0) {
1874         error_setg(errp, "Unsupported vector spec version '%s'", value);
1875         return;
1876     }
1877 
1878     cpu_option_add_user_setting(name, VEXT_VERSION_1_00_0);
1879     cpu->env.vext_ver = VEXT_VERSION_1_00_0;
1880 }
1881 
1882 static void prop_vext_spec_get(Object *obj, Visitor *v, const char *name,
1883                                void *opaque, Error **errp)
1884 {
1885     const char *value = VEXT_VER_1_00_0_STR;
1886 
1887     visit_type_str(v, name, (char **)&value, errp);
1888 }
1889 
1890 static const PropertyInfo prop_vext_spec = {
1891     .name = "vext_spec",
1892     .get = prop_vext_spec_get,
1893     .set = prop_vext_spec_set,
1894 };
1895 
1896 static void prop_vlen_set(Object *obj, Visitor *v, const char *name,
1897                          void *opaque, Error **errp)
1898 {
1899     RISCVCPU *cpu = RISCV_CPU(obj);
1900     uint16_t value;
1901 
1902     if (!visit_type_uint16(v, name, &value, errp)) {
1903         return;
1904     }
1905 
1906     if (!is_power_of_2(value)) {
1907         error_setg(errp, "Vector extension VLEN must be power of 2");
1908         return;
1909     }
1910 
1911     if (value != cpu->cfg.vlenb && riscv_cpu_is_vendor(obj)) {
1912         cpu_set_prop_err(cpu, name, errp);
1913         error_append_hint(errp, "Current '%s' val: %u\n",
1914                           name, cpu->cfg.vlenb << 3);
1915         return;
1916     }
1917 
1918     cpu_option_add_user_setting(name, value);
1919     cpu->cfg.vlenb = value >> 3;
1920 }
1921 
1922 static void prop_vlen_get(Object *obj, Visitor *v, const char *name,
1923                          void *opaque, Error **errp)
1924 {
1925     uint16_t value = RISCV_CPU(obj)->cfg.vlenb << 3;
1926 
1927     visit_type_uint16(v, name, &value, errp);
1928 }
1929 
1930 static const PropertyInfo prop_vlen = {
1931     .name = "vlen",
1932     .get = prop_vlen_get,
1933     .set = prop_vlen_set,
1934 };
1935 
1936 static void prop_elen_set(Object *obj, Visitor *v, const char *name,
1937                          void *opaque, Error **errp)
1938 {
1939     RISCVCPU *cpu = RISCV_CPU(obj);
1940     uint16_t value;
1941 
1942     if (!visit_type_uint16(v, name, &value, errp)) {
1943         return;
1944     }
1945 
1946     if (!is_power_of_2(value)) {
1947         error_setg(errp, "Vector extension ELEN must be power of 2");
1948         return;
1949     }
1950 
1951     if (value != cpu->cfg.elen && riscv_cpu_is_vendor(obj)) {
1952         cpu_set_prop_err(cpu, name, errp);
1953         error_append_hint(errp, "Current '%s' val: %u\n",
1954                           name, cpu->cfg.elen);
1955         return;
1956     }
1957 
1958     cpu_option_add_user_setting(name, value);
1959     cpu->cfg.elen = value;
1960 }
1961 
1962 static void prop_elen_get(Object *obj, Visitor *v, const char *name,
1963                          void *opaque, Error **errp)
1964 {
1965     uint16_t value = RISCV_CPU(obj)->cfg.elen;
1966 
1967     visit_type_uint16(v, name, &value, errp);
1968 }
1969 
1970 static const PropertyInfo prop_elen = {
1971     .name = "elen",
1972     .get = prop_elen_get,
1973     .set = prop_elen_set,
1974 };
1975 
1976 static void prop_cbom_blksize_set(Object *obj, Visitor *v, const char *name,
1977                                   void *opaque, Error **errp)
1978 {
1979     RISCVCPU *cpu = RISCV_CPU(obj);
1980     uint16_t value;
1981 
1982     if (!visit_type_uint16(v, name, &value, errp)) {
1983         return;
1984     }
1985 
1986     if (value != cpu->cfg.cbom_blocksize && riscv_cpu_is_vendor(obj)) {
1987         cpu_set_prop_err(cpu, name, errp);
1988         error_append_hint(errp, "Current '%s' val: %u\n",
1989                           name, cpu->cfg.cbom_blocksize);
1990         return;
1991     }
1992 
1993     cpu_option_add_user_setting(name, value);
1994     cpu->cfg.cbom_blocksize = value;
1995 }
1996 
1997 static void prop_cbom_blksize_get(Object *obj, Visitor *v, const char *name,
1998                          void *opaque, Error **errp)
1999 {
2000     uint16_t value = RISCV_CPU(obj)->cfg.cbom_blocksize;
2001 
2002     visit_type_uint16(v, name, &value, errp);
2003 }
2004 
2005 static const PropertyInfo prop_cbom_blksize = {
2006     .name = "cbom_blocksize",
2007     .get = prop_cbom_blksize_get,
2008     .set = prop_cbom_blksize_set,
2009 };
2010 
2011 static void prop_cbop_blksize_set(Object *obj, Visitor *v, const char *name,
2012                                   void *opaque, Error **errp)
2013 {
2014     RISCVCPU *cpu = RISCV_CPU(obj);
2015     uint16_t value;
2016 
2017     if (!visit_type_uint16(v, name, &value, errp)) {
2018         return;
2019     }
2020 
2021     if (value != cpu->cfg.cbop_blocksize && riscv_cpu_is_vendor(obj)) {
2022         cpu_set_prop_err(cpu, name, errp);
2023         error_append_hint(errp, "Current '%s' val: %u\n",
2024                           name, cpu->cfg.cbop_blocksize);
2025         return;
2026     }
2027 
2028     cpu_option_add_user_setting(name, value);
2029     cpu->cfg.cbop_blocksize = value;
2030 }
2031 
2032 static void prop_cbop_blksize_get(Object *obj, Visitor *v, const char *name,
2033                          void *opaque, Error **errp)
2034 {
2035     uint16_t value = RISCV_CPU(obj)->cfg.cbop_blocksize;
2036 
2037     visit_type_uint16(v, name, &value, errp);
2038 }
2039 
2040 static const PropertyInfo prop_cbop_blksize = {
2041     .name = "cbop_blocksize",
2042     .get = prop_cbop_blksize_get,
2043     .set = prop_cbop_blksize_set,
2044 };
2045 
2046 static void prop_cboz_blksize_set(Object *obj, Visitor *v, const char *name,
2047                                   void *opaque, Error **errp)
2048 {
2049     RISCVCPU *cpu = RISCV_CPU(obj);
2050     uint16_t value;
2051 
2052     if (!visit_type_uint16(v, name, &value, errp)) {
2053         return;
2054     }
2055 
2056     if (value != cpu->cfg.cboz_blocksize && riscv_cpu_is_vendor(obj)) {
2057         cpu_set_prop_err(cpu, name, errp);
2058         error_append_hint(errp, "Current '%s' val: %u\n",
2059                           name, cpu->cfg.cboz_blocksize);
2060         return;
2061     }
2062 
2063     cpu_option_add_user_setting(name, value);
2064     cpu->cfg.cboz_blocksize = value;
2065 }
2066 
2067 static void prop_cboz_blksize_get(Object *obj, Visitor *v, const char *name,
2068                          void *opaque, Error **errp)
2069 {
2070     uint16_t value = RISCV_CPU(obj)->cfg.cboz_blocksize;
2071 
2072     visit_type_uint16(v, name, &value, errp);
2073 }
2074 
2075 static const PropertyInfo prop_cboz_blksize = {
2076     .name = "cboz_blocksize",
2077     .get = prop_cboz_blksize_get,
2078     .set = prop_cboz_blksize_set,
2079 };
2080 
2081 static void prop_mvendorid_set(Object *obj, Visitor *v, const char *name,
2082                                void *opaque, Error **errp)
2083 {
2084     bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
2085     RISCVCPU *cpu = RISCV_CPU(obj);
2086     uint32_t prev_val = cpu->cfg.mvendorid;
2087     uint32_t value;
2088 
2089     if (!visit_type_uint32(v, name, &value, errp)) {
2090         return;
2091     }
2092 
2093     if (!dynamic_cpu && prev_val != value) {
2094         error_setg(errp, "Unable to change %s mvendorid (0x%x)",
2095                    object_get_typename(obj), prev_val);
2096         return;
2097     }
2098 
2099     cpu->cfg.mvendorid = value;
2100 }
2101 
2102 static void prop_mvendorid_get(Object *obj, Visitor *v, const char *name,
2103                                void *opaque, Error **errp)
2104 {
2105     uint32_t value = RISCV_CPU(obj)->cfg.mvendorid;
2106 
2107     visit_type_uint32(v, name, &value, errp);
2108 }
2109 
2110 static const PropertyInfo prop_mvendorid = {
2111     .name = "mvendorid",
2112     .get = prop_mvendorid_get,
2113     .set = prop_mvendorid_set,
2114 };
2115 
2116 static void prop_mimpid_set(Object *obj, Visitor *v, const char *name,
2117                             void *opaque, Error **errp)
2118 {
2119     bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
2120     RISCVCPU *cpu = RISCV_CPU(obj);
2121     uint64_t prev_val = cpu->cfg.mimpid;
2122     uint64_t value;
2123 
2124     if (!visit_type_uint64(v, name, &value, errp)) {
2125         return;
2126     }
2127 
2128     if (!dynamic_cpu && prev_val != value) {
2129         error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")",
2130                    object_get_typename(obj), prev_val);
2131         return;
2132     }
2133 
2134     cpu->cfg.mimpid = value;
2135 }
2136 
2137 static void prop_mimpid_get(Object *obj, Visitor *v, const char *name,
2138                             void *opaque, Error **errp)
2139 {
2140     uint64_t value = RISCV_CPU(obj)->cfg.mimpid;
2141 
2142     visit_type_uint64(v, name, &value, errp);
2143 }
2144 
2145 static const PropertyInfo prop_mimpid = {
2146     .name = "mimpid",
2147     .get = prop_mimpid_get,
2148     .set = prop_mimpid_set,
2149 };
2150 
2151 static void prop_marchid_set(Object *obj, Visitor *v, const char *name,
2152                              void *opaque, Error **errp)
2153 {
2154     bool dynamic_cpu = riscv_cpu_is_dynamic(obj);
2155     RISCVCPU *cpu = RISCV_CPU(obj);
2156     uint64_t prev_val = cpu->cfg.marchid;
2157     uint64_t value, invalid_val;
2158     uint32_t mxlen = 0;
2159 
2160     if (!visit_type_uint64(v, name, &value, errp)) {
2161         return;
2162     }
2163 
2164     if (!dynamic_cpu && prev_val != value) {
2165         error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")",
2166                    object_get_typename(obj), prev_val);
2167         return;
2168     }
2169 
2170     switch (riscv_cpu_mxl(&cpu->env)) {
2171     case MXL_RV32:
2172         mxlen = 32;
2173         break;
2174     case MXL_RV64:
2175     case MXL_RV128:
2176         mxlen = 64;
2177         break;
2178     default:
2179         g_assert_not_reached();
2180     }
2181 
2182     invalid_val = 1LL << (mxlen - 1);
2183 
2184     if (value == invalid_val) {
2185         error_setg(errp, "Unable to set marchid with MSB (%u) bit set "
2186                          "and the remaining bits zero", mxlen);
2187         return;
2188     }
2189 
2190     cpu->cfg.marchid = value;
2191 }
2192 
2193 static void prop_marchid_get(Object *obj, Visitor *v, const char *name,
2194                              void *opaque, Error **errp)
2195 {
2196     uint64_t value = RISCV_CPU(obj)->cfg.marchid;
2197 
2198     visit_type_uint64(v, name, &value, errp);
2199 }
2200 
2201 static const PropertyInfo prop_marchid = {
2202     .name = "marchid",
2203     .get = prop_marchid_get,
2204     .set = prop_marchid_set,
2205 };
2206 
2207 /*
2208  * RVA22U64 defines some 'named features' that are cache
2209  * related: Za64rs, Zic64b, Ziccif, Ziccrse, Ziccamoa
2210  * and Zicclsm. They are always implemented in TCG and
2211  * doesn't need to be manually enabled by the profile.
2212  */
2213 static RISCVCPUProfile RVA22U64 = {
2214     .parent = NULL,
2215     .name = "rva22u64",
2216     .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVU,
2217     .priv_spec = RISCV_PROFILE_ATTR_UNUSED,
2218     .satp_mode = RISCV_PROFILE_ATTR_UNUSED,
2219     .ext_offsets = {
2220         CPU_CFG_OFFSET(ext_zicsr), CPU_CFG_OFFSET(ext_zihintpause),
2221         CPU_CFG_OFFSET(ext_zba), CPU_CFG_OFFSET(ext_zbb),
2222         CPU_CFG_OFFSET(ext_zbs), CPU_CFG_OFFSET(ext_zfhmin),
2223         CPU_CFG_OFFSET(ext_zkt), CPU_CFG_OFFSET(ext_zicntr),
2224         CPU_CFG_OFFSET(ext_zihpm), CPU_CFG_OFFSET(ext_zicbom),
2225         CPU_CFG_OFFSET(ext_zicbop), CPU_CFG_OFFSET(ext_zicboz),
2226 
2227         /* mandatory named features for this profile */
2228         CPU_CFG_OFFSET(ext_zic64b),
2229 
2230         RISCV_PROFILE_EXT_LIST_END
2231     }
2232 };
2233 
2234 /*
2235  * As with RVA22U64, RVA22S64 also defines 'named features'.
2236  *
2237  * Cache related features that we consider enabled since we don't
2238  * implement cache: Ssccptr
2239  *
2240  * Other named features that we already implement: Sstvecd, Sstvala,
2241  * Sscounterenw
2242  *
2243  * The remaining features/extensions comes from RVA22U64.
2244  */
2245 static RISCVCPUProfile RVA22S64 = {
2246     .parent = &RVA22U64,
2247     .name = "rva22s64",
2248     .misa_ext = RVS,
2249     .priv_spec = PRIV_VERSION_1_12_0,
2250     .satp_mode = VM_1_10_SV39,
2251     .ext_offsets = {
2252         /* rva22s64 exts */
2253         CPU_CFG_OFFSET(ext_zifencei), CPU_CFG_OFFSET(ext_svpbmt),
2254         CPU_CFG_OFFSET(ext_svinval), CPU_CFG_OFFSET(ext_svade),
2255 
2256         RISCV_PROFILE_EXT_LIST_END
2257     }
2258 };
2259 
2260 RISCVCPUProfile *riscv_profiles[] = {
2261     &RVA22U64,
2262     &RVA22S64,
2263     NULL,
2264 };
2265 
2266 static RISCVCPUImpliedExtsRule RVA_IMPLIED = {
2267     .is_misa = true,
2268     .ext = RVA,
2269     .implied_multi_exts = {
2270         CPU_CFG_OFFSET(ext_zalrsc), CPU_CFG_OFFSET(ext_zaamo),
2271 
2272         RISCV_IMPLIED_EXTS_RULE_END
2273     },
2274 };
2275 
2276 static RISCVCPUImpliedExtsRule RVD_IMPLIED = {
2277     .is_misa = true,
2278     .ext = RVD,
2279     .implied_misa_exts = RVF,
2280     .implied_multi_exts = { RISCV_IMPLIED_EXTS_RULE_END },
2281 };
2282 
2283 static RISCVCPUImpliedExtsRule RVF_IMPLIED = {
2284     .is_misa = true,
2285     .ext = RVF,
2286     .implied_multi_exts = {
2287         CPU_CFG_OFFSET(ext_zicsr),
2288 
2289         RISCV_IMPLIED_EXTS_RULE_END
2290     },
2291 };
2292 
2293 static RISCVCPUImpliedExtsRule RVM_IMPLIED = {
2294     .is_misa = true,
2295     .ext = RVM,
2296     .implied_multi_exts = {
2297         CPU_CFG_OFFSET(ext_zmmul),
2298 
2299         RISCV_IMPLIED_EXTS_RULE_END
2300     },
2301 };
2302 
2303 static RISCVCPUImpliedExtsRule RVV_IMPLIED = {
2304     .is_misa = true,
2305     .ext = RVV,
2306     .implied_multi_exts = {
2307         CPU_CFG_OFFSET(ext_zve64d),
2308 
2309         RISCV_IMPLIED_EXTS_RULE_END
2310     },
2311 };
2312 
2313 static RISCVCPUImpliedExtsRule ZCB_IMPLIED = {
2314     .ext = CPU_CFG_OFFSET(ext_zcb),
2315     .implied_multi_exts = {
2316         CPU_CFG_OFFSET(ext_zca),
2317 
2318         RISCV_IMPLIED_EXTS_RULE_END
2319     },
2320 };
2321 
2322 static RISCVCPUImpliedExtsRule ZCD_IMPLIED = {
2323     .ext = CPU_CFG_OFFSET(ext_zcd),
2324     .implied_misa_exts = RVD,
2325     .implied_multi_exts = {
2326         CPU_CFG_OFFSET(ext_zca),
2327 
2328         RISCV_IMPLIED_EXTS_RULE_END
2329     },
2330 };
2331 
2332 static RISCVCPUImpliedExtsRule ZCE_IMPLIED = {
2333     .ext = CPU_CFG_OFFSET(ext_zce),
2334     .implied_multi_exts = {
2335         CPU_CFG_OFFSET(ext_zcb), CPU_CFG_OFFSET(ext_zcmp),
2336         CPU_CFG_OFFSET(ext_zcmt),
2337 
2338         RISCV_IMPLIED_EXTS_RULE_END
2339     },
2340 };
2341 
2342 static RISCVCPUImpliedExtsRule ZCF_IMPLIED = {
2343     .ext = CPU_CFG_OFFSET(ext_zcf),
2344     .implied_misa_exts = RVF,
2345     .implied_multi_exts = {
2346         CPU_CFG_OFFSET(ext_zca),
2347 
2348         RISCV_IMPLIED_EXTS_RULE_END
2349     },
2350 };
2351 
2352 static RISCVCPUImpliedExtsRule ZCMP_IMPLIED = {
2353     .ext = CPU_CFG_OFFSET(ext_zcmp),
2354     .implied_multi_exts = {
2355         CPU_CFG_OFFSET(ext_zca),
2356 
2357         RISCV_IMPLIED_EXTS_RULE_END
2358     },
2359 };
2360 
2361 static RISCVCPUImpliedExtsRule ZCMT_IMPLIED = {
2362     .ext = CPU_CFG_OFFSET(ext_zcmt),
2363     .implied_multi_exts = {
2364         CPU_CFG_OFFSET(ext_zca), CPU_CFG_OFFSET(ext_zicsr),
2365 
2366         RISCV_IMPLIED_EXTS_RULE_END
2367     },
2368 };
2369 
2370 static RISCVCPUImpliedExtsRule ZDINX_IMPLIED = {
2371     .ext = CPU_CFG_OFFSET(ext_zdinx),
2372     .implied_multi_exts = {
2373         CPU_CFG_OFFSET(ext_zfinx),
2374 
2375         RISCV_IMPLIED_EXTS_RULE_END
2376     },
2377 };
2378 
2379 static RISCVCPUImpliedExtsRule ZFA_IMPLIED = {
2380     .ext = CPU_CFG_OFFSET(ext_zfa),
2381     .implied_misa_exts = RVF,
2382     .implied_multi_exts = { RISCV_IMPLIED_EXTS_RULE_END },
2383 };
2384 
2385 static RISCVCPUImpliedExtsRule ZFBFMIN_IMPLIED = {
2386     .ext = CPU_CFG_OFFSET(ext_zfbfmin),
2387     .implied_misa_exts = RVF,
2388     .implied_multi_exts = { RISCV_IMPLIED_EXTS_RULE_END },
2389 };
2390 
2391 static RISCVCPUImpliedExtsRule ZFH_IMPLIED = {
2392     .ext = CPU_CFG_OFFSET(ext_zfh),
2393     .implied_multi_exts = {
2394         CPU_CFG_OFFSET(ext_zfhmin),
2395 
2396         RISCV_IMPLIED_EXTS_RULE_END
2397     },
2398 };
2399 
2400 static RISCVCPUImpliedExtsRule ZFHMIN_IMPLIED = {
2401     .ext = CPU_CFG_OFFSET(ext_zfhmin),
2402     .implied_misa_exts = RVF,
2403     .implied_multi_exts = { RISCV_IMPLIED_EXTS_RULE_END },
2404 };
2405 
2406 static RISCVCPUImpliedExtsRule ZFINX_IMPLIED = {
2407     .ext = CPU_CFG_OFFSET(ext_zfinx),
2408     .implied_multi_exts = {
2409         CPU_CFG_OFFSET(ext_zicsr),
2410 
2411         RISCV_IMPLIED_EXTS_RULE_END
2412     },
2413 };
2414 
2415 static RISCVCPUImpliedExtsRule ZHINX_IMPLIED = {
2416     .ext = CPU_CFG_OFFSET(ext_zhinx),
2417     .implied_multi_exts = {
2418         CPU_CFG_OFFSET(ext_zhinxmin),
2419 
2420         RISCV_IMPLIED_EXTS_RULE_END
2421     },
2422 };
2423 
2424 static RISCVCPUImpliedExtsRule ZHINXMIN_IMPLIED = {
2425     .ext = CPU_CFG_OFFSET(ext_zhinxmin),
2426     .implied_multi_exts = {
2427         CPU_CFG_OFFSET(ext_zfinx),
2428 
2429         RISCV_IMPLIED_EXTS_RULE_END
2430     },
2431 };
2432 
2433 static RISCVCPUImpliedExtsRule ZICNTR_IMPLIED = {
2434     .ext = CPU_CFG_OFFSET(ext_zicntr),
2435     .implied_multi_exts = {
2436         CPU_CFG_OFFSET(ext_zicsr),
2437 
2438         RISCV_IMPLIED_EXTS_RULE_END
2439     },
2440 };
2441 
2442 static RISCVCPUImpliedExtsRule ZIHPM_IMPLIED = {
2443     .ext = CPU_CFG_OFFSET(ext_zihpm),
2444     .implied_multi_exts = {
2445         CPU_CFG_OFFSET(ext_zicsr),
2446 
2447         RISCV_IMPLIED_EXTS_RULE_END
2448     },
2449 };
2450 
2451 static RISCVCPUImpliedExtsRule ZK_IMPLIED = {
2452     .ext = CPU_CFG_OFFSET(ext_zk),
2453     .implied_multi_exts = {
2454         CPU_CFG_OFFSET(ext_zkn), CPU_CFG_OFFSET(ext_zkr),
2455         CPU_CFG_OFFSET(ext_zkt),
2456 
2457         RISCV_IMPLIED_EXTS_RULE_END
2458     },
2459 };
2460 
2461 static RISCVCPUImpliedExtsRule ZKN_IMPLIED = {
2462     .ext = CPU_CFG_OFFSET(ext_zkn),
2463     .implied_multi_exts = {
2464         CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc),
2465         CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zkne),
2466         CPU_CFG_OFFSET(ext_zknd), CPU_CFG_OFFSET(ext_zknh),
2467 
2468         RISCV_IMPLIED_EXTS_RULE_END
2469     },
2470 };
2471 
2472 static RISCVCPUImpliedExtsRule ZKS_IMPLIED = {
2473     .ext = CPU_CFG_OFFSET(ext_zks),
2474     .implied_multi_exts = {
2475         CPU_CFG_OFFSET(ext_zbkb), CPU_CFG_OFFSET(ext_zbkc),
2476         CPU_CFG_OFFSET(ext_zbkx), CPU_CFG_OFFSET(ext_zksed),
2477         CPU_CFG_OFFSET(ext_zksh),
2478 
2479         RISCV_IMPLIED_EXTS_RULE_END
2480     },
2481 };
2482 
2483 static RISCVCPUImpliedExtsRule ZVBB_IMPLIED = {
2484     .ext = CPU_CFG_OFFSET(ext_zvbb),
2485     .implied_multi_exts = {
2486         CPU_CFG_OFFSET(ext_zvkb),
2487 
2488         RISCV_IMPLIED_EXTS_RULE_END
2489     },
2490 };
2491 
2492 static RISCVCPUImpliedExtsRule ZVE32F_IMPLIED = {
2493     .ext = CPU_CFG_OFFSET(ext_zve32f),
2494     .implied_misa_exts = RVF,
2495     .implied_multi_exts = {
2496         CPU_CFG_OFFSET(ext_zve32x),
2497 
2498         RISCV_IMPLIED_EXTS_RULE_END
2499     },
2500 };
2501 
2502 static RISCVCPUImpliedExtsRule ZVE32X_IMPLIED = {
2503     .ext = CPU_CFG_OFFSET(ext_zve32x),
2504     .implied_multi_exts = {
2505         CPU_CFG_OFFSET(ext_zicsr),
2506 
2507         RISCV_IMPLIED_EXTS_RULE_END
2508     },
2509 };
2510 
2511 static RISCVCPUImpliedExtsRule ZVE64D_IMPLIED = {
2512     .ext = CPU_CFG_OFFSET(ext_zve64d),
2513     .implied_misa_exts = RVD,
2514     .implied_multi_exts = {
2515         CPU_CFG_OFFSET(ext_zve64f),
2516 
2517         RISCV_IMPLIED_EXTS_RULE_END
2518     },
2519 };
2520 
2521 static RISCVCPUImpliedExtsRule ZVE64F_IMPLIED = {
2522     .ext = CPU_CFG_OFFSET(ext_zve64f),
2523     .implied_misa_exts = RVF,
2524     .implied_multi_exts = {
2525         CPU_CFG_OFFSET(ext_zve32f), CPU_CFG_OFFSET(ext_zve64x),
2526 
2527         RISCV_IMPLIED_EXTS_RULE_END
2528     },
2529 };
2530 
2531 static RISCVCPUImpliedExtsRule ZVE64X_IMPLIED = {
2532     .ext = CPU_CFG_OFFSET(ext_zve64x),
2533     .implied_multi_exts = {
2534         CPU_CFG_OFFSET(ext_zve32x),
2535 
2536         RISCV_IMPLIED_EXTS_RULE_END
2537     },
2538 };
2539 
2540 static RISCVCPUImpliedExtsRule ZVFBFMIN_IMPLIED = {
2541     .ext = CPU_CFG_OFFSET(ext_zvfbfmin),
2542     .implied_multi_exts = {
2543         CPU_CFG_OFFSET(ext_zve32f),
2544 
2545         RISCV_IMPLIED_EXTS_RULE_END
2546     },
2547 };
2548 
2549 static RISCVCPUImpliedExtsRule ZVFBFWMA_IMPLIED = {
2550     .ext = CPU_CFG_OFFSET(ext_zvfbfwma),
2551     .implied_multi_exts = {
2552         CPU_CFG_OFFSET(ext_zvfbfmin), CPU_CFG_OFFSET(ext_zfbfmin),
2553 
2554         RISCV_IMPLIED_EXTS_RULE_END
2555     },
2556 };
2557 
2558 static RISCVCPUImpliedExtsRule ZVFH_IMPLIED = {
2559     .ext = CPU_CFG_OFFSET(ext_zvfh),
2560     .implied_multi_exts = {
2561         CPU_CFG_OFFSET(ext_zvfhmin), CPU_CFG_OFFSET(ext_zfhmin),
2562 
2563         RISCV_IMPLIED_EXTS_RULE_END
2564     },
2565 };
2566 
2567 static RISCVCPUImpliedExtsRule ZVFHMIN_IMPLIED = {
2568     .ext = CPU_CFG_OFFSET(ext_zvfhmin),
2569     .implied_multi_exts = {
2570         CPU_CFG_OFFSET(ext_zve32f),
2571 
2572         RISCV_IMPLIED_EXTS_RULE_END
2573     },
2574 };
2575 
2576 static RISCVCPUImpliedExtsRule ZVKN_IMPLIED = {
2577     .ext = CPU_CFG_OFFSET(ext_zvkn),
2578     .implied_multi_exts = {
2579         CPU_CFG_OFFSET(ext_zvkned), CPU_CFG_OFFSET(ext_zvknhb),
2580         CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt),
2581 
2582         RISCV_IMPLIED_EXTS_RULE_END
2583     },
2584 };
2585 
2586 static RISCVCPUImpliedExtsRule ZVKNC_IMPLIED = {
2587     .ext = CPU_CFG_OFFSET(ext_zvknc),
2588     .implied_multi_exts = {
2589         CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvbc),
2590 
2591         RISCV_IMPLIED_EXTS_RULE_END
2592     },
2593 };
2594 
2595 static RISCVCPUImpliedExtsRule ZVKNG_IMPLIED = {
2596     .ext = CPU_CFG_OFFSET(ext_zvkng),
2597     .implied_multi_exts = {
2598         CPU_CFG_OFFSET(ext_zvkn), CPU_CFG_OFFSET(ext_zvkg),
2599 
2600         RISCV_IMPLIED_EXTS_RULE_END
2601     },
2602 };
2603 
2604 static RISCVCPUImpliedExtsRule ZVKNHB_IMPLIED = {
2605     .ext = CPU_CFG_OFFSET(ext_zvknhb),
2606     .implied_multi_exts = {
2607         CPU_CFG_OFFSET(ext_zve64x),
2608 
2609         RISCV_IMPLIED_EXTS_RULE_END
2610     },
2611 };
2612 
2613 static RISCVCPUImpliedExtsRule ZVKS_IMPLIED = {
2614     .ext = CPU_CFG_OFFSET(ext_zvks),
2615     .implied_multi_exts = {
2616         CPU_CFG_OFFSET(ext_zvksed), CPU_CFG_OFFSET(ext_zvksh),
2617         CPU_CFG_OFFSET(ext_zvkb), CPU_CFG_OFFSET(ext_zvkt),
2618 
2619         RISCV_IMPLIED_EXTS_RULE_END
2620     },
2621 };
2622 
2623 static RISCVCPUImpliedExtsRule ZVKSC_IMPLIED = {
2624     .ext = CPU_CFG_OFFSET(ext_zvksc),
2625     .implied_multi_exts = {
2626         CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvbc),
2627 
2628         RISCV_IMPLIED_EXTS_RULE_END
2629     },
2630 };
2631 
2632 static RISCVCPUImpliedExtsRule ZVKSG_IMPLIED = {
2633     .ext = CPU_CFG_OFFSET(ext_zvksg),
2634     .implied_multi_exts = {
2635         CPU_CFG_OFFSET(ext_zvks), CPU_CFG_OFFSET(ext_zvkg),
2636 
2637         RISCV_IMPLIED_EXTS_RULE_END
2638     },
2639 };
2640 
2641 RISCVCPUImpliedExtsRule *riscv_misa_ext_implied_rules[] = {
2642     &RVA_IMPLIED, &RVD_IMPLIED, &RVF_IMPLIED,
2643     &RVM_IMPLIED, &RVV_IMPLIED, NULL
2644 };
2645 
2646 RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = {
2647     &ZCB_IMPLIED, &ZCD_IMPLIED, &ZCE_IMPLIED,
2648     &ZCF_IMPLIED, &ZCMP_IMPLIED, &ZCMT_IMPLIED,
2649     &ZDINX_IMPLIED, &ZFA_IMPLIED, &ZFBFMIN_IMPLIED,
2650     &ZFH_IMPLIED, &ZFHMIN_IMPLIED, &ZFINX_IMPLIED,
2651     &ZHINX_IMPLIED, &ZHINXMIN_IMPLIED, &ZICNTR_IMPLIED,
2652     &ZIHPM_IMPLIED, &ZK_IMPLIED, &ZKN_IMPLIED,
2653     &ZKS_IMPLIED, &ZVBB_IMPLIED, &ZVE32F_IMPLIED,
2654     &ZVE32X_IMPLIED, &ZVE64D_IMPLIED, &ZVE64F_IMPLIED,
2655     &ZVE64X_IMPLIED, &ZVFBFMIN_IMPLIED, &ZVFBFWMA_IMPLIED,
2656     &ZVFH_IMPLIED, &ZVFHMIN_IMPLIED, &ZVKN_IMPLIED,
2657     &ZVKNC_IMPLIED, &ZVKNG_IMPLIED, &ZVKNHB_IMPLIED,
2658     &ZVKS_IMPLIED,  &ZVKSC_IMPLIED, &ZVKSG_IMPLIED,
2659     NULL
2660 };
2661 
2662 static Property riscv_cpu_properties[] = {
2663     DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
2664 
2665     {.name = "pmu-mask", .info = &prop_pmu_mask},
2666     {.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */
2667 
2668     {.name = "mmu", .info = &prop_mmu},
2669     {.name = "pmp", .info = &prop_pmp},
2670 
2671     {.name = "priv_spec", .info = &prop_priv_spec},
2672     {.name = "vext_spec", .info = &prop_vext_spec},
2673 
2674     {.name = "vlen", .info = &prop_vlen},
2675     {.name = "elen", .info = &prop_elen},
2676 
2677     {.name = "cbom_blocksize", .info = &prop_cbom_blksize},
2678     {.name = "cbop_blocksize", .info = &prop_cbop_blksize},
2679     {.name = "cboz_blocksize", .info = &prop_cboz_blksize},
2680 
2681      {.name = "mvendorid", .info = &prop_mvendorid},
2682      {.name = "mimpid", .info = &prop_mimpid},
2683      {.name = "marchid", .info = &prop_marchid},
2684 
2685 #ifndef CONFIG_USER_ONLY
2686     DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
2687 #endif
2688 
2689     DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
2690 
2691     DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
2692     DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
2693     DEFINE_PROP_BOOL("rvv_vl_half_avl", RISCVCPU, cfg.rvv_vl_half_avl, false),
2694 
2695     /*
2696      * write_misa() is marked as experimental for now so mark
2697      * it with -x and default to 'false'.
2698      */
2699     DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
2700     DEFINE_PROP_END_OF_LIST(),
2701 };
2702 
2703 #if defined(TARGET_RISCV64)
2704 static void rva22u64_profile_cpu_init(Object *obj)
2705 {
2706     rv64i_bare_cpu_init(obj);
2707 
2708     RVA22U64.enabled = true;
2709 }
2710 
2711 static void rva22s64_profile_cpu_init(Object *obj)
2712 {
2713     rv64i_bare_cpu_init(obj);
2714 
2715     RVA22S64.enabled = true;
2716 }
2717 #endif
2718 
2719 static const gchar *riscv_gdb_arch_name(CPUState *cs)
2720 {
2721     RISCVCPU *cpu = RISCV_CPU(cs);
2722     CPURISCVState *env = &cpu->env;
2723 
2724     switch (riscv_cpu_mxl(env)) {
2725     case MXL_RV32:
2726         return "riscv:rv32";
2727     case MXL_RV64:
2728     case MXL_RV128:
2729         return "riscv:rv64";
2730     default:
2731         g_assert_not_reached();
2732     }
2733 }
2734 
2735 #ifndef CONFIG_USER_ONLY
2736 static int64_t riscv_get_arch_id(CPUState *cs)
2737 {
2738     RISCVCPU *cpu = RISCV_CPU(cs);
2739 
2740     return cpu->env.mhartid;
2741 }
2742 
2743 #include "hw/core/sysemu-cpu-ops.h"
2744 
2745 static const struct SysemuCPUOps riscv_sysemu_ops = {
2746     .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
2747     .write_elf64_note = riscv_cpu_write_elf64_note,
2748     .write_elf32_note = riscv_cpu_write_elf32_note,
2749     .legacy_vmsd = &vmstate_riscv_cpu,
2750 };
2751 #endif
2752 
2753 static void riscv_cpu_common_class_init(ObjectClass *c, void *data)
2754 {
2755     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
2756     CPUClass *cc = CPU_CLASS(c);
2757     DeviceClass *dc = DEVICE_CLASS(c);
2758     ResettableClass *rc = RESETTABLE_CLASS(c);
2759 
2760     device_class_set_parent_realize(dc, riscv_cpu_realize,
2761                                     &mcc->parent_realize);
2762 
2763     resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,
2764                                        &mcc->parent_phases);
2765 
2766     cc->class_by_name = riscv_cpu_class_by_name;
2767     cc->has_work = riscv_cpu_has_work;
2768     cc->mmu_index = riscv_cpu_mmu_index;
2769     cc->dump_state = riscv_cpu_dump_state;
2770     cc->set_pc = riscv_cpu_set_pc;
2771     cc->get_pc = riscv_cpu_get_pc;
2772     cc->gdb_read_register = riscv_cpu_gdb_read_register;
2773     cc->gdb_write_register = riscv_cpu_gdb_write_register;
2774     cc->gdb_stop_before_watchpoint = true;
2775     cc->disas_set_info = riscv_cpu_disas_set_info;
2776 #ifndef CONFIG_USER_ONLY
2777     cc->sysemu_ops = &riscv_sysemu_ops;
2778     cc->get_arch_id = riscv_get_arch_id;
2779 #endif
2780     cc->gdb_arch_name = riscv_gdb_arch_name;
2781 
2782     device_class_set_props(dc, riscv_cpu_properties);
2783 }
2784 
2785 static void riscv_cpu_class_init(ObjectClass *c, void *data)
2786 {
2787     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
2788 
2789     mcc->misa_mxl_max = (uint32_t)(uintptr_t)data;
2790     riscv_cpu_validate_misa_mxl(mcc);
2791 }
2792 
2793 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
2794                                  int max_str_len)
2795 {
2796     const RISCVIsaExtData *edata;
2797     char *old = *isa_str;
2798     char *new = *isa_str;
2799 
2800     for (edata = isa_edata_arr; edata && edata->name; edata++) {
2801         if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
2802             new = g_strconcat(old, "_", edata->name, NULL);
2803             g_free(old);
2804             old = new;
2805         }
2806     }
2807 
2808     *isa_str = new;
2809 }
2810 
2811 char *riscv_isa_string(RISCVCPU *cpu)
2812 {
2813     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
2814     int i;
2815     const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts);
2816     char *isa_str = g_new(char, maxlen);
2817     int xlen = riscv_cpu_max_xlen(mcc);
2818     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", xlen);
2819 
2820     for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
2821         if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
2822             *p++ = qemu_tolower(riscv_single_letter_exts[i]);
2823         }
2824     }
2825     *p = '\0';
2826     if (!cpu->cfg.short_isa_string) {
2827         riscv_isa_string_ext(cpu, &isa_str, maxlen);
2828     }
2829     return isa_str;
2830 }
2831 
2832 #ifndef CONFIG_USER_ONLY
2833 static char **riscv_isa_extensions_list(RISCVCPU *cpu, int *count)
2834 {
2835     int maxlen = ARRAY_SIZE(riscv_single_letter_exts) + ARRAY_SIZE(isa_edata_arr);
2836     char **extensions = g_new(char *, maxlen);
2837 
2838     for (int i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
2839         if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
2840             extensions[*count] = g_new(char, 2);
2841             snprintf(extensions[*count], 2, "%c",
2842                      qemu_tolower(riscv_single_letter_exts[i]));
2843             (*count)++;
2844         }
2845     }
2846 
2847     for (const RISCVIsaExtData *edata = isa_edata_arr; edata->name; edata++) {
2848         if (isa_ext_is_enabled(cpu, edata->ext_enable_offset)) {
2849             extensions[*count] = g_strdup(edata->name);
2850             (*count)++;
2851         }
2852     }
2853 
2854     return extensions;
2855 }
2856 
2857 void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename)
2858 {
2859     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
2860     const size_t maxlen = sizeof("rv128i");
2861     g_autofree char *isa_base = g_new(char, maxlen);
2862     g_autofree char *riscv_isa;
2863     char **isa_extensions;
2864     int count = 0;
2865     int xlen = riscv_cpu_max_xlen(mcc);
2866 
2867     riscv_isa = riscv_isa_string(cpu);
2868     qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", riscv_isa);
2869 
2870     snprintf(isa_base, maxlen, "rv%di", xlen);
2871     qemu_fdt_setprop_string(fdt, nodename, "riscv,isa-base", isa_base);
2872 
2873     isa_extensions = riscv_isa_extensions_list(cpu, &count);
2874     qemu_fdt_setprop_string_array(fdt, nodename, "riscv,isa-extensions",
2875                                   isa_extensions, count);
2876 
2877     for (int i = 0; i < count; i++) {
2878         g_free(isa_extensions[i]);
2879     }
2880 
2881     g_free(isa_extensions);
2882 }
2883 #endif
2884 
2885 #define DEFINE_CPU(type_name, misa_mxl_max, initfn)         \
2886     {                                                       \
2887         .name = (type_name),                                \
2888         .parent = TYPE_RISCV_CPU,                           \
2889         .instance_init = (initfn),                          \
2890         .class_init = riscv_cpu_class_init,                 \
2891         .class_data = (void *)(misa_mxl_max)                \
2892     }
2893 
2894 #define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \
2895     {                                                       \
2896         .name = (type_name),                                \
2897         .parent = TYPE_RISCV_DYNAMIC_CPU,                   \
2898         .instance_init = (initfn),                          \
2899         .class_init = riscv_cpu_class_init,                 \
2900         .class_data = (void *)(misa_mxl_max)                \
2901     }
2902 
2903 #define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn)  \
2904     {                                                       \
2905         .name = (type_name),                                \
2906         .parent = TYPE_RISCV_VENDOR_CPU,                    \
2907         .instance_init = (initfn),                          \
2908         .class_init = riscv_cpu_class_init,                 \
2909         .class_data = (void *)(misa_mxl_max)                \
2910     }
2911 
2912 #define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn)    \
2913     {                                                       \
2914         .name = (type_name),                                \
2915         .parent = TYPE_RISCV_BARE_CPU,                      \
2916         .instance_init = (initfn),                          \
2917         .class_init = riscv_cpu_class_init,                 \
2918         .class_data = (void *)(misa_mxl_max)                \
2919     }
2920 
2921 #define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \
2922     {                                                       \
2923         .name = (type_name),                                \
2924         .parent = TYPE_RISCV_BARE_CPU,                      \
2925         .instance_init = (initfn),                          \
2926         .class_init = riscv_cpu_class_init,                 \
2927         .class_data = (void *)(misa_mxl_max)                \
2928     }
2929 
2930 static const TypeInfo riscv_cpu_type_infos[] = {
2931     {
2932         .name = TYPE_RISCV_CPU,
2933         .parent = TYPE_CPU,
2934         .instance_size = sizeof(RISCVCPU),
2935         .instance_align = __alignof(RISCVCPU),
2936         .instance_init = riscv_cpu_init,
2937         .instance_post_init = riscv_cpu_post_init,
2938         .abstract = true,
2939         .class_size = sizeof(RISCVCPUClass),
2940         .class_init = riscv_cpu_common_class_init,
2941     },
2942     {
2943         .name = TYPE_RISCV_DYNAMIC_CPU,
2944         .parent = TYPE_RISCV_CPU,
2945         .abstract = true,
2946     },
2947     {
2948         .name = TYPE_RISCV_VENDOR_CPU,
2949         .parent = TYPE_RISCV_CPU,
2950         .abstract = true,
2951     },
2952     {
2953         .name = TYPE_RISCV_BARE_CPU,
2954         .parent = TYPE_RISCV_CPU,
2955         .instance_init = riscv_bare_cpu_init,
2956         .abstract = true,
2957     },
2958 #if defined(TARGET_RISCV32)
2959     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX,       MXL_RV32,  riscv_max_cpu_init),
2960 #elif defined(TARGET_RISCV64)
2961     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX,       MXL_RV64,  riscv_max_cpu_init),
2962 #endif
2963 
2964 #if defined(TARGET_RISCV32) || \
2965     (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
2966     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32,    MXL_RV32,  rv32_base_cpu_init),
2967     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_IBEX,       MXL_RV32,  rv32_ibex_cpu_init),
2968     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E31, MXL_RV32,  rv32_sifive_e_cpu_init),
2969     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E34, MXL_RV32,  rv32_imafcu_nommu_cpu_init),
2970     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U34, MXL_RV32,  rv32_sifive_u_cpu_init),
2971     DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32I,        MXL_RV32,  rv32i_bare_cpu_init),
2972     DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV32E,        MXL_RV32,  rv32e_bare_cpu_init),
2973 #endif
2974 
2975 #if (defined(TARGET_RISCV64) && !defined(CONFIG_USER_ONLY))
2976     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_MAX32,     MXL_RV32,  riscv_max_cpu_init),
2977 #endif
2978 
2979 #if defined(TARGET_RISCV64)
2980     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64,    MXL_RV64,  rv64_base_cpu_init),
2981     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_E51, MXL_RV64,  rv64_sifive_e_cpu_init),
2982     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64,  rv64_sifive_u_cpu_init),
2983     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C,   MXL_RV64,  rv64_sifive_u_cpu_init),
2984     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64,  rv64_thead_c906_cpu_init),
2985     DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1,  MXL_RV64,  rv64_veyron_v1_cpu_init),
2986 #ifdef CONFIG_TCG
2987     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128,   MXL_RV128, rv128_base_cpu_init),
2988 #endif /* CONFIG_TCG */
2989     DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64I,        MXL_RV64,  rv64i_bare_cpu_init),
2990     DEFINE_BARE_CPU(TYPE_RISCV_CPU_RV64E,        MXL_RV64,  rv64e_bare_cpu_init),
2991     DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22U64,  MXL_RV64,  rva22u64_profile_cpu_init),
2992     DEFINE_PROFILE_CPU(TYPE_RISCV_CPU_RVA22S64,  MXL_RV64,  rva22s64_profile_cpu_init),
2993 #endif /* TARGET_RISCV64 */
2994 };
2995 
2996 DEFINE_TYPES(riscv_cpu_type_infos)
2997