1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "exec/exec-all.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 #include "fpu/softfloat-helpers.h" 31 32 /* RISC-V CPU definitions */ 33 34 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 35 36 const char * const riscv_int_regnames[] = { 37 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 38 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 39 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 40 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 41 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 42 }; 43 44 const char * const riscv_fpr_regnames[] = { 45 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 46 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 47 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 48 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 49 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 50 "f30/ft10", "f31/ft11" 51 }; 52 53 const char * const riscv_excp_names[] = { 54 "misaligned_fetch", 55 "fault_fetch", 56 "illegal_instruction", 57 "breakpoint", 58 "misaligned_load", 59 "fault_load", 60 "misaligned_store", 61 "fault_store", 62 "user_ecall", 63 "supervisor_ecall", 64 "hypervisor_ecall", 65 "machine_ecall", 66 "exec_page_fault", 67 "load_page_fault", 68 "reserved", 69 "store_page_fault", 70 "reserved", 71 "reserved", 72 "reserved", 73 "reserved", 74 "guest_exec_page_fault", 75 "guest_load_page_fault", 76 "reserved", 77 "guest_store_page_fault", 78 }; 79 80 const char * const riscv_intr_names[] = { 81 "u_software", 82 "s_software", 83 "vs_software", 84 "m_software", 85 "u_timer", 86 "s_timer", 87 "vs_timer", 88 "m_timer", 89 "u_external", 90 "vs_external", 91 "h_external", 92 "m_external", 93 "reserved", 94 "reserved", 95 "reserved", 96 "reserved" 97 }; 98 99 static void set_misa(CPURISCVState *env, target_ulong misa) 100 { 101 env->misa_mask = env->misa = misa; 102 } 103 104 static void set_priv_version(CPURISCVState *env, int priv_ver) 105 { 106 env->priv_ver = priv_ver; 107 } 108 109 static void set_feature(CPURISCVState *env, int feature) 110 { 111 env->features |= (1ULL << feature); 112 } 113 114 static void set_resetvec(CPURISCVState *env, int resetvec) 115 { 116 #ifndef CONFIG_USER_ONLY 117 env->resetvec = resetvec; 118 #endif 119 } 120 121 static void riscv_any_cpu_init(Object *obj) 122 { 123 CPURISCVState *env = &RISCV_CPU(obj)->env; 124 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); 125 set_priv_version(env, PRIV_VERSION_1_11_0); 126 set_resetvec(env, DEFAULT_RSTVEC); 127 } 128 129 #if defined(TARGET_RISCV32) 130 131 static void riscv_base32_cpu_init(Object *obj) 132 { 133 CPURISCVState *env = &RISCV_CPU(obj)->env; 134 /* We set this in the realise function */ 135 set_misa(env, 0); 136 set_resetvec(env, DEFAULT_RSTVEC); 137 } 138 139 static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) 140 { 141 CPURISCVState *env = &RISCV_CPU(obj)->env; 142 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 143 set_priv_version(env, PRIV_VERSION_1_10_0); 144 set_resetvec(env, DEFAULT_RSTVEC); 145 } 146 147 static void rv32imcu_nommu_cpu_init(Object *obj) 148 { 149 CPURISCVState *env = &RISCV_CPU(obj)->env; 150 set_misa(env, RV32 | RVI | RVM | RVC | RVU); 151 set_priv_version(env, PRIV_VERSION_1_10_0); 152 set_resetvec(env, 0x8090); 153 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 154 } 155 156 static void rv32imacu_nommu_cpu_init(Object *obj) 157 { 158 CPURISCVState *env = &RISCV_CPU(obj)->env; 159 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); 160 set_priv_version(env, PRIV_VERSION_1_10_0); 161 set_resetvec(env, DEFAULT_RSTVEC); 162 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 163 } 164 165 static void rv32imafcu_nommu_cpu_init(Object *obj) 166 { 167 CPURISCVState *env = &RISCV_CPU(obj)->env; 168 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); 169 set_priv_version(env, PRIV_VERSION_1_10_0); 170 set_resetvec(env, DEFAULT_RSTVEC); 171 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 172 } 173 174 #elif defined(TARGET_RISCV64) 175 176 static void riscv_base64_cpu_init(Object *obj) 177 { 178 CPURISCVState *env = &RISCV_CPU(obj)->env; 179 /* We set this in the realise function */ 180 set_misa(env, 0); 181 set_resetvec(env, DEFAULT_RSTVEC); 182 } 183 184 static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) 185 { 186 CPURISCVState *env = &RISCV_CPU(obj)->env; 187 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 188 set_priv_version(env, PRIV_VERSION_1_10_0); 189 set_resetvec(env, DEFAULT_RSTVEC); 190 } 191 192 static void rv64imacu_nommu_cpu_init(Object *obj) 193 { 194 CPURISCVState *env = &RISCV_CPU(obj)->env; 195 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); 196 set_priv_version(env, PRIV_VERSION_1_10_0); 197 set_resetvec(env, DEFAULT_RSTVEC); 198 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 199 } 200 201 #endif 202 203 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 204 { 205 ObjectClass *oc; 206 char *typename; 207 char **cpuname; 208 209 cpuname = g_strsplit(cpu_model, ",", 1); 210 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 211 oc = object_class_by_name(typename); 212 g_strfreev(cpuname); 213 g_free(typename); 214 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 215 object_class_is_abstract(oc)) { 216 return NULL; 217 } 218 return oc; 219 } 220 221 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 222 { 223 RISCVCPU *cpu = RISCV_CPU(cs); 224 CPURISCVState *env = &cpu->env; 225 int i; 226 227 #if !defined(CONFIG_USER_ONLY) 228 if (riscv_has_ext(env, RVH)) { 229 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 230 } 231 #endif 232 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 233 #ifndef CONFIG_USER_ONLY 234 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); 235 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); 236 #ifdef TARGET_RISCV32 237 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush); 238 #endif 239 if (riscv_has_ext(env, RVH)) { 240 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); 241 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus); 242 } 243 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); 244 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); 245 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); 246 if (riscv_has_ext(env, RVH)) { 247 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); 248 } 249 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); 250 if (riscv_has_ext(env, RVH)) { 251 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); 252 } 253 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); 254 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); 255 if (riscv_has_ext(env, RVH)) { 256 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); 257 } 258 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); 259 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); 260 if (riscv_has_ext(env, RVH)) { 261 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); 262 } 263 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); 264 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); 265 if (riscv_has_ext(env, RVH)) { 266 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); 267 } 268 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); 269 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr); 270 if (riscv_has_ext(env, RVH)) { 271 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); 272 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); 273 } 274 #endif 275 276 for (i = 0; i < 32; i++) { 277 qemu_fprintf(f, " %s " TARGET_FMT_lx, 278 riscv_int_regnames[i], env->gpr[i]); 279 if ((i & 3) == 3) { 280 qemu_fprintf(f, "\n"); 281 } 282 } 283 if (flags & CPU_DUMP_FPU) { 284 for (i = 0; i < 32; i++) { 285 qemu_fprintf(f, " %s %016" PRIx64, 286 riscv_fpr_regnames[i], env->fpr[i]); 287 if ((i & 3) == 3) { 288 qemu_fprintf(f, "\n"); 289 } 290 } 291 } 292 } 293 294 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 295 { 296 RISCVCPU *cpu = RISCV_CPU(cs); 297 CPURISCVState *env = &cpu->env; 298 env->pc = value; 299 } 300 301 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 302 { 303 RISCVCPU *cpu = RISCV_CPU(cs); 304 CPURISCVState *env = &cpu->env; 305 env->pc = tb->pc; 306 } 307 308 static bool riscv_cpu_has_work(CPUState *cs) 309 { 310 #ifndef CONFIG_USER_ONLY 311 RISCVCPU *cpu = RISCV_CPU(cs); 312 CPURISCVState *env = &cpu->env; 313 /* 314 * Definition of the WFI instruction requires it to ignore the privilege 315 * mode and delegation registers, but respect individual enables 316 */ 317 return (env->mip & env->mie) != 0; 318 #else 319 return true; 320 #endif 321 } 322 323 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 324 target_ulong *data) 325 { 326 env->pc = data[0]; 327 } 328 329 static void riscv_cpu_reset(DeviceState *dev) 330 { 331 CPUState *cs = CPU(dev); 332 RISCVCPU *cpu = RISCV_CPU(cs); 333 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 334 CPURISCVState *env = &cpu->env; 335 336 mcc->parent_reset(dev); 337 #ifndef CONFIG_USER_ONLY 338 env->priv = PRV_M; 339 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 340 env->mcause = 0; 341 env->pc = env->resetvec; 342 #endif 343 cs->exception_index = EXCP_NONE; 344 env->load_res = -1; 345 set_default_nan_mode(1, &env->fp_status); 346 } 347 348 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 349 { 350 #if defined(TARGET_RISCV32) 351 info->print_insn = print_insn_riscv32; 352 #elif defined(TARGET_RISCV64) 353 info->print_insn = print_insn_riscv64; 354 #endif 355 } 356 357 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 358 { 359 CPUState *cs = CPU(dev); 360 RISCVCPU *cpu = RISCV_CPU(dev); 361 CPURISCVState *env = &cpu->env; 362 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 363 int priv_version = PRIV_VERSION_1_11_0; 364 target_ulong target_misa = 0; 365 Error *local_err = NULL; 366 367 cpu_exec_realizefn(cs, &local_err); 368 if (local_err != NULL) { 369 error_propagate(errp, local_err); 370 return; 371 } 372 373 if (cpu->cfg.priv_spec) { 374 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 375 priv_version = PRIV_VERSION_1_11_0; 376 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 377 priv_version = PRIV_VERSION_1_10_0; 378 } else { 379 error_setg(errp, 380 "Unsupported privilege spec version '%s'", 381 cpu->cfg.priv_spec); 382 return; 383 } 384 } 385 386 set_priv_version(env, priv_version); 387 388 if (cpu->cfg.mmu) { 389 set_feature(env, RISCV_FEATURE_MMU); 390 } 391 392 if (cpu->cfg.pmp) { 393 set_feature(env, RISCV_FEATURE_PMP); 394 } 395 396 /* If misa isn't set (rv32 and rv64 machines) set it here */ 397 if (!env->misa) { 398 /* Do some ISA extension error checking */ 399 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 400 error_setg(errp, 401 "I and E extensions are incompatible"); 402 return; 403 } 404 405 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 406 error_setg(errp, 407 "Either I or E extension must be set"); 408 return; 409 } 410 411 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 412 cpu->cfg.ext_a & cpu->cfg.ext_f & 413 cpu->cfg.ext_d)) { 414 warn_report("Setting G will also set IMAFD"); 415 cpu->cfg.ext_i = true; 416 cpu->cfg.ext_m = true; 417 cpu->cfg.ext_a = true; 418 cpu->cfg.ext_f = true; 419 cpu->cfg.ext_d = true; 420 } 421 422 /* Set the ISA extensions, checks should have happened above */ 423 if (cpu->cfg.ext_i) { 424 target_misa |= RVI; 425 } 426 if (cpu->cfg.ext_e) { 427 target_misa |= RVE; 428 } 429 if (cpu->cfg.ext_m) { 430 target_misa |= RVM; 431 } 432 if (cpu->cfg.ext_a) { 433 target_misa |= RVA; 434 } 435 if (cpu->cfg.ext_f) { 436 target_misa |= RVF; 437 } 438 if (cpu->cfg.ext_d) { 439 target_misa |= RVD; 440 } 441 if (cpu->cfg.ext_c) { 442 target_misa |= RVC; 443 } 444 if (cpu->cfg.ext_s) { 445 target_misa |= RVS; 446 } 447 if (cpu->cfg.ext_u) { 448 target_misa |= RVU; 449 } 450 if (cpu->cfg.ext_h) { 451 target_misa |= RVH; 452 } 453 454 set_misa(env, RVXLEN | target_misa); 455 } 456 457 riscv_cpu_register_gdb_regs_for_features(cs); 458 459 qemu_init_vcpu(cs); 460 cpu_reset(cs); 461 462 mcc->parent_realize(dev, errp); 463 } 464 465 static void riscv_cpu_init(Object *obj) 466 { 467 RISCVCPU *cpu = RISCV_CPU(obj); 468 469 cpu_set_cpustate_pointers(cpu); 470 } 471 472 #ifndef CONFIG_USER_ONLY 473 static const VMStateDescription vmstate_riscv_cpu = { 474 .name = "cpu", 475 .unmigratable = 1, 476 }; 477 #endif 478 479 static Property riscv_cpu_properties[] = { 480 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 481 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 482 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 483 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 484 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 485 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 486 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 487 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 488 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 489 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 490 /* This is experimental so mark with 'x-' */ 491 DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), 492 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 493 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 494 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 495 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 496 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 497 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 498 DEFINE_PROP_END_OF_LIST(), 499 }; 500 501 static void riscv_cpu_class_init(ObjectClass *c, void *data) 502 { 503 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 504 CPUClass *cc = CPU_CLASS(c); 505 DeviceClass *dc = DEVICE_CLASS(c); 506 507 device_class_set_parent_realize(dc, riscv_cpu_realize, 508 &mcc->parent_realize); 509 510 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 511 512 cc->class_by_name = riscv_cpu_class_by_name; 513 cc->has_work = riscv_cpu_has_work; 514 cc->do_interrupt = riscv_cpu_do_interrupt; 515 cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt; 516 cc->dump_state = riscv_cpu_dump_state; 517 cc->set_pc = riscv_cpu_set_pc; 518 cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb; 519 cc->gdb_read_register = riscv_cpu_gdb_read_register; 520 cc->gdb_write_register = riscv_cpu_gdb_write_register; 521 cc->gdb_num_core_regs = 33; 522 #if defined(TARGET_RISCV32) 523 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 524 #elif defined(TARGET_RISCV64) 525 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 526 #endif 527 cc->gdb_stop_before_watchpoint = true; 528 cc->disas_set_info = riscv_cpu_disas_set_info; 529 #ifndef CONFIG_USER_ONLY 530 cc->do_transaction_failed = riscv_cpu_do_transaction_failed; 531 cc->do_unaligned_access = riscv_cpu_do_unaligned_access; 532 cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; 533 /* For now, mark unmigratable: */ 534 cc->vmsd = &vmstate_riscv_cpu; 535 #endif 536 #ifdef CONFIG_TCG 537 cc->tcg_initialize = riscv_translate_init; 538 cc->tlb_fill = riscv_cpu_tlb_fill; 539 #endif 540 device_class_set_props(dc, riscv_cpu_properties); 541 } 542 543 char *riscv_isa_string(RISCVCPU *cpu) 544 { 545 int i; 546 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 547 char *isa_str = g_new(char, maxlen); 548 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 549 for (i = 0; i < sizeof(riscv_exts); i++) { 550 if (cpu->env.misa & RV(riscv_exts[i])) { 551 *p++ = qemu_tolower(riscv_exts[i]); 552 } 553 } 554 *p = '\0'; 555 return isa_str; 556 } 557 558 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 559 { 560 ObjectClass *class_a = (ObjectClass *)a; 561 ObjectClass *class_b = (ObjectClass *)b; 562 const char *name_a, *name_b; 563 564 name_a = object_class_get_name(class_a); 565 name_b = object_class_get_name(class_b); 566 return strcmp(name_a, name_b); 567 } 568 569 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 570 { 571 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 572 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 573 574 qemu_printf("%.*s\n", len, typename); 575 } 576 577 void riscv_cpu_list(void) 578 { 579 GSList *list; 580 581 list = object_class_get_list(TYPE_RISCV_CPU, false); 582 list = g_slist_sort(list, riscv_cpu_list_compare); 583 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 584 g_slist_free(list); 585 } 586 587 #define DEFINE_CPU(type_name, initfn) \ 588 { \ 589 .name = type_name, \ 590 .parent = TYPE_RISCV_CPU, \ 591 .instance_init = initfn \ 592 } 593 594 static const TypeInfo riscv_cpu_type_infos[] = { 595 { 596 .name = TYPE_RISCV_CPU, 597 .parent = TYPE_CPU, 598 .instance_size = sizeof(RISCVCPU), 599 .instance_init = riscv_cpu_init, 600 .abstract = true, 601 .class_size = sizeof(RISCVCPUClass), 602 .class_init = riscv_cpu_class_init, 603 }, 604 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 605 #if defined(TARGET_RISCV32) 606 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), 607 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32imcu_nommu_cpu_init), 608 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), 609 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), 610 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), 611 #elif defined(TARGET_RISCV64) 612 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), 613 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), 614 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init), 615 #endif 616 }; 617 618 DEFINE_TYPES(riscv_cpu_type_infos) 619