1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "exec/exec-all.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "fpu/softfloat-helpers.h" 32 #include "sysemu/kvm.h" 33 #include "kvm_riscv.h" 34 35 /* RISC-V CPU definitions */ 36 37 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 38 39 struct isa_ext_data { 40 const char *name; 41 bool enabled; 42 }; 43 44 const char * const riscv_int_regnames[] = { 45 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 46 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 47 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 48 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 49 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 50 }; 51 52 const char * const riscv_int_regnamesh[] = { 53 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 54 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 55 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 56 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 57 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 58 "x30h/t5h", "x31h/t6h" 59 }; 60 61 const char * const riscv_fpr_regnames[] = { 62 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 63 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 64 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 65 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 66 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 67 "f30/ft10", "f31/ft11" 68 }; 69 70 static const char * const riscv_excp_names[] = { 71 "misaligned_fetch", 72 "fault_fetch", 73 "illegal_instruction", 74 "breakpoint", 75 "misaligned_load", 76 "fault_load", 77 "misaligned_store", 78 "fault_store", 79 "user_ecall", 80 "supervisor_ecall", 81 "hypervisor_ecall", 82 "machine_ecall", 83 "exec_page_fault", 84 "load_page_fault", 85 "reserved", 86 "store_page_fault", 87 "reserved", 88 "reserved", 89 "reserved", 90 "reserved", 91 "guest_exec_page_fault", 92 "guest_load_page_fault", 93 "reserved", 94 "guest_store_page_fault", 95 }; 96 97 static const char * const riscv_intr_names[] = { 98 "u_software", 99 "s_software", 100 "vs_software", 101 "m_software", 102 "u_timer", 103 "s_timer", 104 "vs_timer", 105 "m_timer", 106 "u_external", 107 "s_external", 108 "vs_external", 109 "m_external", 110 "reserved", 111 "reserved", 112 "reserved", 113 "reserved" 114 }; 115 116 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 117 { 118 if (async) { 119 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 120 riscv_intr_names[cause] : "(unknown)"; 121 } else { 122 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 123 riscv_excp_names[cause] : "(unknown)"; 124 } 125 } 126 127 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 128 { 129 env->misa_mxl_max = env->misa_mxl = mxl; 130 env->misa_ext_mask = env->misa_ext = ext; 131 } 132 133 static void set_priv_version(CPURISCVState *env, int priv_ver) 134 { 135 env->priv_ver = priv_ver; 136 } 137 138 static void set_vext_version(CPURISCVState *env, int vext_ver) 139 { 140 env->vext_ver = vext_ver; 141 } 142 143 static void set_resetvec(CPURISCVState *env, target_ulong resetvec) 144 { 145 #ifndef CONFIG_USER_ONLY 146 env->resetvec = resetvec; 147 #endif 148 } 149 150 static void riscv_any_cpu_init(Object *obj) 151 { 152 CPURISCVState *env = &RISCV_CPU(obj)->env; 153 #if defined(TARGET_RISCV32) 154 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 155 #elif defined(TARGET_RISCV64) 156 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 157 #endif 158 set_priv_version(env, PRIV_VERSION_1_12_0); 159 } 160 161 #if defined(TARGET_RISCV64) 162 static void rv64_base_cpu_init(Object *obj) 163 { 164 CPURISCVState *env = &RISCV_CPU(obj)->env; 165 /* We set this in the realise function */ 166 set_misa(env, MXL_RV64, 0); 167 } 168 169 static void rv64_sifive_u_cpu_init(Object *obj) 170 { 171 CPURISCVState *env = &RISCV_CPU(obj)->env; 172 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 173 set_priv_version(env, PRIV_VERSION_1_10_0); 174 } 175 176 static void rv64_sifive_e_cpu_init(Object *obj) 177 { 178 CPURISCVState *env = &RISCV_CPU(obj)->env; 179 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 180 set_priv_version(env, PRIV_VERSION_1_10_0); 181 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 182 } 183 184 static void rv128_base_cpu_init(Object *obj) 185 { 186 if (qemu_tcg_mttcg_enabled()) { 187 /* Missing 128-bit aligned atomics */ 188 error_report("128-bit RISC-V currently does not work with Multi " 189 "Threaded TCG. Please use: -accel tcg,thread=single"); 190 exit(EXIT_FAILURE); 191 } 192 CPURISCVState *env = &RISCV_CPU(obj)->env; 193 /* We set this in the realise function */ 194 set_misa(env, MXL_RV128, 0); 195 } 196 #else 197 static void rv32_base_cpu_init(Object *obj) 198 { 199 CPURISCVState *env = &RISCV_CPU(obj)->env; 200 /* We set this in the realise function */ 201 set_misa(env, MXL_RV32, 0); 202 } 203 204 static void rv32_sifive_u_cpu_init(Object *obj) 205 { 206 CPURISCVState *env = &RISCV_CPU(obj)->env; 207 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 208 set_priv_version(env, PRIV_VERSION_1_10_0); 209 } 210 211 static void rv32_sifive_e_cpu_init(Object *obj) 212 { 213 CPURISCVState *env = &RISCV_CPU(obj)->env; 214 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 215 set_priv_version(env, PRIV_VERSION_1_10_0); 216 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 217 } 218 219 static void rv32_ibex_cpu_init(Object *obj) 220 { 221 CPURISCVState *env = &RISCV_CPU(obj)->env; 222 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 223 set_priv_version(env, PRIV_VERSION_1_10_0); 224 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 225 qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); 226 } 227 228 static void rv32_imafcu_nommu_cpu_init(Object *obj) 229 { 230 CPURISCVState *env = &RISCV_CPU(obj)->env; 231 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 232 set_priv_version(env, PRIV_VERSION_1_10_0); 233 set_resetvec(env, DEFAULT_RSTVEC); 234 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 235 } 236 #endif 237 238 #if defined(CONFIG_KVM) 239 static void riscv_host_cpu_init(Object *obj) 240 { 241 CPURISCVState *env = &RISCV_CPU(obj)->env; 242 #if defined(TARGET_RISCV32) 243 set_misa(env, MXL_RV32, 0); 244 #elif defined(TARGET_RISCV64) 245 set_misa(env, MXL_RV64, 0); 246 #endif 247 } 248 #endif 249 250 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 251 { 252 ObjectClass *oc; 253 char *typename; 254 char **cpuname; 255 256 cpuname = g_strsplit(cpu_model, ",", 1); 257 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 258 oc = object_class_by_name(typename); 259 g_strfreev(cpuname); 260 g_free(typename); 261 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 262 object_class_is_abstract(oc)) { 263 return NULL; 264 } 265 return oc; 266 } 267 268 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 269 { 270 RISCVCPU *cpu = RISCV_CPU(cs); 271 CPURISCVState *env = &cpu->env; 272 int i; 273 274 #if !defined(CONFIG_USER_ONLY) 275 if (riscv_has_ext(env, RVH)) { 276 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 277 } 278 #endif 279 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 280 #ifndef CONFIG_USER_ONLY 281 { 282 static const int dump_csrs[] = { 283 CSR_MHARTID, 284 CSR_MSTATUS, 285 CSR_MSTATUSH, 286 CSR_HSTATUS, 287 CSR_VSSTATUS, 288 CSR_MIP, 289 CSR_MIE, 290 CSR_MIDELEG, 291 CSR_HIDELEG, 292 CSR_MEDELEG, 293 CSR_HEDELEG, 294 CSR_MTVEC, 295 CSR_STVEC, 296 CSR_VSTVEC, 297 CSR_MEPC, 298 CSR_SEPC, 299 CSR_VSEPC, 300 CSR_MCAUSE, 301 CSR_SCAUSE, 302 CSR_VSCAUSE, 303 CSR_MTVAL, 304 CSR_STVAL, 305 CSR_HTVAL, 306 CSR_MTVAL2, 307 CSR_MSCRATCH, 308 CSR_SSCRATCH, 309 CSR_SATP, 310 CSR_MMTE, 311 CSR_UPMBASE, 312 CSR_UPMMASK, 313 CSR_SPMBASE, 314 CSR_SPMMASK, 315 CSR_MPMBASE, 316 CSR_MPMMASK, 317 }; 318 319 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 320 int csrno = dump_csrs[i]; 321 target_ulong val = 0; 322 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 323 324 /* 325 * Rely on the smode, hmode, etc, predicates within csr.c 326 * to do the filtering of the registers that are present. 327 */ 328 if (res == RISCV_EXCP_NONE) { 329 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 330 csr_ops[csrno].name, val); 331 } 332 } 333 } 334 #endif 335 336 for (i = 0; i < 32; i++) { 337 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 338 riscv_int_regnames[i], env->gpr[i]); 339 if ((i & 3) == 3) { 340 qemu_fprintf(f, "\n"); 341 } 342 } 343 if (flags & CPU_DUMP_FPU) { 344 for (i = 0; i < 32; i++) { 345 qemu_fprintf(f, " %-8s %016" PRIx64, 346 riscv_fpr_regnames[i], env->fpr[i]); 347 if ((i & 3) == 3) { 348 qemu_fprintf(f, "\n"); 349 } 350 } 351 } 352 } 353 354 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 355 { 356 RISCVCPU *cpu = RISCV_CPU(cs); 357 CPURISCVState *env = &cpu->env; 358 359 if (env->xl == MXL_RV32) { 360 env->pc = (int32_t)value; 361 } else { 362 env->pc = value; 363 } 364 } 365 366 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 367 const TranslationBlock *tb) 368 { 369 RISCVCPU *cpu = RISCV_CPU(cs); 370 CPURISCVState *env = &cpu->env; 371 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 372 373 if (xl == MXL_RV32) { 374 env->pc = (int32_t)tb->pc; 375 } else { 376 env->pc = tb->pc; 377 } 378 } 379 380 static bool riscv_cpu_has_work(CPUState *cs) 381 { 382 #ifndef CONFIG_USER_ONLY 383 RISCVCPU *cpu = RISCV_CPU(cs); 384 CPURISCVState *env = &cpu->env; 385 /* 386 * Definition of the WFI instruction requires it to ignore the privilege 387 * mode and delegation registers, but respect individual enables 388 */ 389 return (env->mip & env->mie) != 0; 390 #else 391 return true; 392 #endif 393 } 394 395 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 396 target_ulong *data) 397 { 398 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 399 if (xl == MXL_RV32) { 400 env->pc = (int32_t)data[0]; 401 } else { 402 env->pc = data[0]; 403 } 404 } 405 406 static void riscv_cpu_reset(DeviceState *dev) 407 { 408 #ifndef CONFIG_USER_ONLY 409 uint8_t iprio; 410 int i, irq, rdzero; 411 #endif 412 CPUState *cs = CPU(dev); 413 RISCVCPU *cpu = RISCV_CPU(cs); 414 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 415 CPURISCVState *env = &cpu->env; 416 417 mcc->parent_reset(dev); 418 #ifndef CONFIG_USER_ONLY 419 env->misa_mxl = env->misa_mxl_max; 420 env->priv = PRV_M; 421 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 422 if (env->misa_mxl > MXL_RV32) { 423 /* 424 * The reset status of SXL/UXL is undefined, but mstatus is WARL 425 * and we must ensure that the value after init is valid for read. 426 */ 427 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 428 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 429 if (riscv_has_ext(env, RVH)) { 430 env->vsstatus = set_field(env->vsstatus, 431 MSTATUS64_SXL, env->misa_mxl); 432 env->vsstatus = set_field(env->vsstatus, 433 MSTATUS64_UXL, env->misa_mxl); 434 env->mstatus_hs = set_field(env->mstatus_hs, 435 MSTATUS64_SXL, env->misa_mxl); 436 env->mstatus_hs = set_field(env->mstatus_hs, 437 MSTATUS64_UXL, env->misa_mxl); 438 } 439 } 440 env->mcause = 0; 441 env->miclaim = MIP_SGEIP; 442 env->pc = env->resetvec; 443 env->two_stage_lookup = false; 444 445 /* Initialized default priorities of local interrupts. */ 446 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 447 iprio = riscv_cpu_default_priority(i); 448 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 449 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 450 env->hviprio[i] = 0; 451 } 452 i = 0; 453 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 454 if (!rdzero) { 455 env->hviprio[irq] = env->miprio[irq]; 456 } 457 i++; 458 } 459 /* mmte is supposed to have pm.current hardwired to 1 */ 460 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 461 #endif 462 env->xl = riscv_cpu_mxl(env); 463 riscv_cpu_update_mask(env); 464 cs->exception_index = RISCV_EXCP_NONE; 465 env->load_res = -1; 466 set_default_nan_mode(1, &env->fp_status); 467 468 #ifndef CONFIG_USER_ONLY 469 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 470 riscv_trigger_init(env); 471 } 472 473 if (kvm_enabled()) { 474 kvm_riscv_reset_vcpu(cpu); 475 } 476 #endif 477 } 478 479 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 480 { 481 RISCVCPU *cpu = RISCV_CPU(s); 482 483 switch (riscv_cpu_mxl(&cpu->env)) { 484 case MXL_RV32: 485 info->print_insn = print_insn_riscv32; 486 break; 487 case MXL_RV64: 488 info->print_insn = print_insn_riscv64; 489 break; 490 case MXL_RV128: 491 info->print_insn = print_insn_riscv128; 492 break; 493 default: 494 g_assert_not_reached(); 495 } 496 } 497 498 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 499 { 500 CPUState *cs = CPU(dev); 501 RISCVCPU *cpu = RISCV_CPU(dev); 502 CPURISCVState *env = &cpu->env; 503 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 504 CPUClass *cc = CPU_CLASS(mcc); 505 int priv_version = 0; 506 Error *local_err = NULL; 507 508 cpu_exec_realizefn(cs, &local_err); 509 if (local_err != NULL) { 510 error_propagate(errp, local_err); 511 return; 512 } 513 514 if (cpu->cfg.priv_spec) { 515 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 516 priv_version = PRIV_VERSION_1_12_0; 517 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 518 priv_version = PRIV_VERSION_1_11_0; 519 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 520 priv_version = PRIV_VERSION_1_10_0; 521 } else { 522 error_setg(errp, 523 "Unsupported privilege spec version '%s'", 524 cpu->cfg.priv_spec); 525 return; 526 } 527 } 528 529 if (priv_version) { 530 set_priv_version(env, priv_version); 531 } else if (!env->priv_ver) { 532 set_priv_version(env, PRIV_VERSION_1_12_0); 533 } 534 535 if (cpu->cfg.mmu) { 536 riscv_set_feature(env, RISCV_FEATURE_MMU); 537 } 538 539 if (cpu->cfg.pmp) { 540 riscv_set_feature(env, RISCV_FEATURE_PMP); 541 542 /* 543 * Enhanced PMP should only be available 544 * on harts with PMP support 545 */ 546 if (cpu->cfg.epmp) { 547 riscv_set_feature(env, RISCV_FEATURE_EPMP); 548 } 549 } 550 551 if (cpu->cfg.aia) { 552 riscv_set_feature(env, RISCV_FEATURE_AIA); 553 } 554 555 if (cpu->cfg.debug) { 556 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 557 } 558 559 set_resetvec(env, cpu->cfg.resetvec); 560 561 /* Validate that MISA_MXL is set properly. */ 562 switch (env->misa_mxl_max) { 563 #ifdef TARGET_RISCV64 564 case MXL_RV64: 565 case MXL_RV128: 566 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 567 break; 568 #endif 569 case MXL_RV32: 570 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 571 break; 572 default: 573 g_assert_not_reached(); 574 } 575 assert(env->misa_mxl_max == env->misa_mxl); 576 577 /* If only MISA_EXT is unset for misa, then set it from properties */ 578 if (env->misa_ext == 0) { 579 uint32_t ext = 0; 580 581 /* Do some ISA extension error checking */ 582 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 583 error_setg(errp, 584 "I and E extensions are incompatible"); 585 return; 586 } 587 588 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 589 error_setg(errp, 590 "Either I or E extension must be set"); 591 return; 592 } 593 594 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 595 cpu->cfg.ext_a & cpu->cfg.ext_f & 596 cpu->cfg.ext_d)) { 597 warn_report("Setting G will also set IMAFD"); 598 cpu->cfg.ext_i = true; 599 cpu->cfg.ext_m = true; 600 cpu->cfg.ext_a = true; 601 cpu->cfg.ext_f = true; 602 cpu->cfg.ext_d = true; 603 } 604 605 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || 606 cpu->cfg.ext_zhinxmin) { 607 cpu->cfg.ext_zfinx = true; 608 } 609 610 /* Set the ISA extensions, checks should have happened above */ 611 if (cpu->cfg.ext_i) { 612 ext |= RVI; 613 } 614 if (cpu->cfg.ext_e) { 615 ext |= RVE; 616 } 617 if (cpu->cfg.ext_m) { 618 ext |= RVM; 619 } 620 if (cpu->cfg.ext_a) { 621 ext |= RVA; 622 } 623 if (cpu->cfg.ext_f) { 624 ext |= RVF; 625 } 626 if (cpu->cfg.ext_d) { 627 ext |= RVD; 628 } 629 if (cpu->cfg.ext_c) { 630 ext |= RVC; 631 } 632 if (cpu->cfg.ext_s) { 633 ext |= RVS; 634 } 635 if (cpu->cfg.ext_u) { 636 ext |= RVU; 637 } 638 if (cpu->cfg.ext_h) { 639 ext |= RVH; 640 } 641 if (cpu->cfg.ext_v) { 642 int vext_version = VEXT_VERSION_1_00_0; 643 ext |= RVV; 644 if (!is_power_of_2(cpu->cfg.vlen)) { 645 error_setg(errp, 646 "Vector extension VLEN must be power of 2"); 647 return; 648 } 649 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 650 error_setg(errp, 651 "Vector extension implementation only supports VLEN " 652 "in the range [128, %d]", RV_VLEN_MAX); 653 return; 654 } 655 if (!is_power_of_2(cpu->cfg.elen)) { 656 error_setg(errp, 657 "Vector extension ELEN must be power of 2"); 658 return; 659 } 660 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 661 error_setg(errp, 662 "Vector extension implementation only supports ELEN " 663 "in the range [8, 64]"); 664 return; 665 } 666 if (cpu->cfg.vext_spec) { 667 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 668 vext_version = VEXT_VERSION_1_00_0; 669 } else { 670 error_setg(errp, 671 "Unsupported vector spec version '%s'", 672 cpu->cfg.vext_spec); 673 return; 674 } 675 } else { 676 qemu_log("vector version is not specified, " 677 "use the default value v1.0\n"); 678 } 679 set_vext_version(env, vext_version); 680 } 681 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 682 error_setg(errp, "Zve32f/Zve64f extension depends upon RVF."); 683 return; 684 } 685 if (cpu->cfg.ext_j) { 686 ext |= RVJ; 687 } 688 if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh || 689 cpu->cfg.ext_zfhmin)) { 690 error_setg(errp, 691 "'Zfinx' cannot be supported together with 'F', 'D', 'Zfh'," 692 " 'Zfhmin'"); 693 return; 694 } 695 696 set_misa(env, env->misa_mxl, ext); 697 } 698 699 riscv_cpu_register_gdb_regs_for_features(cs); 700 701 qemu_init_vcpu(cs); 702 cpu_reset(cs); 703 704 mcc->parent_realize(dev, errp); 705 } 706 707 #ifndef CONFIG_USER_ONLY 708 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 709 { 710 RISCVCPU *cpu = RISCV_CPU(opaque); 711 CPURISCVState *env = &cpu->env; 712 713 if (irq < IRQ_LOCAL_MAX) { 714 switch (irq) { 715 case IRQ_U_SOFT: 716 case IRQ_S_SOFT: 717 case IRQ_VS_SOFT: 718 case IRQ_M_SOFT: 719 case IRQ_U_TIMER: 720 case IRQ_S_TIMER: 721 case IRQ_VS_TIMER: 722 case IRQ_M_TIMER: 723 case IRQ_U_EXT: 724 case IRQ_VS_EXT: 725 case IRQ_M_EXT: 726 if (kvm_enabled()) { 727 kvm_riscv_set_irq(cpu, irq, level); 728 } else { 729 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 730 } 731 break; 732 case IRQ_S_EXT: 733 if (kvm_enabled()) { 734 kvm_riscv_set_irq(cpu, irq, level); 735 } else { 736 env->external_seip = level; 737 riscv_cpu_update_mip(cpu, 1 << irq, 738 BOOL_TO_MASK(level | env->software_seip)); 739 } 740 break; 741 default: 742 g_assert_not_reached(); 743 } 744 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 745 /* Require H-extension for handling guest local interrupts */ 746 if (!riscv_has_ext(env, RVH)) { 747 g_assert_not_reached(); 748 } 749 750 /* Compute bit position in HGEIP CSR */ 751 irq = irq - IRQ_LOCAL_MAX + 1; 752 if (env->geilen < irq) { 753 g_assert_not_reached(); 754 } 755 756 /* Update HGEIP CSR */ 757 env->hgeip &= ~((target_ulong)1 << irq); 758 if (level) { 759 env->hgeip |= (target_ulong)1 << irq; 760 } 761 762 /* Update mip.SGEIP bit */ 763 riscv_cpu_update_mip(cpu, MIP_SGEIP, 764 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 765 } else { 766 g_assert_not_reached(); 767 } 768 } 769 #endif /* CONFIG_USER_ONLY */ 770 771 static void riscv_cpu_init(Object *obj) 772 { 773 RISCVCPU *cpu = RISCV_CPU(obj); 774 775 cpu_set_cpustate_pointers(cpu); 776 777 #ifndef CONFIG_USER_ONLY 778 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 779 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 780 #endif /* CONFIG_USER_ONLY */ 781 } 782 783 static Property riscv_cpu_properties[] = { 784 /* Defaults for standard extensions */ 785 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 786 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 787 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 788 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 789 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 790 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 791 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 792 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 793 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 794 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 795 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 796 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 797 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 798 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 799 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 800 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 801 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 802 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 803 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 804 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 805 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 806 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 807 808 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 809 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 810 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 811 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 812 813 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 814 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 815 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 816 817 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 818 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 819 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 820 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 821 822 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 823 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 824 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 825 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 826 827 /* Vendor-specific custom extensions */ 828 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 829 830 /* These are experimental so mark with 'x-' */ 831 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 832 /* ePMP 0.9.3 */ 833 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 834 DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), 835 836 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 837 DEFINE_PROP_END_OF_LIST(), 838 }; 839 840 static gchar *riscv_gdb_arch_name(CPUState *cs) 841 { 842 RISCVCPU *cpu = RISCV_CPU(cs); 843 CPURISCVState *env = &cpu->env; 844 845 switch (riscv_cpu_mxl(env)) { 846 case MXL_RV32: 847 return g_strdup("riscv:rv32"); 848 case MXL_RV64: 849 case MXL_RV128: 850 return g_strdup("riscv:rv64"); 851 default: 852 g_assert_not_reached(); 853 } 854 } 855 856 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 857 { 858 RISCVCPU *cpu = RISCV_CPU(cs); 859 860 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 861 return cpu->dyn_csr_xml; 862 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 863 return cpu->dyn_vreg_xml; 864 } 865 866 return NULL; 867 } 868 869 #ifndef CONFIG_USER_ONLY 870 #include "hw/core/sysemu-cpu-ops.h" 871 872 static const struct SysemuCPUOps riscv_sysemu_ops = { 873 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 874 .write_elf64_note = riscv_cpu_write_elf64_note, 875 .write_elf32_note = riscv_cpu_write_elf32_note, 876 .legacy_vmsd = &vmstate_riscv_cpu, 877 }; 878 #endif 879 880 #include "hw/core/tcg-cpu-ops.h" 881 882 static const struct TCGCPUOps riscv_tcg_ops = { 883 .initialize = riscv_translate_init, 884 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 885 886 #ifndef CONFIG_USER_ONLY 887 .tlb_fill = riscv_cpu_tlb_fill, 888 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 889 .do_interrupt = riscv_cpu_do_interrupt, 890 .do_transaction_failed = riscv_cpu_do_transaction_failed, 891 .do_unaligned_access = riscv_cpu_do_unaligned_access, 892 .debug_excp_handler = riscv_cpu_debug_excp_handler, 893 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 894 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 895 #endif /* !CONFIG_USER_ONLY */ 896 }; 897 898 static void riscv_cpu_class_init(ObjectClass *c, void *data) 899 { 900 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 901 CPUClass *cc = CPU_CLASS(c); 902 DeviceClass *dc = DEVICE_CLASS(c); 903 904 device_class_set_parent_realize(dc, riscv_cpu_realize, 905 &mcc->parent_realize); 906 907 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 908 909 cc->class_by_name = riscv_cpu_class_by_name; 910 cc->has_work = riscv_cpu_has_work; 911 cc->dump_state = riscv_cpu_dump_state; 912 cc->set_pc = riscv_cpu_set_pc; 913 cc->gdb_read_register = riscv_cpu_gdb_read_register; 914 cc->gdb_write_register = riscv_cpu_gdb_write_register; 915 cc->gdb_num_core_regs = 33; 916 cc->gdb_stop_before_watchpoint = true; 917 cc->disas_set_info = riscv_cpu_disas_set_info; 918 #ifndef CONFIG_USER_ONLY 919 cc->sysemu_ops = &riscv_sysemu_ops; 920 #endif 921 cc->gdb_arch_name = riscv_gdb_arch_name; 922 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 923 cc->tcg_ops = &riscv_tcg_ops; 924 925 device_class_set_props(dc, riscv_cpu_properties); 926 } 927 928 #define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop} 929 930 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 931 { 932 char *old = *isa_str; 933 char *new = *isa_str; 934 int i; 935 936 /** 937 * Here are the ordering rules of extension naming defined by RISC-V 938 * specification : 939 * 1. All extensions should be separated from other multi-letter extensions 940 * by an underscore. 941 * 2. The first letter following the 'Z' conventionally indicates the most 942 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 943 * If multiple 'Z' extensions are named, they should be ordered first 944 * by category, then alphabetically within a category. 945 * 3. Standard supervisor-level extensions (starts with 'S') should be 946 * listed after standard unprivileged extensions. If multiple 947 * supervisor-level extensions are listed, they should be ordered 948 * alphabetically. 949 * 4. Non-standard extensions (starts with 'X') must be listed after all 950 * standard extensions. They must be separated from other multi-letter 951 * extensions by an underscore. 952 */ 953 struct isa_ext_data isa_edata_arr[] = { 954 ISA_EDATA_ENTRY(zfh, ext_zfh), 955 ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), 956 ISA_EDATA_ENTRY(zfinx, ext_zfinx), 957 ISA_EDATA_ENTRY(zhinx, ext_zhinx), 958 ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), 959 ISA_EDATA_ENTRY(zdinx, ext_zdinx), 960 ISA_EDATA_ENTRY(zba, ext_zba), 961 ISA_EDATA_ENTRY(zbb, ext_zbb), 962 ISA_EDATA_ENTRY(zbc, ext_zbc), 963 ISA_EDATA_ENTRY(zbs, ext_zbs), 964 ISA_EDATA_ENTRY(zve32f, ext_zve32f), 965 ISA_EDATA_ENTRY(zve64f, ext_zve64f), 966 ISA_EDATA_ENTRY(svinval, ext_svinval), 967 ISA_EDATA_ENTRY(svnapot, ext_svnapot), 968 ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), 969 }; 970 971 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 972 if (isa_edata_arr[i].enabled) { 973 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 974 g_free(old); 975 old = new; 976 } 977 } 978 979 *isa_str = new; 980 } 981 982 char *riscv_isa_string(RISCVCPU *cpu) 983 { 984 int i; 985 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 986 char *isa_str = g_new(char, maxlen); 987 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 988 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 989 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 990 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 991 } 992 } 993 *p = '\0'; 994 riscv_isa_string_ext(cpu, &isa_str, maxlen); 995 return isa_str; 996 } 997 998 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 999 { 1000 ObjectClass *class_a = (ObjectClass *)a; 1001 ObjectClass *class_b = (ObjectClass *)b; 1002 const char *name_a, *name_b; 1003 1004 name_a = object_class_get_name(class_a); 1005 name_b = object_class_get_name(class_b); 1006 return strcmp(name_a, name_b); 1007 } 1008 1009 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1010 { 1011 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1012 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1013 1014 qemu_printf("%.*s\n", len, typename); 1015 } 1016 1017 void riscv_cpu_list(void) 1018 { 1019 GSList *list; 1020 1021 list = object_class_get_list(TYPE_RISCV_CPU, false); 1022 list = g_slist_sort(list, riscv_cpu_list_compare); 1023 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1024 g_slist_free(list); 1025 } 1026 1027 #define DEFINE_CPU(type_name, initfn) \ 1028 { \ 1029 .name = type_name, \ 1030 .parent = TYPE_RISCV_CPU, \ 1031 .instance_init = initfn \ 1032 } 1033 1034 static const TypeInfo riscv_cpu_type_infos[] = { 1035 { 1036 .name = TYPE_RISCV_CPU, 1037 .parent = TYPE_CPU, 1038 .instance_size = sizeof(RISCVCPU), 1039 .instance_align = __alignof__(RISCVCPU), 1040 .instance_init = riscv_cpu_init, 1041 .abstract = true, 1042 .class_size = sizeof(RISCVCPUClass), 1043 .class_init = riscv_cpu_class_init, 1044 }, 1045 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1046 #if defined(CONFIG_KVM) 1047 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1048 #endif 1049 #if defined(TARGET_RISCV32) 1050 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1051 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1052 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1053 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1054 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1055 #elif defined(TARGET_RISCV64) 1056 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1057 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1058 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1059 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1060 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1061 #endif 1062 }; 1063 1064 DEFINE_TYPES(riscv_cpu_type_infos) 1065