1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "qemu/error-report.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "fpu/softfloat-helpers.h" 36 #include "sysemu/kvm.h" 37 #include "kvm_riscv.h" 38 #include "tcg/tcg.h" 39 40 /* RISC-V CPU definitions */ 41 42 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 43 (QEMU_VERSION_MINOR << 8) | \ 44 (QEMU_VERSION_MICRO)) 45 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 46 47 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 48 49 struct isa_ext_data { 50 const char *name; 51 int min_version; 52 int ext_enable_offset; 53 }; 54 55 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ 56 {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 57 58 /* 59 * Here are the ordering rules of extension naming defined by RISC-V 60 * specification : 61 * 1. All extensions should be separated from other multi-letter extensions 62 * by an underscore. 63 * 2. The first letter following the 'Z' conventionally indicates the most 64 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 65 * If multiple 'Z' extensions are named, they should be ordered first 66 * by category, then alphabetically within a category. 67 * 3. Standard supervisor-level extensions (starts with 'S') should be 68 * listed after standard unprivileged extensions. If multiple 69 * supervisor-level extensions are listed, they should be ordered 70 * alphabetically. 71 * 4. Non-standard extensions (starts with 'X') must be listed after all 72 * standard extensions. They must be separated from other multi-letter 73 * extensions by an underscore. 74 * 75 * Single letter extensions are checked in riscv_cpu_validate_misa_priv() 76 * instead. 77 */ 78 static const struct isa_ext_data isa_edata_arr[] = { 79 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), 80 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), 81 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), 82 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), 83 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), 84 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), 85 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), 86 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), 87 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), 88 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), 89 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), 90 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), 91 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), 92 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), 93 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), 94 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), 95 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), 96 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), 97 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), 98 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), 99 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), 100 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), 101 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), 102 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), 103 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), 104 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), 105 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), 106 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), 107 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), 108 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), 109 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), 110 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), 111 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), 112 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), 113 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), 114 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), 115 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), 116 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), 117 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), 118 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), 119 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), 120 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), 121 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), 122 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), 123 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), 124 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), 125 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), 126 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), 127 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), 128 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), 129 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), 130 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), 131 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), 132 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), 133 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 134 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 135 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), 136 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), 137 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 138 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), 139 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), 140 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 141 }; 142 143 static bool isa_ext_is_enabled(RISCVCPU *cpu, 144 const struct isa_ext_data *edata) 145 { 146 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 147 148 return *ext_enabled; 149 } 150 151 static void isa_ext_update_enabled(RISCVCPU *cpu, 152 const struct isa_ext_data *edata, bool en) 153 { 154 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 155 156 *ext_enabled = en; 157 } 158 159 const char * const riscv_int_regnames[] = { 160 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 161 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 162 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 163 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 164 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 165 }; 166 167 const char * const riscv_int_regnamesh[] = { 168 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 169 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 170 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 171 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 172 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 173 "x30h/t5h", "x31h/t6h" 174 }; 175 176 const char * const riscv_fpr_regnames[] = { 177 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 178 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 179 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 180 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 181 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 182 "f30/ft10", "f31/ft11" 183 }; 184 185 static const char * const riscv_excp_names[] = { 186 "misaligned_fetch", 187 "fault_fetch", 188 "illegal_instruction", 189 "breakpoint", 190 "misaligned_load", 191 "fault_load", 192 "misaligned_store", 193 "fault_store", 194 "user_ecall", 195 "supervisor_ecall", 196 "hypervisor_ecall", 197 "machine_ecall", 198 "exec_page_fault", 199 "load_page_fault", 200 "reserved", 201 "store_page_fault", 202 "reserved", 203 "reserved", 204 "reserved", 205 "reserved", 206 "guest_exec_page_fault", 207 "guest_load_page_fault", 208 "reserved", 209 "guest_store_page_fault", 210 }; 211 212 static const char * const riscv_intr_names[] = { 213 "u_software", 214 "s_software", 215 "vs_software", 216 "m_software", 217 "u_timer", 218 "s_timer", 219 "vs_timer", 220 "m_timer", 221 "u_external", 222 "s_external", 223 "vs_external", 224 "m_external", 225 "reserved", 226 "reserved", 227 "reserved", 228 "reserved" 229 }; 230 231 static void riscv_cpu_add_user_properties(Object *obj); 232 233 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 234 { 235 if (async) { 236 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 237 riscv_intr_names[cause] : "(unknown)"; 238 } else { 239 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 240 riscv_excp_names[cause] : "(unknown)"; 241 } 242 } 243 244 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 245 { 246 env->misa_mxl_max = env->misa_mxl = mxl; 247 env->misa_ext_mask = env->misa_ext = ext; 248 } 249 250 static void set_priv_version(CPURISCVState *env, int priv_ver) 251 { 252 env->priv_ver = priv_ver; 253 } 254 255 static void set_vext_version(CPURISCVState *env, int vext_ver) 256 { 257 env->vext_ver = vext_ver; 258 } 259 260 #ifndef CONFIG_USER_ONLY 261 static uint8_t satp_mode_from_str(const char *satp_mode_str) 262 { 263 if (!strncmp(satp_mode_str, "mbare", 5)) { 264 return VM_1_10_MBARE; 265 } 266 267 if (!strncmp(satp_mode_str, "sv32", 4)) { 268 return VM_1_10_SV32; 269 } 270 271 if (!strncmp(satp_mode_str, "sv39", 4)) { 272 return VM_1_10_SV39; 273 } 274 275 if (!strncmp(satp_mode_str, "sv48", 4)) { 276 return VM_1_10_SV48; 277 } 278 279 if (!strncmp(satp_mode_str, "sv57", 4)) { 280 return VM_1_10_SV57; 281 } 282 283 if (!strncmp(satp_mode_str, "sv64", 4)) { 284 return VM_1_10_SV64; 285 } 286 287 g_assert_not_reached(); 288 } 289 290 uint8_t satp_mode_max_from_map(uint32_t map) 291 { 292 /* map here has at least one bit set, so no problem with clz */ 293 return 31 - __builtin_clz(map); 294 } 295 296 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) 297 { 298 if (is_32_bit) { 299 switch (satp_mode) { 300 case VM_1_10_SV32: 301 return "sv32"; 302 case VM_1_10_MBARE: 303 return "none"; 304 } 305 } else { 306 switch (satp_mode) { 307 case VM_1_10_SV64: 308 return "sv64"; 309 case VM_1_10_SV57: 310 return "sv57"; 311 case VM_1_10_SV48: 312 return "sv48"; 313 case VM_1_10_SV39: 314 return "sv39"; 315 case VM_1_10_MBARE: 316 return "none"; 317 } 318 } 319 320 g_assert_not_reached(); 321 } 322 323 static void set_satp_mode_max_supported(RISCVCPU *cpu, 324 uint8_t satp_mode) 325 { 326 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 327 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; 328 329 for (int i = 0; i <= satp_mode; ++i) { 330 if (valid_vm[i]) { 331 cpu->cfg.satp_mode.supported |= (1 << i); 332 } 333 } 334 } 335 336 /* Set the satp mode to the max supported */ 337 static void set_satp_mode_default_map(RISCVCPU *cpu) 338 { 339 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; 340 } 341 #endif 342 343 static void riscv_any_cpu_init(Object *obj) 344 { 345 CPURISCVState *env = &RISCV_CPU(obj)->env; 346 #if defined(TARGET_RISCV32) 347 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 348 #elif defined(TARGET_RISCV64) 349 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 350 #endif 351 352 #ifndef CONFIG_USER_ONLY 353 set_satp_mode_max_supported(RISCV_CPU(obj), 354 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? 355 VM_1_10_SV32 : VM_1_10_SV57); 356 #endif 357 358 set_priv_version(env, PRIV_VERSION_1_12_0); 359 } 360 361 #if defined(TARGET_RISCV64) 362 static void rv64_base_cpu_init(Object *obj) 363 { 364 CPURISCVState *env = &RISCV_CPU(obj)->env; 365 /* We set this in the realise function */ 366 set_misa(env, MXL_RV64, 0); 367 riscv_cpu_add_user_properties(obj); 368 /* Set latest version of privileged specification */ 369 set_priv_version(env, PRIV_VERSION_1_12_0); 370 #ifndef CONFIG_USER_ONLY 371 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 372 #endif 373 } 374 375 static void rv64_sifive_u_cpu_init(Object *obj) 376 { 377 CPURISCVState *env = &RISCV_CPU(obj)->env; 378 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 379 set_priv_version(env, PRIV_VERSION_1_10_0); 380 #ifndef CONFIG_USER_ONLY 381 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); 382 #endif 383 } 384 385 static void rv64_sifive_e_cpu_init(Object *obj) 386 { 387 CPURISCVState *env = &RISCV_CPU(obj)->env; 388 RISCVCPU *cpu = RISCV_CPU(obj); 389 390 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 391 set_priv_version(env, PRIV_VERSION_1_10_0); 392 cpu->cfg.mmu = false; 393 #ifndef CONFIG_USER_ONLY 394 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 395 #endif 396 } 397 398 static void rv64_thead_c906_cpu_init(Object *obj) 399 { 400 CPURISCVState *env = &RISCV_CPU(obj)->env; 401 RISCVCPU *cpu = RISCV_CPU(obj); 402 403 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); 404 set_priv_version(env, PRIV_VERSION_1_11_0); 405 406 cpu->cfg.ext_zfh = true; 407 cpu->cfg.mmu = true; 408 cpu->cfg.ext_xtheadba = true; 409 cpu->cfg.ext_xtheadbb = true; 410 cpu->cfg.ext_xtheadbs = true; 411 cpu->cfg.ext_xtheadcmo = true; 412 cpu->cfg.ext_xtheadcondmov = true; 413 cpu->cfg.ext_xtheadfmemidx = true; 414 cpu->cfg.ext_xtheadmac = true; 415 cpu->cfg.ext_xtheadmemidx = true; 416 cpu->cfg.ext_xtheadmempair = true; 417 cpu->cfg.ext_xtheadsync = true; 418 419 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 420 #ifndef CONFIG_USER_ONLY 421 set_satp_mode_max_supported(cpu, VM_1_10_SV39); 422 #endif 423 } 424 425 static void rv128_base_cpu_init(Object *obj) 426 { 427 if (qemu_tcg_mttcg_enabled()) { 428 /* Missing 128-bit aligned atomics */ 429 error_report("128-bit RISC-V currently does not work with Multi " 430 "Threaded TCG. Please use: -accel tcg,thread=single"); 431 exit(EXIT_FAILURE); 432 } 433 CPURISCVState *env = &RISCV_CPU(obj)->env; 434 /* We set this in the realise function */ 435 set_misa(env, MXL_RV128, 0); 436 riscv_cpu_add_user_properties(obj); 437 /* Set latest version of privileged specification */ 438 set_priv_version(env, PRIV_VERSION_1_12_0); 439 #ifndef CONFIG_USER_ONLY 440 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 441 #endif 442 } 443 #else 444 static void rv32_base_cpu_init(Object *obj) 445 { 446 CPURISCVState *env = &RISCV_CPU(obj)->env; 447 /* We set this in the realise function */ 448 set_misa(env, MXL_RV32, 0); 449 riscv_cpu_add_user_properties(obj); 450 /* Set latest version of privileged specification */ 451 set_priv_version(env, PRIV_VERSION_1_12_0); 452 #ifndef CONFIG_USER_ONLY 453 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 454 #endif 455 } 456 457 static void rv32_sifive_u_cpu_init(Object *obj) 458 { 459 CPURISCVState *env = &RISCV_CPU(obj)->env; 460 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 461 set_priv_version(env, PRIV_VERSION_1_10_0); 462 #ifndef CONFIG_USER_ONLY 463 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 464 #endif 465 } 466 467 static void rv32_sifive_e_cpu_init(Object *obj) 468 { 469 CPURISCVState *env = &RISCV_CPU(obj)->env; 470 RISCVCPU *cpu = RISCV_CPU(obj); 471 472 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 473 set_priv_version(env, PRIV_VERSION_1_10_0); 474 cpu->cfg.mmu = false; 475 #ifndef CONFIG_USER_ONLY 476 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 477 #endif 478 } 479 480 static void rv32_ibex_cpu_init(Object *obj) 481 { 482 CPURISCVState *env = &RISCV_CPU(obj)->env; 483 RISCVCPU *cpu = RISCV_CPU(obj); 484 485 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 486 set_priv_version(env, PRIV_VERSION_1_11_0); 487 cpu->cfg.mmu = false; 488 #ifndef CONFIG_USER_ONLY 489 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 490 #endif 491 cpu->cfg.epmp = true; 492 } 493 494 static void rv32_imafcu_nommu_cpu_init(Object *obj) 495 { 496 CPURISCVState *env = &RISCV_CPU(obj)->env; 497 RISCVCPU *cpu = RISCV_CPU(obj); 498 499 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 500 set_priv_version(env, PRIV_VERSION_1_10_0); 501 cpu->cfg.mmu = false; 502 #ifndef CONFIG_USER_ONLY 503 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 504 #endif 505 } 506 #endif 507 508 #if defined(CONFIG_KVM) 509 static void riscv_host_cpu_init(Object *obj) 510 { 511 CPURISCVState *env = &RISCV_CPU(obj)->env; 512 #if defined(TARGET_RISCV32) 513 set_misa(env, MXL_RV32, 0); 514 #elif defined(TARGET_RISCV64) 515 set_misa(env, MXL_RV64, 0); 516 #endif 517 riscv_cpu_add_user_properties(obj); 518 } 519 #endif 520 521 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 522 { 523 ObjectClass *oc; 524 char *typename; 525 char **cpuname; 526 527 cpuname = g_strsplit(cpu_model, ",", 1); 528 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 529 oc = object_class_by_name(typename); 530 g_strfreev(cpuname); 531 g_free(typename); 532 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 533 object_class_is_abstract(oc)) { 534 return NULL; 535 } 536 return oc; 537 } 538 539 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 540 { 541 RISCVCPU *cpu = RISCV_CPU(cs); 542 CPURISCVState *env = &cpu->env; 543 int i; 544 545 #if !defined(CONFIG_USER_ONLY) 546 if (riscv_has_ext(env, RVH)) { 547 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); 548 } 549 #endif 550 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 551 #ifndef CONFIG_USER_ONLY 552 { 553 static const int dump_csrs[] = { 554 CSR_MHARTID, 555 CSR_MSTATUS, 556 CSR_MSTATUSH, 557 /* 558 * CSR_SSTATUS is intentionally omitted here as its value 559 * can be figured out by looking at CSR_MSTATUS 560 */ 561 CSR_HSTATUS, 562 CSR_VSSTATUS, 563 CSR_MIP, 564 CSR_MIE, 565 CSR_MIDELEG, 566 CSR_HIDELEG, 567 CSR_MEDELEG, 568 CSR_HEDELEG, 569 CSR_MTVEC, 570 CSR_STVEC, 571 CSR_VSTVEC, 572 CSR_MEPC, 573 CSR_SEPC, 574 CSR_VSEPC, 575 CSR_MCAUSE, 576 CSR_SCAUSE, 577 CSR_VSCAUSE, 578 CSR_MTVAL, 579 CSR_STVAL, 580 CSR_HTVAL, 581 CSR_MTVAL2, 582 CSR_MSCRATCH, 583 CSR_SSCRATCH, 584 CSR_SATP, 585 CSR_MMTE, 586 CSR_UPMBASE, 587 CSR_UPMMASK, 588 CSR_SPMBASE, 589 CSR_SPMMASK, 590 CSR_MPMBASE, 591 CSR_MPMMASK, 592 }; 593 594 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 595 int csrno = dump_csrs[i]; 596 target_ulong val = 0; 597 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 598 599 /* 600 * Rely on the smode, hmode, etc, predicates within csr.c 601 * to do the filtering of the registers that are present. 602 */ 603 if (res == RISCV_EXCP_NONE) { 604 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 605 csr_ops[csrno].name, val); 606 } 607 } 608 } 609 #endif 610 611 for (i = 0; i < 32; i++) { 612 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 613 riscv_int_regnames[i], env->gpr[i]); 614 if ((i & 3) == 3) { 615 qemu_fprintf(f, "\n"); 616 } 617 } 618 if (flags & CPU_DUMP_FPU) { 619 for (i = 0; i < 32; i++) { 620 qemu_fprintf(f, " %-8s %016" PRIx64, 621 riscv_fpr_regnames[i], env->fpr[i]); 622 if ((i & 3) == 3) { 623 qemu_fprintf(f, "\n"); 624 } 625 } 626 } 627 } 628 629 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 630 { 631 RISCVCPU *cpu = RISCV_CPU(cs); 632 CPURISCVState *env = &cpu->env; 633 634 if (env->xl == MXL_RV32) { 635 env->pc = (int32_t)value; 636 } else { 637 env->pc = value; 638 } 639 } 640 641 static vaddr riscv_cpu_get_pc(CPUState *cs) 642 { 643 RISCVCPU *cpu = RISCV_CPU(cs); 644 CPURISCVState *env = &cpu->env; 645 646 /* Match cpu_get_tb_cpu_state. */ 647 if (env->xl == MXL_RV32) { 648 return env->pc & UINT32_MAX; 649 } 650 return env->pc; 651 } 652 653 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 654 const TranslationBlock *tb) 655 { 656 RISCVCPU *cpu = RISCV_CPU(cs); 657 CPURISCVState *env = &cpu->env; 658 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 659 660 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 661 662 if (xl == MXL_RV32) { 663 env->pc = (int32_t) tb->pc; 664 } else { 665 env->pc = tb->pc; 666 } 667 } 668 669 static bool riscv_cpu_has_work(CPUState *cs) 670 { 671 #ifndef CONFIG_USER_ONLY 672 RISCVCPU *cpu = RISCV_CPU(cs); 673 CPURISCVState *env = &cpu->env; 674 /* 675 * Definition of the WFI instruction requires it to ignore the privilege 676 * mode and delegation registers, but respect individual enables 677 */ 678 return riscv_cpu_all_pending(env) != 0; 679 #else 680 return true; 681 #endif 682 } 683 684 static void riscv_restore_state_to_opc(CPUState *cs, 685 const TranslationBlock *tb, 686 const uint64_t *data) 687 { 688 RISCVCPU *cpu = RISCV_CPU(cs); 689 CPURISCVState *env = &cpu->env; 690 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 691 692 if (xl == MXL_RV32) { 693 env->pc = (int32_t)data[0]; 694 } else { 695 env->pc = data[0]; 696 } 697 env->bins = data[1]; 698 } 699 700 static void riscv_cpu_reset_hold(Object *obj) 701 { 702 #ifndef CONFIG_USER_ONLY 703 uint8_t iprio; 704 int i, irq, rdzero; 705 #endif 706 CPUState *cs = CPU(obj); 707 RISCVCPU *cpu = RISCV_CPU(cs); 708 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 709 CPURISCVState *env = &cpu->env; 710 711 if (mcc->parent_phases.hold) { 712 mcc->parent_phases.hold(obj); 713 } 714 #ifndef CONFIG_USER_ONLY 715 env->misa_mxl = env->misa_mxl_max; 716 env->priv = PRV_M; 717 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 718 if (env->misa_mxl > MXL_RV32) { 719 /* 720 * The reset status of SXL/UXL is undefined, but mstatus is WARL 721 * and we must ensure that the value after init is valid for read. 722 */ 723 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 724 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 725 if (riscv_has_ext(env, RVH)) { 726 env->vsstatus = set_field(env->vsstatus, 727 MSTATUS64_SXL, env->misa_mxl); 728 env->vsstatus = set_field(env->vsstatus, 729 MSTATUS64_UXL, env->misa_mxl); 730 env->mstatus_hs = set_field(env->mstatus_hs, 731 MSTATUS64_SXL, env->misa_mxl); 732 env->mstatus_hs = set_field(env->mstatus_hs, 733 MSTATUS64_UXL, env->misa_mxl); 734 } 735 } 736 env->mcause = 0; 737 env->miclaim = MIP_SGEIP; 738 env->pc = env->resetvec; 739 env->bins = 0; 740 env->two_stage_lookup = false; 741 742 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | 743 (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); 744 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | 745 (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); 746 747 /* Initialized default priorities of local interrupts. */ 748 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 749 iprio = riscv_cpu_default_priority(i); 750 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 751 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 752 env->hviprio[i] = 0; 753 } 754 i = 0; 755 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 756 if (!rdzero) { 757 env->hviprio[irq] = env->miprio[irq]; 758 } 759 i++; 760 } 761 /* mmte is supposed to have pm.current hardwired to 1 */ 762 env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); 763 #endif 764 env->xl = riscv_cpu_mxl(env); 765 riscv_cpu_update_mask(env); 766 cs->exception_index = RISCV_EXCP_NONE; 767 env->load_res = -1; 768 set_default_nan_mode(1, &env->fp_status); 769 770 #ifndef CONFIG_USER_ONLY 771 if (cpu->cfg.debug) { 772 riscv_trigger_init(env); 773 } 774 775 if (kvm_enabled()) { 776 kvm_riscv_reset_vcpu(cpu); 777 } 778 #endif 779 } 780 781 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 782 { 783 RISCVCPU *cpu = RISCV_CPU(s); 784 785 switch (riscv_cpu_mxl(&cpu->env)) { 786 case MXL_RV32: 787 info->print_insn = print_insn_riscv32; 788 break; 789 case MXL_RV64: 790 info->print_insn = print_insn_riscv64; 791 break; 792 case MXL_RV128: 793 info->print_insn = print_insn_riscv128; 794 break; 795 default: 796 g_assert_not_reached(); 797 } 798 } 799 800 /* 801 * Check consistency between chosen extensions while setting 802 * cpu->cfg accordingly. 803 */ 804 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 805 { 806 CPURISCVState *env = &cpu->env; 807 808 /* Do some ISA extension error checking */ 809 if (riscv_has_ext(env, RVG) && 810 !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && 811 riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && 812 riscv_has_ext(env, RVD) && 813 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 814 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 815 cpu->cfg.ext_icsr = true; 816 cpu->cfg.ext_ifencei = true; 817 818 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; 819 env->misa_ext_mask = env->misa_ext; 820 } 821 822 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 823 error_setg(errp, 824 "I and E extensions are incompatible"); 825 return; 826 } 827 828 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 829 error_setg(errp, 830 "Either I or E extension must be set"); 831 return; 832 } 833 834 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 835 error_setg(errp, 836 "Setting S extension without U extension is illegal"); 837 return; 838 } 839 840 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 841 error_setg(errp, 842 "H depends on an I base integer ISA with 32 x registers"); 843 return; 844 } 845 846 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 847 error_setg(errp, "H extension implicitly requires S-mode"); 848 return; 849 } 850 851 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { 852 error_setg(errp, "F extension requires Zicsr"); 853 return; 854 } 855 856 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 857 error_setg(errp, "Zawrs extension requires A extension"); 858 return; 859 } 860 861 if (cpu->cfg.ext_zfh) { 862 cpu->cfg.ext_zfhmin = true; 863 } 864 865 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 866 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 867 return; 868 } 869 870 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 871 error_setg(errp, "D extension requires F extension"); 872 return; 873 } 874 875 /* The V vector extension depends on the Zve64d extension */ 876 if (riscv_has_ext(env, RVV)) { 877 cpu->cfg.ext_zve64d = true; 878 } 879 880 /* The Zve64d extension depends on the Zve64f extension */ 881 if (cpu->cfg.ext_zve64d) { 882 cpu->cfg.ext_zve64f = true; 883 } 884 885 /* The Zve64f extension depends on the Zve32f extension */ 886 if (cpu->cfg.ext_zve64f) { 887 cpu->cfg.ext_zve32f = true; 888 } 889 890 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 891 error_setg(errp, "Zve64d/V extensions require D extension"); 892 return; 893 } 894 895 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 896 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 897 return; 898 } 899 900 if (cpu->cfg.ext_zvfh) { 901 cpu->cfg.ext_zvfhmin = true; 902 } 903 904 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 905 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 906 return; 907 } 908 909 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 910 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 911 return; 912 } 913 914 /* Set the ISA extensions, checks should have happened above */ 915 if (cpu->cfg.ext_zhinx) { 916 cpu->cfg.ext_zhinxmin = true; 917 } 918 919 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 920 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 921 return; 922 } 923 924 if (cpu->cfg.ext_zfinx) { 925 if (!cpu->cfg.ext_icsr) { 926 error_setg(errp, "Zfinx extension requires Zicsr"); 927 return; 928 } 929 if (riscv_has_ext(env, RVF)) { 930 error_setg(errp, 931 "Zfinx cannot be supported together with F extension"); 932 return; 933 } 934 } 935 936 if (cpu->cfg.ext_zce) { 937 cpu->cfg.ext_zca = true; 938 cpu->cfg.ext_zcb = true; 939 cpu->cfg.ext_zcmp = true; 940 cpu->cfg.ext_zcmt = true; 941 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 942 cpu->cfg.ext_zcf = true; 943 } 944 } 945 946 if (riscv_has_ext(env, RVC)) { 947 cpu->cfg.ext_zca = true; 948 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 949 cpu->cfg.ext_zcf = true; 950 } 951 if (riscv_has_ext(env, RVD)) { 952 cpu->cfg.ext_zcd = true; 953 } 954 } 955 956 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 957 error_setg(errp, "Zcf extension is only relevant to RV32"); 958 return; 959 } 960 961 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 962 error_setg(errp, "Zcf extension requires F extension"); 963 return; 964 } 965 966 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 967 error_setg(errp, "Zcd extension requires D extension"); 968 return; 969 } 970 971 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 972 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 973 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 974 "extension"); 975 return; 976 } 977 978 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 979 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 980 "Zcd extension"); 981 return; 982 } 983 984 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { 985 error_setg(errp, "Zcmt extension requires Zicsr extension"); 986 return; 987 } 988 989 if (cpu->cfg.ext_zk) { 990 cpu->cfg.ext_zkn = true; 991 cpu->cfg.ext_zkr = true; 992 cpu->cfg.ext_zkt = true; 993 } 994 995 if (cpu->cfg.ext_zkn) { 996 cpu->cfg.ext_zbkb = true; 997 cpu->cfg.ext_zbkc = true; 998 cpu->cfg.ext_zbkx = true; 999 cpu->cfg.ext_zkne = true; 1000 cpu->cfg.ext_zknd = true; 1001 cpu->cfg.ext_zknh = true; 1002 } 1003 1004 if (cpu->cfg.ext_zks) { 1005 cpu->cfg.ext_zbkb = true; 1006 cpu->cfg.ext_zbkc = true; 1007 cpu->cfg.ext_zbkx = true; 1008 cpu->cfg.ext_zksed = true; 1009 cpu->cfg.ext_zksh = true; 1010 } 1011 1012 if (riscv_has_ext(env, RVV)) { 1013 int vext_version = VEXT_VERSION_1_00_0; 1014 if (!is_power_of_2(cpu->cfg.vlen)) { 1015 error_setg(errp, 1016 "Vector extension VLEN must be power of 2"); 1017 return; 1018 } 1019 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 1020 error_setg(errp, 1021 "Vector extension implementation only supports VLEN " 1022 "in the range [128, %d]", RV_VLEN_MAX); 1023 return; 1024 } 1025 if (!is_power_of_2(cpu->cfg.elen)) { 1026 error_setg(errp, 1027 "Vector extension ELEN must be power of 2"); 1028 return; 1029 } 1030 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 1031 error_setg(errp, 1032 "Vector extension implementation only supports ELEN " 1033 "in the range [8, 64]"); 1034 return; 1035 } 1036 if (cpu->cfg.vext_spec) { 1037 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 1038 vext_version = VEXT_VERSION_1_00_0; 1039 } else { 1040 error_setg(errp, 1041 "Unsupported vector spec version '%s'", 1042 cpu->cfg.vext_spec); 1043 return; 1044 } 1045 } else { 1046 qemu_log("vector version is not specified, " 1047 "use the default value v1.0\n"); 1048 } 1049 set_vext_version(env, vext_version); 1050 } 1051 } 1052 1053 #ifndef CONFIG_USER_ONLY 1054 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) 1055 { 1056 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 1057 uint8_t satp_mode_map_max; 1058 uint8_t satp_mode_supported_max = 1059 satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 1060 1061 if (cpu->cfg.satp_mode.map == 0) { 1062 if (cpu->cfg.satp_mode.init == 0) { 1063 /* If unset by the user, we fallback to the default satp mode. */ 1064 set_satp_mode_default_map(cpu); 1065 } else { 1066 /* 1067 * Find the lowest level that was disabled and then enable the 1068 * first valid level below which can be found in 1069 * valid_vm_1_10_32/64. 1070 */ 1071 for (int i = 1; i < 16; ++i) { 1072 if ((cpu->cfg.satp_mode.init & (1 << i)) && 1073 (cpu->cfg.satp_mode.supported & (1 << i))) { 1074 for (int j = i - 1; j >= 0; --j) { 1075 if (cpu->cfg.satp_mode.supported & (1 << j)) { 1076 cpu->cfg.satp_mode.map |= (1 << j); 1077 break; 1078 } 1079 } 1080 break; 1081 } 1082 } 1083 } 1084 } 1085 1086 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 1087 1088 /* Make sure the user asked for a supported configuration (HW and qemu) */ 1089 if (satp_mode_map_max > satp_mode_supported_max) { 1090 error_setg(errp, "satp_mode %s is higher than hw max capability %s", 1091 satp_mode_str(satp_mode_map_max, rv32), 1092 satp_mode_str(satp_mode_supported_max, rv32)); 1093 return; 1094 } 1095 1096 /* 1097 * Make sure the user did not ask for an invalid configuration as per 1098 * the specification. 1099 */ 1100 if (!rv32) { 1101 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1102 if (!(cpu->cfg.satp_mode.map & (1 << i)) && 1103 (cpu->cfg.satp_mode.init & (1 << i)) && 1104 (cpu->cfg.satp_mode.supported & (1 << i))) { 1105 error_setg(errp, "cannot disable %s satp mode if %s " 1106 "is enabled", satp_mode_str(i, false), 1107 satp_mode_str(satp_mode_map_max, false)); 1108 return; 1109 } 1110 } 1111 } 1112 1113 /* Finally expand the map so that all valid modes are set */ 1114 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1115 if (cpu->cfg.satp_mode.supported & (1 << i)) { 1116 cpu->cfg.satp_mode.map |= (1 << i); 1117 } 1118 } 1119 } 1120 #endif 1121 1122 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1123 { 1124 #ifndef CONFIG_USER_ONLY 1125 Error *local_err = NULL; 1126 1127 riscv_cpu_satp_mode_finalize(cpu, &local_err); 1128 if (local_err != NULL) { 1129 error_propagate(errp, local_err); 1130 return; 1131 } 1132 #endif 1133 } 1134 1135 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 1136 { 1137 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 1138 error_setg(errp, "H extension requires priv spec 1.12.0"); 1139 return; 1140 } 1141 } 1142 1143 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 1144 { 1145 CPUState *cs = CPU(dev); 1146 RISCVCPU *cpu = RISCV_CPU(dev); 1147 CPURISCVState *env = &cpu->env; 1148 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 1149 CPUClass *cc = CPU_CLASS(mcc); 1150 int i, priv_version = -1; 1151 Error *local_err = NULL; 1152 1153 cpu_exec_realizefn(cs, &local_err); 1154 if (local_err != NULL) { 1155 error_propagate(errp, local_err); 1156 return; 1157 } 1158 1159 if (cpu->cfg.priv_spec) { 1160 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 1161 priv_version = PRIV_VERSION_1_12_0; 1162 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 1163 priv_version = PRIV_VERSION_1_11_0; 1164 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 1165 priv_version = PRIV_VERSION_1_10_0; 1166 } else { 1167 error_setg(errp, 1168 "Unsupported privilege spec version '%s'", 1169 cpu->cfg.priv_spec); 1170 return; 1171 } 1172 } 1173 1174 if (priv_version >= PRIV_VERSION_1_10_0) { 1175 set_priv_version(env, priv_version); 1176 } 1177 1178 riscv_cpu_validate_misa_priv(env, &local_err); 1179 if (local_err != NULL) { 1180 error_propagate(errp, local_err); 1181 return; 1182 } 1183 1184 /* Force disable extensions if priv spec version does not match */ 1185 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1186 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 1187 (env->priv_ver < isa_edata_arr[i].min_version)) { 1188 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 1189 #ifndef CONFIG_USER_ONLY 1190 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 1191 " because privilege spec version does not match", 1192 isa_edata_arr[i].name, env->mhartid); 1193 #else 1194 warn_report("disabling %s extension because " 1195 "privilege spec version does not match", 1196 isa_edata_arr[i].name); 1197 #endif 1198 } 1199 } 1200 1201 if (cpu->cfg.epmp && !cpu->cfg.pmp) { 1202 /* 1203 * Enhanced PMP should only be available 1204 * on harts with PMP support 1205 */ 1206 error_setg(errp, "Invalid configuration: EPMP requires PMP support"); 1207 return; 1208 } 1209 1210 1211 #ifndef CONFIG_USER_ONLY 1212 if (cpu->cfg.ext_sstc) { 1213 riscv_timer_init(cpu); 1214 } 1215 #endif /* CONFIG_USER_ONLY */ 1216 1217 /* Validate that MISA_MXL is set properly. */ 1218 switch (env->misa_mxl_max) { 1219 #ifdef TARGET_RISCV64 1220 case MXL_RV64: 1221 case MXL_RV128: 1222 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 1223 break; 1224 #endif 1225 case MXL_RV32: 1226 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 1227 break; 1228 default: 1229 g_assert_not_reached(); 1230 } 1231 assert(env->misa_mxl_max == env->misa_mxl); 1232 1233 riscv_cpu_validate_set_extensions(cpu, &local_err); 1234 if (local_err != NULL) { 1235 error_propagate(errp, local_err); 1236 return; 1237 } 1238 1239 #ifndef CONFIG_USER_ONLY 1240 if (cpu->cfg.pmu_num) { 1241 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 1242 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1243 riscv_pmu_timer_cb, cpu); 1244 } 1245 } 1246 #endif 1247 1248 riscv_cpu_finalize_features(cpu, &local_err); 1249 if (local_err != NULL) { 1250 error_propagate(errp, local_err); 1251 return; 1252 } 1253 1254 riscv_cpu_register_gdb_regs_for_features(cs); 1255 1256 qemu_init_vcpu(cs); 1257 cpu_reset(cs); 1258 1259 mcc->parent_realize(dev, errp); 1260 } 1261 1262 #ifndef CONFIG_USER_ONLY 1263 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, 1264 void *opaque, Error **errp) 1265 { 1266 RISCVSATPMap *satp_map = opaque; 1267 uint8_t satp = satp_mode_from_str(name); 1268 bool value; 1269 1270 value = satp_map->map & (1 << satp); 1271 1272 visit_type_bool(v, name, &value, errp); 1273 } 1274 1275 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, 1276 void *opaque, Error **errp) 1277 { 1278 RISCVSATPMap *satp_map = opaque; 1279 uint8_t satp = satp_mode_from_str(name); 1280 bool value; 1281 1282 if (!visit_type_bool(v, name, &value, errp)) { 1283 return; 1284 } 1285 1286 satp_map->map = deposit32(satp_map->map, satp, 1, value); 1287 satp_map->init |= 1 << satp; 1288 } 1289 1290 static void riscv_add_satp_mode_properties(Object *obj) 1291 { 1292 RISCVCPU *cpu = RISCV_CPU(obj); 1293 1294 if (cpu->env.misa_mxl == MXL_RV32) { 1295 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, 1296 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1297 } else { 1298 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, 1299 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1300 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, 1301 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1302 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, 1303 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1304 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, 1305 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1306 } 1307 } 1308 1309 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1310 { 1311 RISCVCPU *cpu = RISCV_CPU(opaque); 1312 CPURISCVState *env = &cpu->env; 1313 1314 if (irq < IRQ_LOCAL_MAX) { 1315 switch (irq) { 1316 case IRQ_U_SOFT: 1317 case IRQ_S_SOFT: 1318 case IRQ_VS_SOFT: 1319 case IRQ_M_SOFT: 1320 case IRQ_U_TIMER: 1321 case IRQ_S_TIMER: 1322 case IRQ_VS_TIMER: 1323 case IRQ_M_TIMER: 1324 case IRQ_U_EXT: 1325 case IRQ_VS_EXT: 1326 case IRQ_M_EXT: 1327 if (kvm_enabled()) { 1328 kvm_riscv_set_irq(cpu, irq, level); 1329 } else { 1330 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); 1331 } 1332 break; 1333 case IRQ_S_EXT: 1334 if (kvm_enabled()) { 1335 kvm_riscv_set_irq(cpu, irq, level); 1336 } else { 1337 env->external_seip = level; 1338 riscv_cpu_update_mip(env, 1 << irq, 1339 BOOL_TO_MASK(level | env->software_seip)); 1340 } 1341 break; 1342 default: 1343 g_assert_not_reached(); 1344 } 1345 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1346 /* Require H-extension for handling guest local interrupts */ 1347 if (!riscv_has_ext(env, RVH)) { 1348 g_assert_not_reached(); 1349 } 1350 1351 /* Compute bit position in HGEIP CSR */ 1352 irq = irq - IRQ_LOCAL_MAX + 1; 1353 if (env->geilen < irq) { 1354 g_assert_not_reached(); 1355 } 1356 1357 /* Update HGEIP CSR */ 1358 env->hgeip &= ~((target_ulong)1 << irq); 1359 if (level) { 1360 env->hgeip |= (target_ulong)1 << irq; 1361 } 1362 1363 /* Update mip.SGEIP bit */ 1364 riscv_cpu_update_mip(env, MIP_SGEIP, 1365 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1366 } else { 1367 g_assert_not_reached(); 1368 } 1369 } 1370 #endif /* CONFIG_USER_ONLY */ 1371 1372 static void riscv_cpu_init(Object *obj) 1373 { 1374 RISCVCPU *cpu = RISCV_CPU(obj); 1375 1376 cpu->cfg.ext_ifencei = true; 1377 cpu->cfg.ext_icsr = true; 1378 cpu->cfg.mmu = true; 1379 cpu->cfg.pmp = true; 1380 1381 cpu_set_cpustate_pointers(cpu); 1382 1383 #ifndef CONFIG_USER_ONLY 1384 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1385 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1386 #endif /* CONFIG_USER_ONLY */ 1387 } 1388 1389 typedef struct RISCVCPUMisaExtConfig { 1390 const char *name; 1391 const char *description; 1392 target_ulong misa_bit; 1393 bool enabled; 1394 } RISCVCPUMisaExtConfig; 1395 1396 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1397 void *opaque, Error **errp) 1398 { 1399 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1400 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1401 RISCVCPU *cpu = RISCV_CPU(obj); 1402 CPURISCVState *env = &cpu->env; 1403 bool value; 1404 1405 if (!visit_type_bool(v, name, &value, errp)) { 1406 return; 1407 } 1408 1409 if (value) { 1410 env->misa_ext |= misa_bit; 1411 env->misa_ext_mask |= misa_bit; 1412 } else { 1413 env->misa_ext &= ~misa_bit; 1414 env->misa_ext_mask &= ~misa_bit; 1415 } 1416 } 1417 1418 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1419 void *opaque, Error **errp) 1420 { 1421 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1422 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1423 RISCVCPU *cpu = RISCV_CPU(obj); 1424 CPURISCVState *env = &cpu->env; 1425 bool value; 1426 1427 value = env->misa_ext & misa_bit; 1428 1429 visit_type_bool(v, name, &value, errp); 1430 } 1431 1432 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1433 {.name = "a", .description = "Atomic instructions", 1434 .misa_bit = RVA, .enabled = true}, 1435 {.name = "c", .description = "Compressed instructions", 1436 .misa_bit = RVC, .enabled = true}, 1437 {.name = "d", .description = "Double-precision float point", 1438 .misa_bit = RVD, .enabled = true}, 1439 {.name = "f", .description = "Single-precision float point", 1440 .misa_bit = RVF, .enabled = true}, 1441 {.name = "i", .description = "Base integer instruction set", 1442 .misa_bit = RVI, .enabled = true}, 1443 {.name = "e", .description = "Base integer instruction set (embedded)", 1444 .misa_bit = RVE, .enabled = false}, 1445 {.name = "m", .description = "Integer multiplication and division", 1446 .misa_bit = RVM, .enabled = true}, 1447 {.name = "s", .description = "Supervisor-level instructions", 1448 .misa_bit = RVS, .enabled = true}, 1449 {.name = "u", .description = "User-level instructions", 1450 .misa_bit = RVU, .enabled = true}, 1451 {.name = "h", .description = "Hypervisor", 1452 .misa_bit = RVH, .enabled = true}, 1453 {.name = "x-j", .description = "Dynamic translated languages", 1454 .misa_bit = RVJ, .enabled = false}, 1455 {.name = "v", .description = "Vector operations", 1456 .misa_bit = RVV, .enabled = false}, 1457 {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)", 1458 .misa_bit = RVG, .enabled = false}, 1459 }; 1460 1461 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1462 { 1463 int i; 1464 1465 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1466 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1467 1468 object_property_add(cpu_obj, misa_cfg->name, "bool", 1469 cpu_get_misa_ext_cfg, 1470 cpu_set_misa_ext_cfg, 1471 NULL, (void *)misa_cfg); 1472 object_property_set_description(cpu_obj, misa_cfg->name, 1473 misa_cfg->description); 1474 object_property_set_bool(cpu_obj, misa_cfg->name, 1475 misa_cfg->enabled, NULL); 1476 } 1477 } 1478 1479 static Property riscv_cpu_extensions[] = { 1480 /* Defaults for standard extensions */ 1481 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1482 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1483 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1484 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1485 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1486 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1487 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1488 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1489 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1490 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1491 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), 1492 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1493 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1494 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1495 1496 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1497 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1498 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1499 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1500 1501 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), 1502 1503 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1504 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1505 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1506 1507 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1508 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1509 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1510 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1511 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1512 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1513 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1514 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1515 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1516 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1517 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1518 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1519 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1520 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1521 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1522 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1523 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1524 1525 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1526 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1527 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1528 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1529 1530 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), 1531 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), 1532 DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), 1533 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), 1534 1535 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1536 1537 /* Vendor-specific custom extensions */ 1538 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1539 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1540 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1541 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1542 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1543 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1544 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1545 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1546 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1547 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1548 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1549 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1550 1551 /* These are experimental so mark with 'x-' */ 1552 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), 1553 1554 DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), 1555 DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), 1556 DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), 1557 DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), 1558 DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), 1559 DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), 1560 DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), 1561 1562 /* ePMP 0.9.3 */ 1563 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1564 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1565 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1566 1567 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), 1568 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), 1569 1570 DEFINE_PROP_END_OF_LIST(), 1571 }; 1572 1573 /* 1574 * Add CPU properties with user-facing flags. 1575 * 1576 * This will overwrite existing env->misa_ext values with the 1577 * defaults set via riscv_cpu_add_misa_properties(). 1578 */ 1579 static void riscv_cpu_add_user_properties(Object *obj) 1580 { 1581 Property *prop; 1582 DeviceState *dev = DEVICE(obj); 1583 1584 riscv_cpu_add_misa_properties(obj); 1585 1586 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1587 qdev_property_add_static(dev, prop); 1588 } 1589 1590 #ifndef CONFIG_USER_ONLY 1591 riscv_add_satp_mode_properties(obj); 1592 #endif 1593 } 1594 1595 static Property riscv_cpu_properties[] = { 1596 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1597 1598 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1599 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1600 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1601 1602 #ifndef CONFIG_USER_ONLY 1603 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1604 #endif 1605 1606 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1607 1608 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1609 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1610 1611 /* 1612 * write_misa() is marked as experimental for now so mark 1613 * it with -x and default to 'false'. 1614 */ 1615 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1616 DEFINE_PROP_END_OF_LIST(), 1617 }; 1618 1619 static gchar *riscv_gdb_arch_name(CPUState *cs) 1620 { 1621 RISCVCPU *cpu = RISCV_CPU(cs); 1622 CPURISCVState *env = &cpu->env; 1623 1624 switch (riscv_cpu_mxl(env)) { 1625 case MXL_RV32: 1626 return g_strdup("riscv:rv32"); 1627 case MXL_RV64: 1628 case MXL_RV128: 1629 return g_strdup("riscv:rv64"); 1630 default: 1631 g_assert_not_reached(); 1632 } 1633 } 1634 1635 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1636 { 1637 RISCVCPU *cpu = RISCV_CPU(cs); 1638 1639 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1640 return cpu->dyn_csr_xml; 1641 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1642 return cpu->dyn_vreg_xml; 1643 } 1644 1645 return NULL; 1646 } 1647 1648 #ifndef CONFIG_USER_ONLY 1649 static int64_t riscv_get_arch_id(CPUState *cs) 1650 { 1651 RISCVCPU *cpu = RISCV_CPU(cs); 1652 1653 return cpu->env.mhartid; 1654 } 1655 1656 #include "hw/core/sysemu-cpu-ops.h" 1657 1658 static const struct SysemuCPUOps riscv_sysemu_ops = { 1659 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1660 .write_elf64_note = riscv_cpu_write_elf64_note, 1661 .write_elf32_note = riscv_cpu_write_elf32_note, 1662 .legacy_vmsd = &vmstate_riscv_cpu, 1663 }; 1664 #endif 1665 1666 #include "hw/core/tcg-cpu-ops.h" 1667 1668 static const struct TCGCPUOps riscv_tcg_ops = { 1669 .initialize = riscv_translate_init, 1670 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1671 .restore_state_to_opc = riscv_restore_state_to_opc, 1672 1673 #ifndef CONFIG_USER_ONLY 1674 .tlb_fill = riscv_cpu_tlb_fill, 1675 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1676 .do_interrupt = riscv_cpu_do_interrupt, 1677 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1678 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1679 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1680 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1681 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1682 #endif /* !CONFIG_USER_ONLY */ 1683 }; 1684 1685 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1686 { 1687 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1688 CPUClass *cc = CPU_CLASS(c); 1689 DeviceClass *dc = DEVICE_CLASS(c); 1690 ResettableClass *rc = RESETTABLE_CLASS(c); 1691 1692 device_class_set_parent_realize(dc, riscv_cpu_realize, 1693 &mcc->parent_realize); 1694 1695 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1696 &mcc->parent_phases); 1697 1698 cc->class_by_name = riscv_cpu_class_by_name; 1699 cc->has_work = riscv_cpu_has_work; 1700 cc->dump_state = riscv_cpu_dump_state; 1701 cc->set_pc = riscv_cpu_set_pc; 1702 cc->get_pc = riscv_cpu_get_pc; 1703 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1704 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1705 cc->gdb_num_core_regs = 33; 1706 cc->gdb_stop_before_watchpoint = true; 1707 cc->disas_set_info = riscv_cpu_disas_set_info; 1708 #ifndef CONFIG_USER_ONLY 1709 cc->sysemu_ops = &riscv_sysemu_ops; 1710 cc->get_arch_id = riscv_get_arch_id; 1711 #endif 1712 cc->gdb_arch_name = riscv_gdb_arch_name; 1713 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1714 cc->tcg_ops = &riscv_tcg_ops; 1715 1716 device_class_set_props(dc, riscv_cpu_properties); 1717 } 1718 1719 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, 1720 int max_str_len) 1721 { 1722 char *old = *isa_str; 1723 char *new = *isa_str; 1724 int i; 1725 1726 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1727 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1728 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1729 g_free(old); 1730 old = new; 1731 } 1732 } 1733 1734 *isa_str = new; 1735 } 1736 1737 char *riscv_isa_string(RISCVCPU *cpu) 1738 { 1739 int i; 1740 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1741 char *isa_str = g_new(char, maxlen); 1742 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1743 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1744 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1745 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1746 } 1747 } 1748 *p = '\0'; 1749 if (!cpu->cfg.short_isa_string) { 1750 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1751 } 1752 return isa_str; 1753 } 1754 1755 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1756 { 1757 ObjectClass *class_a = (ObjectClass *)a; 1758 ObjectClass *class_b = (ObjectClass *)b; 1759 const char *name_a, *name_b; 1760 1761 name_a = object_class_get_name(class_a); 1762 name_b = object_class_get_name(class_b); 1763 return strcmp(name_a, name_b); 1764 } 1765 1766 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1767 { 1768 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1769 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1770 1771 qemu_printf("%.*s\n", len, typename); 1772 } 1773 1774 void riscv_cpu_list(void) 1775 { 1776 GSList *list; 1777 1778 list = object_class_get_list(TYPE_RISCV_CPU, false); 1779 list = g_slist_sort(list, riscv_cpu_list_compare); 1780 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1781 g_slist_free(list); 1782 } 1783 1784 #define DEFINE_CPU(type_name, initfn) \ 1785 { \ 1786 .name = type_name, \ 1787 .parent = TYPE_RISCV_CPU, \ 1788 .instance_init = initfn \ 1789 } 1790 1791 static const TypeInfo riscv_cpu_type_infos[] = { 1792 { 1793 .name = TYPE_RISCV_CPU, 1794 .parent = TYPE_CPU, 1795 .instance_size = sizeof(RISCVCPU), 1796 .instance_align = __alignof__(RISCVCPU), 1797 .instance_init = riscv_cpu_init, 1798 .abstract = true, 1799 .class_size = sizeof(RISCVCPUClass), 1800 .class_init = riscv_cpu_class_init, 1801 }, 1802 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1803 #if defined(CONFIG_KVM) 1804 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1805 #endif 1806 #if defined(TARGET_RISCV32) 1807 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1808 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1809 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1810 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1811 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1812 #elif defined(TARGET_RISCV64) 1813 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1814 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1815 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1816 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1817 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1818 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1819 #endif 1820 }; 1821 1822 DEFINE_TYPES(riscv_cpu_type_infos) 1823