1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "exec/exec-all.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "fpu/softfloat-helpers.h" 32 #include "sysemu/kvm.h" 33 #include "kvm_riscv.h" 34 35 /* RISC-V CPU definitions */ 36 37 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 38 39 const char * const riscv_int_regnames[] = { 40 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 41 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 42 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 43 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 44 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 45 }; 46 47 const char * const riscv_int_regnamesh[] = { 48 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 49 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 50 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 51 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 52 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 53 "x30h/t5h", "x31h/t6h" 54 }; 55 56 const char * const riscv_fpr_regnames[] = { 57 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 58 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 59 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 60 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 61 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 62 "f30/ft10", "f31/ft11" 63 }; 64 65 static const char * const riscv_excp_names[] = { 66 "misaligned_fetch", 67 "fault_fetch", 68 "illegal_instruction", 69 "breakpoint", 70 "misaligned_load", 71 "fault_load", 72 "misaligned_store", 73 "fault_store", 74 "user_ecall", 75 "supervisor_ecall", 76 "hypervisor_ecall", 77 "machine_ecall", 78 "exec_page_fault", 79 "load_page_fault", 80 "reserved", 81 "store_page_fault", 82 "reserved", 83 "reserved", 84 "reserved", 85 "reserved", 86 "guest_exec_page_fault", 87 "guest_load_page_fault", 88 "reserved", 89 "guest_store_page_fault", 90 }; 91 92 static const char * const riscv_intr_names[] = { 93 "u_software", 94 "s_software", 95 "vs_software", 96 "m_software", 97 "u_timer", 98 "s_timer", 99 "vs_timer", 100 "m_timer", 101 "u_external", 102 "s_external", 103 "vs_external", 104 "m_external", 105 "reserved", 106 "reserved", 107 "reserved", 108 "reserved" 109 }; 110 111 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 112 { 113 if (async) { 114 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 115 riscv_intr_names[cause] : "(unknown)"; 116 } else { 117 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 118 riscv_excp_names[cause] : "(unknown)"; 119 } 120 } 121 122 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 123 { 124 env->misa_mxl_max = env->misa_mxl = mxl; 125 env->misa_ext_mask = env->misa_ext = ext; 126 } 127 128 static void set_priv_version(CPURISCVState *env, int priv_ver) 129 { 130 env->priv_ver = priv_ver; 131 } 132 133 static void set_vext_version(CPURISCVState *env, int vext_ver) 134 { 135 env->vext_ver = vext_ver; 136 } 137 138 static void set_feature(CPURISCVState *env, int feature) 139 { 140 env->features |= (1ULL << feature); 141 } 142 143 static void set_resetvec(CPURISCVState *env, target_ulong resetvec) 144 { 145 #ifndef CONFIG_USER_ONLY 146 env->resetvec = resetvec; 147 #endif 148 } 149 150 static void riscv_any_cpu_init(Object *obj) 151 { 152 CPURISCVState *env = &RISCV_CPU(obj)->env; 153 #if defined(TARGET_RISCV32) 154 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 155 #elif defined(TARGET_RISCV64) 156 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 157 #endif 158 set_priv_version(env, PRIV_VERSION_1_11_0); 159 } 160 161 #if defined(TARGET_RISCV64) 162 static void rv64_base_cpu_init(Object *obj) 163 { 164 CPURISCVState *env = &RISCV_CPU(obj)->env; 165 /* We set this in the realise function */ 166 set_misa(env, MXL_RV64, 0); 167 } 168 169 static void rv64_sifive_u_cpu_init(Object *obj) 170 { 171 CPURISCVState *env = &RISCV_CPU(obj)->env; 172 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 173 set_priv_version(env, PRIV_VERSION_1_10_0); 174 } 175 176 static void rv64_sifive_e_cpu_init(Object *obj) 177 { 178 CPURISCVState *env = &RISCV_CPU(obj)->env; 179 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 180 set_priv_version(env, PRIV_VERSION_1_10_0); 181 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 182 } 183 184 static void rv128_base_cpu_init(Object *obj) 185 { 186 if (qemu_tcg_mttcg_enabled()) { 187 /* Missing 128-bit aligned atomics */ 188 error_report("128-bit RISC-V currently does not work with Multi " 189 "Threaded TCG. Please use: -accel tcg,thread=single"); 190 exit(EXIT_FAILURE); 191 } 192 CPURISCVState *env = &RISCV_CPU(obj)->env; 193 /* We set this in the realise function */ 194 set_misa(env, MXL_RV128, 0); 195 } 196 #else 197 static void rv32_base_cpu_init(Object *obj) 198 { 199 CPURISCVState *env = &RISCV_CPU(obj)->env; 200 /* We set this in the realise function */ 201 set_misa(env, MXL_RV32, 0); 202 } 203 204 static void rv32_sifive_u_cpu_init(Object *obj) 205 { 206 CPURISCVState *env = &RISCV_CPU(obj)->env; 207 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 208 set_priv_version(env, PRIV_VERSION_1_10_0); 209 } 210 211 static void rv32_sifive_e_cpu_init(Object *obj) 212 { 213 CPURISCVState *env = &RISCV_CPU(obj)->env; 214 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 215 set_priv_version(env, PRIV_VERSION_1_10_0); 216 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 217 } 218 219 static void rv32_ibex_cpu_init(Object *obj) 220 { 221 CPURISCVState *env = &RISCV_CPU(obj)->env; 222 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 223 set_priv_version(env, PRIV_VERSION_1_10_0); 224 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 225 qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); 226 } 227 228 static void rv32_imafcu_nommu_cpu_init(Object *obj) 229 { 230 CPURISCVState *env = &RISCV_CPU(obj)->env; 231 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 232 set_priv_version(env, PRIV_VERSION_1_10_0); 233 set_resetvec(env, DEFAULT_RSTVEC); 234 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 235 } 236 #endif 237 238 #if defined(CONFIG_KVM) 239 static void riscv_host_cpu_init(Object *obj) 240 { 241 CPURISCVState *env = &RISCV_CPU(obj)->env; 242 #if defined(TARGET_RISCV32) 243 set_misa(env, MXL_RV32, 0); 244 #elif defined(TARGET_RISCV64) 245 set_misa(env, MXL_RV64, 0); 246 #endif 247 } 248 #endif 249 250 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 251 { 252 ObjectClass *oc; 253 char *typename; 254 char **cpuname; 255 256 cpuname = g_strsplit(cpu_model, ",", 1); 257 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 258 oc = object_class_by_name(typename); 259 g_strfreev(cpuname); 260 g_free(typename); 261 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 262 object_class_is_abstract(oc)) { 263 return NULL; 264 } 265 return oc; 266 } 267 268 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 269 { 270 RISCVCPU *cpu = RISCV_CPU(cs); 271 CPURISCVState *env = &cpu->env; 272 int i; 273 274 #if !defined(CONFIG_USER_ONLY) 275 if (riscv_has_ext(env, RVH)) { 276 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 277 } 278 #endif 279 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 280 #ifndef CONFIG_USER_ONLY 281 { 282 static const int dump_csrs[] = { 283 CSR_MHARTID, 284 CSR_MSTATUS, 285 CSR_MSTATUSH, 286 CSR_HSTATUS, 287 CSR_VSSTATUS, 288 CSR_MIP, 289 CSR_MIE, 290 CSR_MIDELEG, 291 CSR_HIDELEG, 292 CSR_MEDELEG, 293 CSR_HEDELEG, 294 CSR_MTVEC, 295 CSR_STVEC, 296 CSR_VSTVEC, 297 CSR_MEPC, 298 CSR_SEPC, 299 CSR_VSEPC, 300 CSR_MCAUSE, 301 CSR_SCAUSE, 302 CSR_VSCAUSE, 303 CSR_MTVAL, 304 CSR_STVAL, 305 CSR_HTVAL, 306 CSR_MTVAL2, 307 CSR_MSCRATCH, 308 CSR_SSCRATCH, 309 CSR_SATP, 310 CSR_MMTE, 311 CSR_UPMBASE, 312 CSR_UPMMASK, 313 CSR_SPMBASE, 314 CSR_SPMMASK, 315 CSR_MPMBASE, 316 CSR_MPMMASK, 317 }; 318 319 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 320 int csrno = dump_csrs[i]; 321 target_ulong val = 0; 322 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 323 324 /* 325 * Rely on the smode, hmode, etc, predicates within csr.c 326 * to do the filtering of the registers that are present. 327 */ 328 if (res == RISCV_EXCP_NONE) { 329 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 330 csr_ops[csrno].name, val); 331 } 332 } 333 } 334 #endif 335 336 for (i = 0; i < 32; i++) { 337 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 338 riscv_int_regnames[i], env->gpr[i]); 339 if ((i & 3) == 3) { 340 qemu_fprintf(f, "\n"); 341 } 342 } 343 if (flags & CPU_DUMP_FPU) { 344 for (i = 0; i < 32; i++) { 345 qemu_fprintf(f, " %-8s %016" PRIx64, 346 riscv_fpr_regnames[i], env->fpr[i]); 347 if ((i & 3) == 3) { 348 qemu_fprintf(f, "\n"); 349 } 350 } 351 } 352 } 353 354 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 355 { 356 RISCVCPU *cpu = RISCV_CPU(cs); 357 CPURISCVState *env = &cpu->env; 358 env->pc = value; 359 } 360 361 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 362 const TranslationBlock *tb) 363 { 364 RISCVCPU *cpu = RISCV_CPU(cs); 365 CPURISCVState *env = &cpu->env; 366 env->pc = tb->pc; 367 } 368 369 static bool riscv_cpu_has_work(CPUState *cs) 370 { 371 #ifndef CONFIG_USER_ONLY 372 RISCVCPU *cpu = RISCV_CPU(cs); 373 CPURISCVState *env = &cpu->env; 374 /* 375 * Definition of the WFI instruction requires it to ignore the privilege 376 * mode and delegation registers, but respect individual enables 377 */ 378 return (env->mip & env->mie) != 0; 379 #else 380 return true; 381 #endif 382 } 383 384 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 385 target_ulong *data) 386 { 387 env->pc = data[0]; 388 } 389 390 static void riscv_cpu_reset(DeviceState *dev) 391 { 392 CPUState *cs = CPU(dev); 393 RISCVCPU *cpu = RISCV_CPU(cs); 394 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 395 CPURISCVState *env = &cpu->env; 396 397 mcc->parent_reset(dev); 398 #ifndef CONFIG_USER_ONLY 399 env->misa_mxl = env->misa_mxl_max; 400 env->priv = PRV_M; 401 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 402 if (env->misa_mxl > MXL_RV32) { 403 /* 404 * The reset status of SXL/UXL is undefined, but mstatus is WARL 405 * and we must ensure that the value after init is valid for read. 406 */ 407 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 408 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 409 } 410 env->mcause = 0; 411 env->pc = env->resetvec; 412 env->two_stage_lookup = false; 413 /* mmte is supposed to have pm.current hardwired to 1 */ 414 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 415 #endif 416 cs->exception_index = RISCV_EXCP_NONE; 417 env->load_res = -1; 418 set_default_nan_mode(1, &env->fp_status); 419 420 #ifndef CONFIG_USER_ONLY 421 if (kvm_enabled()) { 422 kvm_riscv_reset_vcpu(cpu); 423 } 424 #endif 425 } 426 427 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 428 { 429 RISCVCPU *cpu = RISCV_CPU(s); 430 431 switch (riscv_cpu_mxl(&cpu->env)) { 432 case MXL_RV32: 433 info->print_insn = print_insn_riscv32; 434 break; 435 case MXL_RV64: 436 info->print_insn = print_insn_riscv64; 437 break; 438 case MXL_RV128: 439 info->print_insn = print_insn_riscv128; 440 break; 441 default: 442 g_assert_not_reached(); 443 } 444 } 445 446 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 447 { 448 CPUState *cs = CPU(dev); 449 RISCVCPU *cpu = RISCV_CPU(dev); 450 CPURISCVState *env = &cpu->env; 451 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 452 int priv_version = 0; 453 Error *local_err = NULL; 454 455 cpu_exec_realizefn(cs, &local_err); 456 if (local_err != NULL) { 457 error_propagate(errp, local_err); 458 return; 459 } 460 461 if (cpu->cfg.priv_spec) { 462 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 463 priv_version = PRIV_VERSION_1_11_0; 464 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 465 priv_version = PRIV_VERSION_1_10_0; 466 } else { 467 error_setg(errp, 468 "Unsupported privilege spec version '%s'", 469 cpu->cfg.priv_spec); 470 return; 471 } 472 } 473 474 if (priv_version) { 475 set_priv_version(env, priv_version); 476 } else if (!env->priv_ver) { 477 set_priv_version(env, PRIV_VERSION_1_11_0); 478 } 479 480 if (cpu->cfg.mmu) { 481 set_feature(env, RISCV_FEATURE_MMU); 482 } 483 484 if (cpu->cfg.pmp) { 485 set_feature(env, RISCV_FEATURE_PMP); 486 487 /* 488 * Enhanced PMP should only be available 489 * on harts with PMP support 490 */ 491 if (cpu->cfg.epmp) { 492 set_feature(env, RISCV_FEATURE_EPMP); 493 } 494 } 495 496 set_resetvec(env, cpu->cfg.resetvec); 497 498 /* Validate that MISA_MXL is set properly. */ 499 switch (env->misa_mxl_max) { 500 #ifdef TARGET_RISCV64 501 case MXL_RV64: 502 break; 503 case MXL_RV128: 504 break; 505 #endif 506 case MXL_RV32: 507 break; 508 default: 509 g_assert_not_reached(); 510 } 511 assert(env->misa_mxl_max == env->misa_mxl); 512 513 /* If only MISA_EXT is unset for misa, then set it from properties */ 514 if (env->misa_ext == 0) { 515 uint32_t ext = 0; 516 517 /* Do some ISA extension error checking */ 518 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 519 error_setg(errp, 520 "I and E extensions are incompatible"); 521 return; 522 } 523 524 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 525 error_setg(errp, 526 "Either I or E extension must be set"); 527 return; 528 } 529 530 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 531 cpu->cfg.ext_a & cpu->cfg.ext_f & 532 cpu->cfg.ext_d)) { 533 warn_report("Setting G will also set IMAFD"); 534 cpu->cfg.ext_i = true; 535 cpu->cfg.ext_m = true; 536 cpu->cfg.ext_a = true; 537 cpu->cfg.ext_f = true; 538 cpu->cfg.ext_d = true; 539 } 540 541 /* Set the ISA extensions, checks should have happened above */ 542 if (cpu->cfg.ext_i) { 543 ext |= RVI; 544 } 545 if (cpu->cfg.ext_e) { 546 ext |= RVE; 547 } 548 if (cpu->cfg.ext_m) { 549 ext |= RVM; 550 } 551 if (cpu->cfg.ext_a) { 552 ext |= RVA; 553 } 554 if (cpu->cfg.ext_f) { 555 ext |= RVF; 556 } 557 if (cpu->cfg.ext_d) { 558 ext |= RVD; 559 } 560 if (cpu->cfg.ext_c) { 561 ext |= RVC; 562 } 563 if (cpu->cfg.ext_s) { 564 ext |= RVS; 565 } 566 if (cpu->cfg.ext_u) { 567 ext |= RVU; 568 } 569 if (cpu->cfg.ext_h) { 570 ext |= RVH; 571 } 572 if (cpu->cfg.ext_v) { 573 int vext_version = VEXT_VERSION_1_00_0; 574 ext |= RVV; 575 if (!is_power_of_2(cpu->cfg.vlen)) { 576 error_setg(errp, 577 "Vector extension VLEN must be power of 2"); 578 return; 579 } 580 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 581 error_setg(errp, 582 "Vector extension implementation only supports VLEN " 583 "in the range [128, %d]", RV_VLEN_MAX); 584 return; 585 } 586 if (!is_power_of_2(cpu->cfg.elen)) { 587 error_setg(errp, 588 "Vector extension ELEN must be power of 2"); 589 return; 590 } 591 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 592 error_setg(errp, 593 "Vector extension implementation only supports ELEN " 594 "in the range [8, 64]"); 595 return; 596 } 597 if (cpu->cfg.vext_spec) { 598 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 599 vext_version = VEXT_VERSION_1_00_0; 600 } else { 601 error_setg(errp, 602 "Unsupported vector spec version '%s'", 603 cpu->cfg.vext_spec); 604 return; 605 } 606 } else { 607 qemu_log("vector version is not specified, " 608 "use the default value v1.0\n"); 609 } 610 set_vext_version(env, vext_version); 611 } 612 if (cpu->cfg.ext_zve64f && !cpu->cfg.ext_f) { 613 error_setg(errp, "Zve64f extension depends upon RVF."); 614 return; 615 } 616 if (cpu->cfg.ext_j) { 617 ext |= RVJ; 618 } 619 620 set_misa(env, env->misa_mxl, ext); 621 } 622 623 riscv_cpu_register_gdb_regs_for_features(cs); 624 625 qemu_init_vcpu(cs); 626 cpu_reset(cs); 627 628 mcc->parent_realize(dev, errp); 629 } 630 631 #ifndef CONFIG_USER_ONLY 632 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 633 { 634 RISCVCPU *cpu = RISCV_CPU(opaque); 635 636 switch (irq) { 637 case IRQ_U_SOFT: 638 case IRQ_S_SOFT: 639 case IRQ_VS_SOFT: 640 case IRQ_M_SOFT: 641 case IRQ_U_TIMER: 642 case IRQ_S_TIMER: 643 case IRQ_VS_TIMER: 644 case IRQ_M_TIMER: 645 case IRQ_U_EXT: 646 case IRQ_S_EXT: 647 case IRQ_VS_EXT: 648 case IRQ_M_EXT: 649 if (kvm_enabled()) { 650 kvm_riscv_set_irq(cpu, irq, level); 651 } else { 652 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 653 } 654 break; 655 default: 656 g_assert_not_reached(); 657 } 658 } 659 #endif /* CONFIG_USER_ONLY */ 660 661 static void riscv_cpu_init(Object *obj) 662 { 663 RISCVCPU *cpu = RISCV_CPU(obj); 664 665 cpu_set_cpustate_pointers(cpu); 666 667 #ifndef CONFIG_USER_ONLY 668 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); 669 #endif /* CONFIG_USER_ONLY */ 670 } 671 672 static Property riscv_cpu_properties[] = { 673 /* Defaults for standard extensions */ 674 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 675 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 676 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 677 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 678 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 679 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 680 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 681 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 682 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 683 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 684 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 685 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 686 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 687 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 688 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 689 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 690 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 691 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 692 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 693 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 694 695 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 696 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 697 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 698 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 699 700 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 701 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 702 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 703 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 704 705 /* These are experimental so mark with 'x-' */ 706 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 707 /* ePMP 0.9.3 */ 708 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 709 710 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 711 DEFINE_PROP_END_OF_LIST(), 712 }; 713 714 static gchar *riscv_gdb_arch_name(CPUState *cs) 715 { 716 RISCVCPU *cpu = RISCV_CPU(cs); 717 CPURISCVState *env = &cpu->env; 718 719 switch (riscv_cpu_mxl(env)) { 720 case MXL_RV32: 721 return g_strdup("riscv:rv32"); 722 case MXL_RV64: 723 case MXL_RV128: 724 return g_strdup("riscv:rv64"); 725 default: 726 g_assert_not_reached(); 727 } 728 } 729 730 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 731 { 732 RISCVCPU *cpu = RISCV_CPU(cs); 733 734 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 735 return cpu->dyn_csr_xml; 736 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 737 return cpu->dyn_vreg_xml; 738 } 739 740 return NULL; 741 } 742 743 #ifndef CONFIG_USER_ONLY 744 #include "hw/core/sysemu-cpu-ops.h" 745 746 static const struct SysemuCPUOps riscv_sysemu_ops = { 747 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 748 .write_elf64_note = riscv_cpu_write_elf64_note, 749 .write_elf32_note = riscv_cpu_write_elf32_note, 750 .legacy_vmsd = &vmstate_riscv_cpu, 751 }; 752 #endif 753 754 #include "hw/core/tcg-cpu-ops.h" 755 756 static const struct TCGCPUOps riscv_tcg_ops = { 757 .initialize = riscv_translate_init, 758 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 759 760 #ifndef CONFIG_USER_ONLY 761 .tlb_fill = riscv_cpu_tlb_fill, 762 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 763 .do_interrupt = riscv_cpu_do_interrupt, 764 .do_transaction_failed = riscv_cpu_do_transaction_failed, 765 .do_unaligned_access = riscv_cpu_do_unaligned_access, 766 #endif /* !CONFIG_USER_ONLY */ 767 }; 768 769 static void riscv_cpu_class_init(ObjectClass *c, void *data) 770 { 771 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 772 CPUClass *cc = CPU_CLASS(c); 773 DeviceClass *dc = DEVICE_CLASS(c); 774 775 device_class_set_parent_realize(dc, riscv_cpu_realize, 776 &mcc->parent_realize); 777 778 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 779 780 cc->class_by_name = riscv_cpu_class_by_name; 781 cc->has_work = riscv_cpu_has_work; 782 cc->dump_state = riscv_cpu_dump_state; 783 cc->set_pc = riscv_cpu_set_pc; 784 cc->gdb_read_register = riscv_cpu_gdb_read_register; 785 cc->gdb_write_register = riscv_cpu_gdb_write_register; 786 cc->gdb_num_core_regs = 33; 787 #if defined(TARGET_RISCV32) 788 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 789 #elif defined(TARGET_RISCV64) 790 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 791 #endif 792 cc->gdb_stop_before_watchpoint = true; 793 cc->disas_set_info = riscv_cpu_disas_set_info; 794 #ifndef CONFIG_USER_ONLY 795 cc->sysemu_ops = &riscv_sysemu_ops; 796 #endif 797 cc->gdb_arch_name = riscv_gdb_arch_name; 798 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 799 cc->tcg_ops = &riscv_tcg_ops; 800 801 device_class_set_props(dc, riscv_cpu_properties); 802 } 803 804 char *riscv_isa_string(RISCVCPU *cpu) 805 { 806 int i; 807 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 808 char *isa_str = g_new(char, maxlen); 809 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 810 for (i = 0; i < sizeof(riscv_exts); i++) { 811 if (cpu->env.misa_ext & RV(riscv_exts[i])) { 812 *p++ = qemu_tolower(riscv_exts[i]); 813 } 814 } 815 *p = '\0'; 816 return isa_str; 817 } 818 819 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 820 { 821 ObjectClass *class_a = (ObjectClass *)a; 822 ObjectClass *class_b = (ObjectClass *)b; 823 const char *name_a, *name_b; 824 825 name_a = object_class_get_name(class_a); 826 name_b = object_class_get_name(class_b); 827 return strcmp(name_a, name_b); 828 } 829 830 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 831 { 832 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 833 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 834 835 qemu_printf("%.*s\n", len, typename); 836 } 837 838 void riscv_cpu_list(void) 839 { 840 GSList *list; 841 842 list = object_class_get_list(TYPE_RISCV_CPU, false); 843 list = g_slist_sort(list, riscv_cpu_list_compare); 844 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 845 g_slist_free(list); 846 } 847 848 #define DEFINE_CPU(type_name, initfn) \ 849 { \ 850 .name = type_name, \ 851 .parent = TYPE_RISCV_CPU, \ 852 .instance_init = initfn \ 853 } 854 855 static const TypeInfo riscv_cpu_type_infos[] = { 856 { 857 .name = TYPE_RISCV_CPU, 858 .parent = TYPE_CPU, 859 .instance_size = sizeof(RISCVCPU), 860 .instance_align = __alignof__(RISCVCPU), 861 .instance_init = riscv_cpu_init, 862 .abstract = true, 863 .class_size = sizeof(RISCVCPUClass), 864 .class_init = riscv_cpu_class_init, 865 }, 866 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 867 #if defined(CONFIG_KVM) 868 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 869 #endif 870 #if defined(TARGET_RISCV32) 871 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 872 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 873 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 874 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 875 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 876 #elif defined(TARGET_RISCV64) 877 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 878 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 879 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 880 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 881 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 882 #endif 883 }; 884 885 DEFINE_TYPES(riscv_cpu_type_infos) 886