1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "exec/exec-all.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "fpu/softfloat-helpers.h" 32 #include "sysemu/kvm.h" 33 #include "kvm_riscv.h" 34 35 /* RISC-V CPU definitions */ 36 37 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 38 (QEMU_VERSION_MINOR << 8) | \ 39 (QEMU_VERSION_MICRO)) 40 #define RISCV_CPU_MIPID RISCV_CPU_MARCHID 41 42 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 43 44 struct isa_ext_data { 45 const char *name; 46 bool enabled; 47 }; 48 49 const char * const riscv_int_regnames[] = { 50 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 51 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 52 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 53 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 54 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 55 }; 56 57 const char * const riscv_int_regnamesh[] = { 58 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 59 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 60 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 61 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 62 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 63 "x30h/t5h", "x31h/t6h" 64 }; 65 66 const char * const riscv_fpr_regnames[] = { 67 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 68 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 69 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 70 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 71 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 72 "f30/ft10", "f31/ft11" 73 }; 74 75 static const char * const riscv_excp_names[] = { 76 "misaligned_fetch", 77 "fault_fetch", 78 "illegal_instruction", 79 "breakpoint", 80 "misaligned_load", 81 "fault_load", 82 "misaligned_store", 83 "fault_store", 84 "user_ecall", 85 "supervisor_ecall", 86 "hypervisor_ecall", 87 "machine_ecall", 88 "exec_page_fault", 89 "load_page_fault", 90 "reserved", 91 "store_page_fault", 92 "reserved", 93 "reserved", 94 "reserved", 95 "reserved", 96 "guest_exec_page_fault", 97 "guest_load_page_fault", 98 "reserved", 99 "guest_store_page_fault", 100 }; 101 102 static const char * const riscv_intr_names[] = { 103 "u_software", 104 "s_software", 105 "vs_software", 106 "m_software", 107 "u_timer", 108 "s_timer", 109 "vs_timer", 110 "m_timer", 111 "u_external", 112 "s_external", 113 "vs_external", 114 "m_external", 115 "reserved", 116 "reserved", 117 "reserved", 118 "reserved" 119 }; 120 121 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 122 { 123 if (async) { 124 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 125 riscv_intr_names[cause] : "(unknown)"; 126 } else { 127 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 128 riscv_excp_names[cause] : "(unknown)"; 129 } 130 } 131 132 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 133 { 134 env->misa_mxl_max = env->misa_mxl = mxl; 135 env->misa_ext_mask = env->misa_ext = ext; 136 } 137 138 static void set_priv_version(CPURISCVState *env, int priv_ver) 139 { 140 env->priv_ver = priv_ver; 141 } 142 143 static void set_vext_version(CPURISCVState *env, int vext_ver) 144 { 145 env->vext_ver = vext_ver; 146 } 147 148 static void set_resetvec(CPURISCVState *env, target_ulong resetvec) 149 { 150 #ifndef CONFIG_USER_ONLY 151 env->resetvec = resetvec; 152 #endif 153 } 154 155 static void riscv_any_cpu_init(Object *obj) 156 { 157 CPURISCVState *env = &RISCV_CPU(obj)->env; 158 #if defined(TARGET_RISCV32) 159 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 160 #elif defined(TARGET_RISCV64) 161 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 162 #endif 163 set_priv_version(env, PRIV_VERSION_1_12_0); 164 } 165 166 #if defined(TARGET_RISCV64) 167 static void rv64_base_cpu_init(Object *obj) 168 { 169 CPURISCVState *env = &RISCV_CPU(obj)->env; 170 /* We set this in the realise function */ 171 set_misa(env, MXL_RV64, 0); 172 } 173 174 static void rv64_sifive_u_cpu_init(Object *obj) 175 { 176 CPURISCVState *env = &RISCV_CPU(obj)->env; 177 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 178 set_priv_version(env, PRIV_VERSION_1_10_0); 179 } 180 181 static void rv64_sifive_e_cpu_init(Object *obj) 182 { 183 CPURISCVState *env = &RISCV_CPU(obj)->env; 184 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 185 set_priv_version(env, PRIV_VERSION_1_10_0); 186 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 187 } 188 189 static void rv128_base_cpu_init(Object *obj) 190 { 191 if (qemu_tcg_mttcg_enabled()) { 192 /* Missing 128-bit aligned atomics */ 193 error_report("128-bit RISC-V currently does not work with Multi " 194 "Threaded TCG. Please use: -accel tcg,thread=single"); 195 exit(EXIT_FAILURE); 196 } 197 CPURISCVState *env = &RISCV_CPU(obj)->env; 198 /* We set this in the realise function */ 199 set_misa(env, MXL_RV128, 0); 200 } 201 #else 202 static void rv32_base_cpu_init(Object *obj) 203 { 204 CPURISCVState *env = &RISCV_CPU(obj)->env; 205 /* We set this in the realise function */ 206 set_misa(env, MXL_RV32, 0); 207 } 208 209 static void rv32_sifive_u_cpu_init(Object *obj) 210 { 211 CPURISCVState *env = &RISCV_CPU(obj)->env; 212 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 213 set_priv_version(env, PRIV_VERSION_1_10_0); 214 } 215 216 static void rv32_sifive_e_cpu_init(Object *obj) 217 { 218 CPURISCVState *env = &RISCV_CPU(obj)->env; 219 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 220 set_priv_version(env, PRIV_VERSION_1_10_0); 221 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 222 } 223 224 static void rv32_ibex_cpu_init(Object *obj) 225 { 226 CPURISCVState *env = &RISCV_CPU(obj)->env; 227 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 228 set_priv_version(env, PRIV_VERSION_1_10_0); 229 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 230 qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); 231 } 232 233 static void rv32_imafcu_nommu_cpu_init(Object *obj) 234 { 235 CPURISCVState *env = &RISCV_CPU(obj)->env; 236 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 237 set_priv_version(env, PRIV_VERSION_1_10_0); 238 set_resetvec(env, DEFAULT_RSTVEC); 239 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 240 } 241 #endif 242 243 #if defined(CONFIG_KVM) 244 static void riscv_host_cpu_init(Object *obj) 245 { 246 CPURISCVState *env = &RISCV_CPU(obj)->env; 247 #if defined(TARGET_RISCV32) 248 set_misa(env, MXL_RV32, 0); 249 #elif defined(TARGET_RISCV64) 250 set_misa(env, MXL_RV64, 0); 251 #endif 252 } 253 #endif 254 255 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 256 { 257 ObjectClass *oc; 258 char *typename; 259 char **cpuname; 260 261 cpuname = g_strsplit(cpu_model, ",", 1); 262 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 263 oc = object_class_by_name(typename); 264 g_strfreev(cpuname); 265 g_free(typename); 266 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 267 object_class_is_abstract(oc)) { 268 return NULL; 269 } 270 return oc; 271 } 272 273 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 274 { 275 RISCVCPU *cpu = RISCV_CPU(cs); 276 CPURISCVState *env = &cpu->env; 277 int i; 278 279 #if !defined(CONFIG_USER_ONLY) 280 if (riscv_has_ext(env, RVH)) { 281 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 282 } 283 #endif 284 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 285 #ifndef CONFIG_USER_ONLY 286 { 287 static const int dump_csrs[] = { 288 CSR_MHARTID, 289 CSR_MSTATUS, 290 CSR_MSTATUSH, 291 CSR_HSTATUS, 292 CSR_VSSTATUS, 293 CSR_MIP, 294 CSR_MIE, 295 CSR_MIDELEG, 296 CSR_HIDELEG, 297 CSR_MEDELEG, 298 CSR_HEDELEG, 299 CSR_MTVEC, 300 CSR_STVEC, 301 CSR_VSTVEC, 302 CSR_MEPC, 303 CSR_SEPC, 304 CSR_VSEPC, 305 CSR_MCAUSE, 306 CSR_SCAUSE, 307 CSR_VSCAUSE, 308 CSR_MTVAL, 309 CSR_STVAL, 310 CSR_HTVAL, 311 CSR_MTVAL2, 312 CSR_MSCRATCH, 313 CSR_SSCRATCH, 314 CSR_SATP, 315 CSR_MMTE, 316 CSR_UPMBASE, 317 CSR_UPMMASK, 318 CSR_SPMBASE, 319 CSR_SPMMASK, 320 CSR_MPMBASE, 321 CSR_MPMMASK, 322 }; 323 324 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 325 int csrno = dump_csrs[i]; 326 target_ulong val = 0; 327 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 328 329 /* 330 * Rely on the smode, hmode, etc, predicates within csr.c 331 * to do the filtering of the registers that are present. 332 */ 333 if (res == RISCV_EXCP_NONE) { 334 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 335 csr_ops[csrno].name, val); 336 } 337 } 338 } 339 #endif 340 341 for (i = 0; i < 32; i++) { 342 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 343 riscv_int_regnames[i], env->gpr[i]); 344 if ((i & 3) == 3) { 345 qemu_fprintf(f, "\n"); 346 } 347 } 348 if (flags & CPU_DUMP_FPU) { 349 for (i = 0; i < 32; i++) { 350 qemu_fprintf(f, " %-8s %016" PRIx64, 351 riscv_fpr_regnames[i], env->fpr[i]); 352 if ((i & 3) == 3) { 353 qemu_fprintf(f, "\n"); 354 } 355 } 356 } 357 } 358 359 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 360 { 361 RISCVCPU *cpu = RISCV_CPU(cs); 362 CPURISCVState *env = &cpu->env; 363 364 if (env->xl == MXL_RV32) { 365 env->pc = (int32_t)value; 366 } else { 367 env->pc = value; 368 } 369 } 370 371 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 372 const TranslationBlock *tb) 373 { 374 RISCVCPU *cpu = RISCV_CPU(cs); 375 CPURISCVState *env = &cpu->env; 376 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 377 378 if (xl == MXL_RV32) { 379 env->pc = (int32_t)tb->pc; 380 } else { 381 env->pc = tb->pc; 382 } 383 } 384 385 static bool riscv_cpu_has_work(CPUState *cs) 386 { 387 #ifndef CONFIG_USER_ONLY 388 RISCVCPU *cpu = RISCV_CPU(cs); 389 CPURISCVState *env = &cpu->env; 390 /* 391 * Definition of the WFI instruction requires it to ignore the privilege 392 * mode and delegation registers, but respect individual enables 393 */ 394 return (env->mip & env->mie) != 0; 395 #else 396 return true; 397 #endif 398 } 399 400 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 401 target_ulong *data) 402 { 403 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 404 if (xl == MXL_RV32) { 405 env->pc = (int32_t)data[0]; 406 } else { 407 env->pc = data[0]; 408 } 409 } 410 411 static void riscv_cpu_reset(DeviceState *dev) 412 { 413 #ifndef CONFIG_USER_ONLY 414 uint8_t iprio; 415 int i, irq, rdzero; 416 #endif 417 CPUState *cs = CPU(dev); 418 RISCVCPU *cpu = RISCV_CPU(cs); 419 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 420 CPURISCVState *env = &cpu->env; 421 422 mcc->parent_reset(dev); 423 #ifndef CONFIG_USER_ONLY 424 env->misa_mxl = env->misa_mxl_max; 425 env->priv = PRV_M; 426 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 427 if (env->misa_mxl > MXL_RV32) { 428 /* 429 * The reset status of SXL/UXL is undefined, but mstatus is WARL 430 * and we must ensure that the value after init is valid for read. 431 */ 432 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 433 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 434 if (riscv_has_ext(env, RVH)) { 435 env->vsstatus = set_field(env->vsstatus, 436 MSTATUS64_SXL, env->misa_mxl); 437 env->vsstatus = set_field(env->vsstatus, 438 MSTATUS64_UXL, env->misa_mxl); 439 env->mstatus_hs = set_field(env->mstatus_hs, 440 MSTATUS64_SXL, env->misa_mxl); 441 env->mstatus_hs = set_field(env->mstatus_hs, 442 MSTATUS64_UXL, env->misa_mxl); 443 } 444 } 445 env->mcause = 0; 446 env->miclaim = MIP_SGEIP; 447 env->pc = env->resetvec; 448 env->two_stage_lookup = false; 449 450 /* Initialized default priorities of local interrupts. */ 451 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 452 iprio = riscv_cpu_default_priority(i); 453 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 454 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 455 env->hviprio[i] = 0; 456 } 457 i = 0; 458 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 459 if (!rdzero) { 460 env->hviprio[irq] = env->miprio[irq]; 461 } 462 i++; 463 } 464 /* mmte is supposed to have pm.current hardwired to 1 */ 465 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 466 #endif 467 env->xl = riscv_cpu_mxl(env); 468 riscv_cpu_update_mask(env); 469 cs->exception_index = RISCV_EXCP_NONE; 470 env->load_res = -1; 471 set_default_nan_mode(1, &env->fp_status); 472 473 #ifndef CONFIG_USER_ONLY 474 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 475 riscv_trigger_init(env); 476 } 477 478 if (kvm_enabled()) { 479 kvm_riscv_reset_vcpu(cpu); 480 } 481 #endif 482 } 483 484 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 485 { 486 RISCVCPU *cpu = RISCV_CPU(s); 487 488 switch (riscv_cpu_mxl(&cpu->env)) { 489 case MXL_RV32: 490 info->print_insn = print_insn_riscv32; 491 break; 492 case MXL_RV64: 493 info->print_insn = print_insn_riscv64; 494 break; 495 case MXL_RV128: 496 info->print_insn = print_insn_riscv128; 497 break; 498 default: 499 g_assert_not_reached(); 500 } 501 } 502 503 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 504 { 505 CPUState *cs = CPU(dev); 506 RISCVCPU *cpu = RISCV_CPU(dev); 507 CPURISCVState *env = &cpu->env; 508 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 509 CPUClass *cc = CPU_CLASS(mcc); 510 int priv_version = 0; 511 Error *local_err = NULL; 512 513 cpu_exec_realizefn(cs, &local_err); 514 if (local_err != NULL) { 515 error_propagate(errp, local_err); 516 return; 517 } 518 519 if (cpu->cfg.priv_spec) { 520 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 521 priv_version = PRIV_VERSION_1_12_0; 522 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 523 priv_version = PRIV_VERSION_1_11_0; 524 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 525 priv_version = PRIV_VERSION_1_10_0; 526 } else { 527 error_setg(errp, 528 "Unsupported privilege spec version '%s'", 529 cpu->cfg.priv_spec); 530 return; 531 } 532 } 533 534 if (priv_version) { 535 set_priv_version(env, priv_version); 536 } else if (!env->priv_ver) { 537 set_priv_version(env, PRIV_VERSION_1_12_0); 538 } 539 540 if (cpu->cfg.mmu) { 541 riscv_set_feature(env, RISCV_FEATURE_MMU); 542 } 543 544 if (cpu->cfg.pmp) { 545 riscv_set_feature(env, RISCV_FEATURE_PMP); 546 547 /* 548 * Enhanced PMP should only be available 549 * on harts with PMP support 550 */ 551 if (cpu->cfg.epmp) { 552 riscv_set_feature(env, RISCV_FEATURE_EPMP); 553 } 554 } 555 556 if (cpu->cfg.aia) { 557 riscv_set_feature(env, RISCV_FEATURE_AIA); 558 } 559 560 if (cpu->cfg.debug) { 561 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 562 } 563 564 set_resetvec(env, cpu->cfg.resetvec); 565 566 /* Validate that MISA_MXL is set properly. */ 567 switch (env->misa_mxl_max) { 568 #ifdef TARGET_RISCV64 569 case MXL_RV64: 570 case MXL_RV128: 571 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 572 break; 573 #endif 574 case MXL_RV32: 575 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 576 break; 577 default: 578 g_assert_not_reached(); 579 } 580 assert(env->misa_mxl_max == env->misa_mxl); 581 582 /* If only MISA_EXT is unset for misa, then set it from properties */ 583 if (env->misa_ext == 0) { 584 uint32_t ext = 0; 585 586 /* Do some ISA extension error checking */ 587 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 588 error_setg(errp, 589 "I and E extensions are incompatible"); 590 return; 591 } 592 593 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 594 error_setg(errp, 595 "Either I or E extension must be set"); 596 return; 597 } 598 599 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 600 cpu->cfg.ext_a && cpu->cfg.ext_f && 601 cpu->cfg.ext_d && 602 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 603 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 604 cpu->cfg.ext_i = true; 605 cpu->cfg.ext_m = true; 606 cpu->cfg.ext_a = true; 607 cpu->cfg.ext_f = true; 608 cpu->cfg.ext_d = true; 609 cpu->cfg.ext_icsr = true; 610 cpu->cfg.ext_ifencei = true; 611 } 612 613 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 614 error_setg(errp, "F extension requires Zicsr"); 615 return; 616 } 617 618 if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { 619 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 620 return; 621 } 622 623 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 624 error_setg(errp, "D extension requires F extension"); 625 return; 626 } 627 628 if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { 629 error_setg(errp, "V extension requires D extension"); 630 return; 631 } 632 633 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 634 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 635 return; 636 } 637 638 /* Set the ISA extensions, checks should have happened above */ 639 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || 640 cpu->cfg.ext_zhinxmin) { 641 cpu->cfg.ext_zfinx = true; 642 } 643 644 if (cpu->cfg.ext_zfinx) { 645 if (!cpu->cfg.ext_icsr) { 646 error_setg(errp, "Zfinx extension requires Zicsr"); 647 return; 648 } 649 if (cpu->cfg.ext_f) { 650 error_setg(errp, 651 "Zfinx cannot be supported together with F extension"); 652 return; 653 } 654 } 655 656 if (cpu->cfg.ext_zk) { 657 cpu->cfg.ext_zkn = true; 658 cpu->cfg.ext_zkr = true; 659 cpu->cfg.ext_zkt = true; 660 } 661 662 if (cpu->cfg.ext_zkn) { 663 cpu->cfg.ext_zbkb = true; 664 cpu->cfg.ext_zbkc = true; 665 cpu->cfg.ext_zbkx = true; 666 cpu->cfg.ext_zkne = true; 667 cpu->cfg.ext_zknd = true; 668 cpu->cfg.ext_zknh = true; 669 } 670 671 if (cpu->cfg.ext_zks) { 672 cpu->cfg.ext_zbkb = true; 673 cpu->cfg.ext_zbkc = true; 674 cpu->cfg.ext_zbkx = true; 675 cpu->cfg.ext_zksed = true; 676 cpu->cfg.ext_zksh = true; 677 } 678 679 if (cpu->cfg.ext_i) { 680 ext |= RVI; 681 } 682 if (cpu->cfg.ext_e) { 683 ext |= RVE; 684 } 685 if (cpu->cfg.ext_m) { 686 ext |= RVM; 687 } 688 if (cpu->cfg.ext_a) { 689 ext |= RVA; 690 } 691 if (cpu->cfg.ext_f) { 692 ext |= RVF; 693 } 694 if (cpu->cfg.ext_d) { 695 ext |= RVD; 696 } 697 if (cpu->cfg.ext_c) { 698 ext |= RVC; 699 } 700 if (cpu->cfg.ext_s) { 701 ext |= RVS; 702 } 703 if (cpu->cfg.ext_u) { 704 ext |= RVU; 705 } 706 if (cpu->cfg.ext_h) { 707 ext |= RVH; 708 } 709 if (cpu->cfg.ext_v) { 710 int vext_version = VEXT_VERSION_1_00_0; 711 ext |= RVV; 712 if (!is_power_of_2(cpu->cfg.vlen)) { 713 error_setg(errp, 714 "Vector extension VLEN must be power of 2"); 715 return; 716 } 717 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 718 error_setg(errp, 719 "Vector extension implementation only supports VLEN " 720 "in the range [128, %d]", RV_VLEN_MAX); 721 return; 722 } 723 if (!is_power_of_2(cpu->cfg.elen)) { 724 error_setg(errp, 725 "Vector extension ELEN must be power of 2"); 726 return; 727 } 728 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 729 error_setg(errp, 730 "Vector extension implementation only supports ELEN " 731 "in the range [8, 64]"); 732 return; 733 } 734 if (cpu->cfg.vext_spec) { 735 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 736 vext_version = VEXT_VERSION_1_00_0; 737 } else { 738 error_setg(errp, 739 "Unsupported vector spec version '%s'", 740 cpu->cfg.vext_spec); 741 return; 742 } 743 } else { 744 qemu_log("vector version is not specified, " 745 "use the default value v1.0\n"); 746 } 747 set_vext_version(env, vext_version); 748 } 749 if (cpu->cfg.ext_j) { 750 ext |= RVJ; 751 } 752 753 set_misa(env, env->misa_mxl, ext); 754 } 755 756 riscv_cpu_register_gdb_regs_for_features(cs); 757 758 qemu_init_vcpu(cs); 759 cpu_reset(cs); 760 761 mcc->parent_realize(dev, errp); 762 } 763 764 #ifndef CONFIG_USER_ONLY 765 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 766 { 767 RISCVCPU *cpu = RISCV_CPU(opaque); 768 CPURISCVState *env = &cpu->env; 769 770 if (irq < IRQ_LOCAL_MAX) { 771 switch (irq) { 772 case IRQ_U_SOFT: 773 case IRQ_S_SOFT: 774 case IRQ_VS_SOFT: 775 case IRQ_M_SOFT: 776 case IRQ_U_TIMER: 777 case IRQ_S_TIMER: 778 case IRQ_VS_TIMER: 779 case IRQ_M_TIMER: 780 case IRQ_U_EXT: 781 case IRQ_VS_EXT: 782 case IRQ_M_EXT: 783 if (kvm_enabled()) { 784 kvm_riscv_set_irq(cpu, irq, level); 785 } else { 786 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 787 } 788 break; 789 case IRQ_S_EXT: 790 if (kvm_enabled()) { 791 kvm_riscv_set_irq(cpu, irq, level); 792 } else { 793 env->external_seip = level; 794 riscv_cpu_update_mip(cpu, 1 << irq, 795 BOOL_TO_MASK(level | env->software_seip)); 796 } 797 break; 798 default: 799 g_assert_not_reached(); 800 } 801 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 802 /* Require H-extension for handling guest local interrupts */ 803 if (!riscv_has_ext(env, RVH)) { 804 g_assert_not_reached(); 805 } 806 807 /* Compute bit position in HGEIP CSR */ 808 irq = irq - IRQ_LOCAL_MAX + 1; 809 if (env->geilen < irq) { 810 g_assert_not_reached(); 811 } 812 813 /* Update HGEIP CSR */ 814 env->hgeip &= ~((target_ulong)1 << irq); 815 if (level) { 816 env->hgeip |= (target_ulong)1 << irq; 817 } 818 819 /* Update mip.SGEIP bit */ 820 riscv_cpu_update_mip(cpu, MIP_SGEIP, 821 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 822 } else { 823 g_assert_not_reached(); 824 } 825 } 826 #endif /* CONFIG_USER_ONLY */ 827 828 static void riscv_cpu_init(Object *obj) 829 { 830 RISCVCPU *cpu = RISCV_CPU(obj); 831 832 cpu_set_cpustate_pointers(cpu); 833 834 #ifndef CONFIG_USER_ONLY 835 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 836 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 837 #endif /* CONFIG_USER_ONLY */ 838 } 839 840 static Property riscv_cpu_properties[] = { 841 /* Defaults for standard extensions */ 842 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 843 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 844 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 845 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 846 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 847 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 848 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 849 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 850 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 851 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 852 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 853 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 854 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 855 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 856 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 857 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 858 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 859 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 860 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 861 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 862 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 863 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 864 865 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 866 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 867 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 868 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 869 870 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 871 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 872 DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID), 873 874 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 875 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 876 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 877 878 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 879 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 880 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 881 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 882 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 883 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 884 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 885 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 886 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 887 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 888 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 889 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 890 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 891 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 892 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 893 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 894 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 895 896 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 897 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 898 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 899 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 900 901 /* Vendor-specific custom extensions */ 902 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 903 904 /* These are experimental so mark with 'x-' */ 905 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 906 /* ePMP 0.9.3 */ 907 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 908 DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), 909 910 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 911 912 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 913 DEFINE_PROP_END_OF_LIST(), 914 }; 915 916 static gchar *riscv_gdb_arch_name(CPUState *cs) 917 { 918 RISCVCPU *cpu = RISCV_CPU(cs); 919 CPURISCVState *env = &cpu->env; 920 921 switch (riscv_cpu_mxl(env)) { 922 case MXL_RV32: 923 return g_strdup("riscv:rv32"); 924 case MXL_RV64: 925 case MXL_RV128: 926 return g_strdup("riscv:rv64"); 927 default: 928 g_assert_not_reached(); 929 } 930 } 931 932 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 933 { 934 RISCVCPU *cpu = RISCV_CPU(cs); 935 936 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 937 return cpu->dyn_csr_xml; 938 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 939 return cpu->dyn_vreg_xml; 940 } 941 942 return NULL; 943 } 944 945 #ifndef CONFIG_USER_ONLY 946 #include "hw/core/sysemu-cpu-ops.h" 947 948 static const struct SysemuCPUOps riscv_sysemu_ops = { 949 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 950 .write_elf64_note = riscv_cpu_write_elf64_note, 951 .write_elf32_note = riscv_cpu_write_elf32_note, 952 .legacy_vmsd = &vmstate_riscv_cpu, 953 }; 954 #endif 955 956 #include "hw/core/tcg-cpu-ops.h" 957 958 static const struct TCGCPUOps riscv_tcg_ops = { 959 .initialize = riscv_translate_init, 960 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 961 962 #ifndef CONFIG_USER_ONLY 963 .tlb_fill = riscv_cpu_tlb_fill, 964 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 965 .do_interrupt = riscv_cpu_do_interrupt, 966 .do_transaction_failed = riscv_cpu_do_transaction_failed, 967 .do_unaligned_access = riscv_cpu_do_unaligned_access, 968 .debug_excp_handler = riscv_cpu_debug_excp_handler, 969 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 970 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 971 #endif /* !CONFIG_USER_ONLY */ 972 }; 973 974 static void riscv_cpu_class_init(ObjectClass *c, void *data) 975 { 976 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 977 CPUClass *cc = CPU_CLASS(c); 978 DeviceClass *dc = DEVICE_CLASS(c); 979 980 device_class_set_parent_realize(dc, riscv_cpu_realize, 981 &mcc->parent_realize); 982 983 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 984 985 cc->class_by_name = riscv_cpu_class_by_name; 986 cc->has_work = riscv_cpu_has_work; 987 cc->dump_state = riscv_cpu_dump_state; 988 cc->set_pc = riscv_cpu_set_pc; 989 cc->gdb_read_register = riscv_cpu_gdb_read_register; 990 cc->gdb_write_register = riscv_cpu_gdb_write_register; 991 cc->gdb_num_core_regs = 33; 992 cc->gdb_stop_before_watchpoint = true; 993 cc->disas_set_info = riscv_cpu_disas_set_info; 994 #ifndef CONFIG_USER_ONLY 995 cc->sysemu_ops = &riscv_sysemu_ops; 996 #endif 997 cc->gdb_arch_name = riscv_gdb_arch_name; 998 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 999 cc->tcg_ops = &riscv_tcg_ops; 1000 1001 device_class_set_props(dc, riscv_cpu_properties); 1002 } 1003 1004 #define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop} 1005 1006 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1007 { 1008 char *old = *isa_str; 1009 char *new = *isa_str; 1010 int i; 1011 1012 /** 1013 * Here are the ordering rules of extension naming defined by RISC-V 1014 * specification : 1015 * 1. All extensions should be separated from other multi-letter extensions 1016 * by an underscore. 1017 * 2. The first letter following the 'Z' conventionally indicates the most 1018 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 1019 * If multiple 'Z' extensions are named, they should be ordered first 1020 * by category, then alphabetically within a category. 1021 * 3. Standard supervisor-level extensions (starts with 'S') should be 1022 * listed after standard unprivileged extensions. If multiple 1023 * supervisor-level extensions are listed, they should be ordered 1024 * alphabetically. 1025 * 4. Non-standard extensions (starts with 'X') must be listed after all 1026 * standard extensions. They must be separated from other multi-letter 1027 * extensions by an underscore. 1028 */ 1029 struct isa_ext_data isa_edata_arr[] = { 1030 ISA_EDATA_ENTRY(zfh, ext_zfh), 1031 ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), 1032 ISA_EDATA_ENTRY(zfinx, ext_zfinx), 1033 ISA_EDATA_ENTRY(zdinx, ext_zdinx), 1034 ISA_EDATA_ENTRY(zba, ext_zba), 1035 ISA_EDATA_ENTRY(zbb, ext_zbb), 1036 ISA_EDATA_ENTRY(zbc, ext_zbc), 1037 ISA_EDATA_ENTRY(zbkb, ext_zbkb), 1038 ISA_EDATA_ENTRY(zbkc, ext_zbkc), 1039 ISA_EDATA_ENTRY(zbkx, ext_zbkx), 1040 ISA_EDATA_ENTRY(zbs, ext_zbs), 1041 ISA_EDATA_ENTRY(zk, ext_zk), 1042 ISA_EDATA_ENTRY(zkn, ext_zkn), 1043 ISA_EDATA_ENTRY(zknd, ext_zknd), 1044 ISA_EDATA_ENTRY(zkne, ext_zkne), 1045 ISA_EDATA_ENTRY(zknh, ext_zknh), 1046 ISA_EDATA_ENTRY(zkr, ext_zkr), 1047 ISA_EDATA_ENTRY(zks, ext_zks), 1048 ISA_EDATA_ENTRY(zksed, ext_zksed), 1049 ISA_EDATA_ENTRY(zksh, ext_zksh), 1050 ISA_EDATA_ENTRY(zkt, ext_zkt), 1051 ISA_EDATA_ENTRY(zve32f, ext_zve32f), 1052 ISA_EDATA_ENTRY(zve64f, ext_zve64f), 1053 ISA_EDATA_ENTRY(zhinx, ext_zhinx), 1054 ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), 1055 ISA_EDATA_ENTRY(svinval, ext_svinval), 1056 ISA_EDATA_ENTRY(svnapot, ext_svnapot), 1057 ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), 1058 }; 1059 1060 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1061 if (isa_edata_arr[i].enabled) { 1062 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1063 g_free(old); 1064 old = new; 1065 } 1066 } 1067 1068 *isa_str = new; 1069 } 1070 1071 char *riscv_isa_string(RISCVCPU *cpu) 1072 { 1073 int i; 1074 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1075 char *isa_str = g_new(char, maxlen); 1076 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1077 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1078 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1079 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1080 } 1081 } 1082 *p = '\0'; 1083 if (!cpu->cfg.short_isa_string) { 1084 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1085 } 1086 return isa_str; 1087 } 1088 1089 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1090 { 1091 ObjectClass *class_a = (ObjectClass *)a; 1092 ObjectClass *class_b = (ObjectClass *)b; 1093 const char *name_a, *name_b; 1094 1095 name_a = object_class_get_name(class_a); 1096 name_b = object_class_get_name(class_b); 1097 return strcmp(name_a, name_b); 1098 } 1099 1100 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1101 { 1102 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1103 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1104 1105 qemu_printf("%.*s\n", len, typename); 1106 } 1107 1108 void riscv_cpu_list(void) 1109 { 1110 GSList *list; 1111 1112 list = object_class_get_list(TYPE_RISCV_CPU, false); 1113 list = g_slist_sort(list, riscv_cpu_list_compare); 1114 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1115 g_slist_free(list); 1116 } 1117 1118 #define DEFINE_CPU(type_name, initfn) \ 1119 { \ 1120 .name = type_name, \ 1121 .parent = TYPE_RISCV_CPU, \ 1122 .instance_init = initfn \ 1123 } 1124 1125 static const TypeInfo riscv_cpu_type_infos[] = { 1126 { 1127 .name = TYPE_RISCV_CPU, 1128 .parent = TYPE_CPU, 1129 .instance_size = sizeof(RISCVCPU), 1130 .instance_align = __alignof__(RISCVCPU), 1131 .instance_init = riscv_cpu_init, 1132 .abstract = true, 1133 .class_size = sizeof(RISCVCPUClass), 1134 .class_init = riscv_cpu_class_init, 1135 }, 1136 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1137 #if defined(CONFIG_KVM) 1138 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1139 #endif 1140 #if defined(TARGET_RISCV32) 1141 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1142 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1143 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1144 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1145 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1146 #elif defined(TARGET_RISCV64) 1147 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1148 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1149 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1150 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1151 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1152 #endif 1153 }; 1154 1155 DEFINE_TYPES(riscv_cpu_type_infos) 1156