1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qemu/error-report.h" 32 #include "hw/qdev-properties.h" 33 #include "migration/vmstate.h" 34 #include "fpu/softfloat-helpers.h" 35 #include "sysemu/kvm.h" 36 #include "kvm_riscv.h" 37 38 /* RISC-V CPU definitions */ 39 40 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 41 (QEMU_VERSION_MINOR << 8) | \ 42 (QEMU_VERSION_MICRO)) 43 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 44 45 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 46 47 struct isa_ext_data { 48 const char *name; 49 bool multi_letter; 50 int min_version; 51 int ext_enable_offset; 52 }; 53 54 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ 55 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 56 57 /** 58 * Here are the ordering rules of extension naming defined by RISC-V 59 * specification : 60 * 1. All extensions should be separated from other multi-letter extensions 61 * by an underscore. 62 * 2. The first letter following the 'Z' conventionally indicates the most 63 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 64 * If multiple 'Z' extensions are named, they should be ordered first 65 * by category, then alphabetically within a category. 66 * 3. Standard supervisor-level extensions (starts with 'S') should be 67 * listed after standard unprivileged extensions. If multiple 68 * supervisor-level extensions are listed, they should be ordered 69 * alphabetically. 70 * 4. Non-standard extensions (starts with 'X') must be listed after all 71 * standard extensions. They must be separated from other multi-letter 72 * extensions by an underscore. 73 */ 74 static const struct isa_ext_data isa_edata_arr[] = { 75 ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), 76 ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v), 77 ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond), 78 ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), 79 ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), 80 ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), 81 ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), 82 ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), 83 ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), 84 ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), 85 ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), 86 ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), 87 ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), 88 ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), 89 ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), 90 ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), 91 ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), 92 ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), 93 ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), 94 ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), 95 ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), 96 ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), 97 ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), 98 ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), 99 ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), 100 ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), 101 ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), 102 ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), 103 ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), 104 ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), 105 ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d), 106 ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh), 107 ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin), 108 ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), 109 ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), 110 ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), 111 ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), 112 ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), 113 ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), 114 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), 115 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), 116 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), 117 ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), 118 ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), 119 ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), 120 ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), 121 ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 122 ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 123 ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), 124 ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), 125 ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 126 ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), 127 ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), 128 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 129 }; 130 131 static bool isa_ext_is_enabled(RISCVCPU *cpu, 132 const struct isa_ext_data *edata) 133 { 134 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 135 136 return *ext_enabled; 137 } 138 139 static void isa_ext_update_enabled(RISCVCPU *cpu, 140 const struct isa_ext_data *edata, bool en) 141 { 142 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 143 144 *ext_enabled = en; 145 } 146 147 const char * const riscv_int_regnames[] = { 148 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 149 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 150 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 151 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 152 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 153 }; 154 155 const char * const riscv_int_regnamesh[] = { 156 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 157 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 158 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 159 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 160 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 161 "x30h/t5h", "x31h/t6h" 162 }; 163 164 const char * const riscv_fpr_regnames[] = { 165 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 166 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 167 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 168 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 169 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 170 "f30/ft10", "f31/ft11" 171 }; 172 173 static const char * const riscv_excp_names[] = { 174 "misaligned_fetch", 175 "fault_fetch", 176 "illegal_instruction", 177 "breakpoint", 178 "misaligned_load", 179 "fault_load", 180 "misaligned_store", 181 "fault_store", 182 "user_ecall", 183 "supervisor_ecall", 184 "hypervisor_ecall", 185 "machine_ecall", 186 "exec_page_fault", 187 "load_page_fault", 188 "reserved", 189 "store_page_fault", 190 "reserved", 191 "reserved", 192 "reserved", 193 "reserved", 194 "guest_exec_page_fault", 195 "guest_load_page_fault", 196 "reserved", 197 "guest_store_page_fault", 198 }; 199 200 static const char * const riscv_intr_names[] = { 201 "u_software", 202 "s_software", 203 "vs_software", 204 "m_software", 205 "u_timer", 206 "s_timer", 207 "vs_timer", 208 "m_timer", 209 "u_external", 210 "s_external", 211 "vs_external", 212 "m_external", 213 "reserved", 214 "reserved", 215 "reserved", 216 "reserved" 217 }; 218 219 static void register_cpu_props(DeviceState *dev); 220 221 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 222 { 223 if (async) { 224 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 225 riscv_intr_names[cause] : "(unknown)"; 226 } else { 227 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 228 riscv_excp_names[cause] : "(unknown)"; 229 } 230 } 231 232 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 233 { 234 env->misa_mxl_max = env->misa_mxl = mxl; 235 env->misa_ext_mask = env->misa_ext = ext; 236 } 237 238 static void set_priv_version(CPURISCVState *env, int priv_ver) 239 { 240 env->priv_ver = priv_ver; 241 } 242 243 static void set_vext_version(CPURISCVState *env, int vext_ver) 244 { 245 env->vext_ver = vext_ver; 246 } 247 248 static void riscv_any_cpu_init(Object *obj) 249 { 250 CPURISCVState *env = &RISCV_CPU(obj)->env; 251 #if defined(TARGET_RISCV32) 252 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 253 #elif defined(TARGET_RISCV64) 254 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 255 #endif 256 set_priv_version(env, PRIV_VERSION_1_12_0); 257 register_cpu_props(DEVICE(obj)); 258 } 259 260 #if defined(TARGET_RISCV64) 261 static void rv64_base_cpu_init(Object *obj) 262 { 263 CPURISCVState *env = &RISCV_CPU(obj)->env; 264 /* We set this in the realise function */ 265 set_misa(env, MXL_RV64, 0); 266 register_cpu_props(DEVICE(obj)); 267 /* Set latest version of privileged specification */ 268 set_priv_version(env, PRIV_VERSION_1_12_0); 269 } 270 271 static void rv64_sifive_u_cpu_init(Object *obj) 272 { 273 CPURISCVState *env = &RISCV_CPU(obj)->env; 274 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 275 register_cpu_props(DEVICE(obj)); 276 set_priv_version(env, PRIV_VERSION_1_10_0); 277 } 278 279 static void rv64_sifive_e_cpu_init(Object *obj) 280 { 281 CPURISCVState *env = &RISCV_CPU(obj)->env; 282 RISCVCPU *cpu = RISCV_CPU(obj); 283 284 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 285 register_cpu_props(DEVICE(obj)); 286 set_priv_version(env, PRIV_VERSION_1_10_0); 287 cpu->cfg.mmu = false; 288 } 289 290 static void rv64_thead_c906_cpu_init(Object *obj) 291 { 292 CPURISCVState *env = &RISCV_CPU(obj)->env; 293 RISCVCPU *cpu = RISCV_CPU(obj); 294 295 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 296 set_priv_version(env, PRIV_VERSION_1_11_0); 297 298 cpu->cfg.ext_g = true; 299 cpu->cfg.ext_c = true; 300 cpu->cfg.ext_u = true; 301 cpu->cfg.ext_s = true; 302 cpu->cfg.ext_icsr = true; 303 cpu->cfg.ext_zfh = true; 304 cpu->cfg.mmu = true; 305 cpu->cfg.ext_xtheadba = true; 306 cpu->cfg.ext_xtheadbb = true; 307 cpu->cfg.ext_xtheadbs = true; 308 cpu->cfg.ext_xtheadcmo = true; 309 cpu->cfg.ext_xtheadcondmov = true; 310 cpu->cfg.ext_xtheadfmemidx = true; 311 cpu->cfg.ext_xtheadmac = true; 312 cpu->cfg.ext_xtheadmemidx = true; 313 cpu->cfg.ext_xtheadmempair = true; 314 cpu->cfg.ext_xtheadsync = true; 315 316 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 317 } 318 319 static void rv128_base_cpu_init(Object *obj) 320 { 321 if (qemu_tcg_mttcg_enabled()) { 322 /* Missing 128-bit aligned atomics */ 323 error_report("128-bit RISC-V currently does not work with Multi " 324 "Threaded TCG. Please use: -accel tcg,thread=single"); 325 exit(EXIT_FAILURE); 326 } 327 CPURISCVState *env = &RISCV_CPU(obj)->env; 328 /* We set this in the realise function */ 329 set_misa(env, MXL_RV128, 0); 330 register_cpu_props(DEVICE(obj)); 331 /* Set latest version of privileged specification */ 332 set_priv_version(env, PRIV_VERSION_1_12_0); 333 } 334 #else 335 static void rv32_base_cpu_init(Object *obj) 336 { 337 CPURISCVState *env = &RISCV_CPU(obj)->env; 338 /* We set this in the realise function */ 339 set_misa(env, MXL_RV32, 0); 340 register_cpu_props(DEVICE(obj)); 341 /* Set latest version of privileged specification */ 342 set_priv_version(env, PRIV_VERSION_1_12_0); 343 } 344 345 static void rv32_sifive_u_cpu_init(Object *obj) 346 { 347 CPURISCVState *env = &RISCV_CPU(obj)->env; 348 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 349 register_cpu_props(DEVICE(obj)); 350 set_priv_version(env, PRIV_VERSION_1_10_0); 351 } 352 353 static void rv32_sifive_e_cpu_init(Object *obj) 354 { 355 CPURISCVState *env = &RISCV_CPU(obj)->env; 356 RISCVCPU *cpu = RISCV_CPU(obj); 357 358 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 359 register_cpu_props(DEVICE(obj)); 360 set_priv_version(env, PRIV_VERSION_1_10_0); 361 cpu->cfg.mmu = false; 362 } 363 364 static void rv32_ibex_cpu_init(Object *obj) 365 { 366 CPURISCVState *env = &RISCV_CPU(obj)->env; 367 RISCVCPU *cpu = RISCV_CPU(obj); 368 369 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 370 register_cpu_props(DEVICE(obj)); 371 set_priv_version(env, PRIV_VERSION_1_11_0); 372 cpu->cfg.mmu = false; 373 cpu->cfg.epmp = true; 374 } 375 376 static void rv32_imafcu_nommu_cpu_init(Object *obj) 377 { 378 CPURISCVState *env = &RISCV_CPU(obj)->env; 379 RISCVCPU *cpu = RISCV_CPU(obj); 380 381 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 382 register_cpu_props(DEVICE(obj)); 383 set_priv_version(env, PRIV_VERSION_1_10_0); 384 cpu->cfg.mmu = false; 385 } 386 #endif 387 388 #if defined(CONFIG_KVM) 389 static void riscv_host_cpu_init(Object *obj) 390 { 391 CPURISCVState *env = &RISCV_CPU(obj)->env; 392 #if defined(TARGET_RISCV32) 393 set_misa(env, MXL_RV32, 0); 394 #elif defined(TARGET_RISCV64) 395 set_misa(env, MXL_RV64, 0); 396 #endif 397 register_cpu_props(DEVICE(obj)); 398 } 399 #endif 400 401 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 402 { 403 ObjectClass *oc; 404 char *typename; 405 char **cpuname; 406 407 cpuname = g_strsplit(cpu_model, ",", 1); 408 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 409 oc = object_class_by_name(typename); 410 g_strfreev(cpuname); 411 g_free(typename); 412 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 413 object_class_is_abstract(oc)) { 414 return NULL; 415 } 416 return oc; 417 } 418 419 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 420 { 421 RISCVCPU *cpu = RISCV_CPU(cs); 422 CPURISCVState *env = &cpu->env; 423 int i; 424 425 #if !defined(CONFIG_USER_ONLY) 426 if (riscv_has_ext(env, RVH)) { 427 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 428 } 429 #endif 430 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 431 #ifndef CONFIG_USER_ONLY 432 { 433 static const int dump_csrs[] = { 434 CSR_MHARTID, 435 CSR_MSTATUS, 436 CSR_MSTATUSH, 437 /* 438 * CSR_SSTATUS is intentionally omitted here as its value 439 * can be figured out by looking at CSR_MSTATUS 440 */ 441 CSR_HSTATUS, 442 CSR_VSSTATUS, 443 CSR_MIP, 444 CSR_MIE, 445 CSR_MIDELEG, 446 CSR_HIDELEG, 447 CSR_MEDELEG, 448 CSR_HEDELEG, 449 CSR_MTVEC, 450 CSR_STVEC, 451 CSR_VSTVEC, 452 CSR_MEPC, 453 CSR_SEPC, 454 CSR_VSEPC, 455 CSR_MCAUSE, 456 CSR_SCAUSE, 457 CSR_VSCAUSE, 458 CSR_MTVAL, 459 CSR_STVAL, 460 CSR_HTVAL, 461 CSR_MTVAL2, 462 CSR_MSCRATCH, 463 CSR_SSCRATCH, 464 CSR_SATP, 465 CSR_MMTE, 466 CSR_UPMBASE, 467 CSR_UPMMASK, 468 CSR_SPMBASE, 469 CSR_SPMMASK, 470 CSR_MPMBASE, 471 CSR_MPMMASK, 472 }; 473 474 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 475 int csrno = dump_csrs[i]; 476 target_ulong val = 0; 477 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 478 479 /* 480 * Rely on the smode, hmode, etc, predicates within csr.c 481 * to do the filtering of the registers that are present. 482 */ 483 if (res == RISCV_EXCP_NONE) { 484 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 485 csr_ops[csrno].name, val); 486 } 487 } 488 } 489 #endif 490 491 for (i = 0; i < 32; i++) { 492 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 493 riscv_int_regnames[i], env->gpr[i]); 494 if ((i & 3) == 3) { 495 qemu_fprintf(f, "\n"); 496 } 497 } 498 if (flags & CPU_DUMP_FPU) { 499 for (i = 0; i < 32; i++) { 500 qemu_fprintf(f, " %-8s %016" PRIx64, 501 riscv_fpr_regnames[i], env->fpr[i]); 502 if ((i & 3) == 3) { 503 qemu_fprintf(f, "\n"); 504 } 505 } 506 } 507 } 508 509 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 510 { 511 RISCVCPU *cpu = RISCV_CPU(cs); 512 CPURISCVState *env = &cpu->env; 513 514 if (env->xl == MXL_RV32) { 515 env->pc = (int32_t)value; 516 } else { 517 env->pc = value; 518 } 519 } 520 521 static vaddr riscv_cpu_get_pc(CPUState *cs) 522 { 523 RISCVCPU *cpu = RISCV_CPU(cs); 524 CPURISCVState *env = &cpu->env; 525 526 /* Match cpu_get_tb_cpu_state. */ 527 if (env->xl == MXL_RV32) { 528 return env->pc & UINT32_MAX; 529 } 530 return env->pc; 531 } 532 533 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 534 const TranslationBlock *tb) 535 { 536 RISCVCPU *cpu = RISCV_CPU(cs); 537 CPURISCVState *env = &cpu->env; 538 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 539 540 if (xl == MXL_RV32) { 541 env->pc = (int32_t)tb_pc(tb); 542 } else { 543 env->pc = tb_pc(tb); 544 } 545 } 546 547 static bool riscv_cpu_has_work(CPUState *cs) 548 { 549 #ifndef CONFIG_USER_ONLY 550 RISCVCPU *cpu = RISCV_CPU(cs); 551 CPURISCVState *env = &cpu->env; 552 /* 553 * Definition of the WFI instruction requires it to ignore the privilege 554 * mode and delegation registers, but respect individual enables 555 */ 556 return riscv_cpu_all_pending(env) != 0; 557 #else 558 return true; 559 #endif 560 } 561 562 static void riscv_restore_state_to_opc(CPUState *cs, 563 const TranslationBlock *tb, 564 const uint64_t *data) 565 { 566 RISCVCPU *cpu = RISCV_CPU(cs); 567 CPURISCVState *env = &cpu->env; 568 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 569 570 if (xl == MXL_RV32) { 571 env->pc = (int32_t)data[0]; 572 } else { 573 env->pc = data[0]; 574 } 575 env->bins = data[1]; 576 } 577 578 static void riscv_cpu_reset_hold(Object *obj) 579 { 580 #ifndef CONFIG_USER_ONLY 581 uint8_t iprio; 582 int i, irq, rdzero; 583 #endif 584 CPUState *cs = CPU(obj); 585 RISCVCPU *cpu = RISCV_CPU(cs); 586 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 587 CPURISCVState *env = &cpu->env; 588 589 if (mcc->parent_phases.hold) { 590 mcc->parent_phases.hold(obj); 591 } 592 #ifndef CONFIG_USER_ONLY 593 env->misa_mxl = env->misa_mxl_max; 594 env->priv = PRV_M; 595 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 596 if (env->misa_mxl > MXL_RV32) { 597 /* 598 * The reset status of SXL/UXL is undefined, but mstatus is WARL 599 * and we must ensure that the value after init is valid for read. 600 */ 601 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 602 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 603 if (riscv_has_ext(env, RVH)) { 604 env->vsstatus = set_field(env->vsstatus, 605 MSTATUS64_SXL, env->misa_mxl); 606 env->vsstatus = set_field(env->vsstatus, 607 MSTATUS64_UXL, env->misa_mxl); 608 env->mstatus_hs = set_field(env->mstatus_hs, 609 MSTATUS64_SXL, env->misa_mxl); 610 env->mstatus_hs = set_field(env->mstatus_hs, 611 MSTATUS64_UXL, env->misa_mxl); 612 } 613 } 614 env->mcause = 0; 615 env->miclaim = MIP_SGEIP; 616 env->pc = env->resetvec; 617 env->bins = 0; 618 env->two_stage_lookup = false; 619 620 /* Initialized default priorities of local interrupts. */ 621 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 622 iprio = riscv_cpu_default_priority(i); 623 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 624 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 625 env->hviprio[i] = 0; 626 } 627 i = 0; 628 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 629 if (!rdzero) { 630 env->hviprio[irq] = env->miprio[irq]; 631 } 632 i++; 633 } 634 /* mmte is supposed to have pm.current hardwired to 1 */ 635 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 636 #endif 637 env->xl = riscv_cpu_mxl(env); 638 riscv_cpu_update_mask(env); 639 cs->exception_index = RISCV_EXCP_NONE; 640 env->load_res = -1; 641 set_default_nan_mode(1, &env->fp_status); 642 643 #ifndef CONFIG_USER_ONLY 644 if (cpu->cfg.debug) { 645 riscv_trigger_init(env); 646 } 647 648 if (kvm_enabled()) { 649 kvm_riscv_reset_vcpu(cpu); 650 } 651 #endif 652 } 653 654 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 655 { 656 RISCVCPU *cpu = RISCV_CPU(s); 657 658 switch (riscv_cpu_mxl(&cpu->env)) { 659 case MXL_RV32: 660 info->print_insn = print_insn_riscv32; 661 break; 662 case MXL_RV64: 663 info->print_insn = print_insn_riscv64; 664 break; 665 case MXL_RV128: 666 info->print_insn = print_insn_riscv128; 667 break; 668 default: 669 g_assert_not_reached(); 670 } 671 } 672 673 /* 674 * Check consistency between chosen extensions while setting 675 * cpu->cfg accordingly, doing a set_misa() in the end. 676 */ 677 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 678 { 679 CPURISCVState *env = &cpu->env; 680 uint32_t ext = 0; 681 682 /* Do some ISA extension error checking */ 683 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 684 cpu->cfg.ext_a && cpu->cfg.ext_f && 685 cpu->cfg.ext_d && 686 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 687 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 688 cpu->cfg.ext_i = true; 689 cpu->cfg.ext_m = true; 690 cpu->cfg.ext_a = true; 691 cpu->cfg.ext_f = true; 692 cpu->cfg.ext_d = true; 693 cpu->cfg.ext_icsr = true; 694 cpu->cfg.ext_ifencei = true; 695 } 696 697 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 698 error_setg(errp, 699 "I and E extensions are incompatible"); 700 return; 701 } 702 703 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 704 error_setg(errp, 705 "Either I or E extension must be set"); 706 return; 707 } 708 709 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 710 error_setg(errp, 711 "Setting S extension without U extension is illegal"); 712 return; 713 } 714 715 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { 716 error_setg(errp, 717 "H depends on an I base integer ISA with 32 x registers"); 718 return; 719 } 720 721 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 722 error_setg(errp, "H extension implicitly requires S-mode"); 723 return; 724 } 725 726 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 727 error_setg(errp, "F extension requires Zicsr"); 728 return; 729 } 730 731 if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { 732 error_setg(errp, "Zawrs extension requires A extension"); 733 return; 734 } 735 736 if (cpu->cfg.ext_zfh) { 737 cpu->cfg.ext_zfhmin = true; 738 } 739 740 if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { 741 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 742 return; 743 } 744 745 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 746 error_setg(errp, "D extension requires F extension"); 747 return; 748 } 749 750 /* The V vector extension depends on the Zve64d extension */ 751 if (cpu->cfg.ext_v) { 752 cpu->cfg.ext_zve64d = true; 753 } 754 755 /* The Zve64d extension depends on the Zve64f extension */ 756 if (cpu->cfg.ext_zve64d) { 757 cpu->cfg.ext_zve64f = true; 758 } 759 760 /* The Zve64f extension depends on the Zve32f extension */ 761 if (cpu->cfg.ext_zve64f) { 762 cpu->cfg.ext_zve32f = true; 763 } 764 765 if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { 766 error_setg(errp, "Zve64d/V extensions require D extension"); 767 return; 768 } 769 770 if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { 771 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 772 return; 773 } 774 775 if (cpu->cfg.ext_zvfh) { 776 cpu->cfg.ext_zvfhmin = true; 777 } 778 779 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 780 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 781 return; 782 } 783 784 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 785 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 786 return; 787 } 788 789 /* Set the ISA extensions, checks should have happened above */ 790 if (cpu->cfg.ext_zhinx) { 791 cpu->cfg.ext_zhinxmin = true; 792 } 793 794 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { 795 cpu->cfg.ext_zfinx = true; 796 } 797 798 if (cpu->cfg.ext_zfinx) { 799 if (!cpu->cfg.ext_icsr) { 800 error_setg(errp, "Zfinx extension requires Zicsr"); 801 return; 802 } 803 if (cpu->cfg.ext_f) { 804 error_setg(errp, 805 "Zfinx cannot be supported together with F extension"); 806 return; 807 } 808 } 809 810 if (cpu->cfg.ext_zk) { 811 cpu->cfg.ext_zkn = true; 812 cpu->cfg.ext_zkr = true; 813 cpu->cfg.ext_zkt = true; 814 } 815 816 if (cpu->cfg.ext_zkn) { 817 cpu->cfg.ext_zbkb = true; 818 cpu->cfg.ext_zbkc = true; 819 cpu->cfg.ext_zbkx = true; 820 cpu->cfg.ext_zkne = true; 821 cpu->cfg.ext_zknd = true; 822 cpu->cfg.ext_zknh = true; 823 } 824 825 if (cpu->cfg.ext_zks) { 826 cpu->cfg.ext_zbkb = true; 827 cpu->cfg.ext_zbkc = true; 828 cpu->cfg.ext_zbkx = true; 829 cpu->cfg.ext_zksed = true; 830 cpu->cfg.ext_zksh = true; 831 } 832 833 if (cpu->cfg.ext_i) { 834 ext |= RVI; 835 } 836 if (cpu->cfg.ext_e) { 837 ext |= RVE; 838 } 839 if (cpu->cfg.ext_m) { 840 ext |= RVM; 841 } 842 if (cpu->cfg.ext_a) { 843 ext |= RVA; 844 } 845 if (cpu->cfg.ext_f) { 846 ext |= RVF; 847 } 848 if (cpu->cfg.ext_d) { 849 ext |= RVD; 850 } 851 if (cpu->cfg.ext_c) { 852 ext |= RVC; 853 } 854 if (cpu->cfg.ext_s) { 855 ext |= RVS; 856 } 857 if (cpu->cfg.ext_u) { 858 ext |= RVU; 859 } 860 if (cpu->cfg.ext_h) { 861 ext |= RVH; 862 } 863 if (cpu->cfg.ext_v) { 864 int vext_version = VEXT_VERSION_1_00_0; 865 ext |= RVV; 866 if (!is_power_of_2(cpu->cfg.vlen)) { 867 error_setg(errp, 868 "Vector extension VLEN must be power of 2"); 869 return; 870 } 871 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 872 error_setg(errp, 873 "Vector extension implementation only supports VLEN " 874 "in the range [128, %d]", RV_VLEN_MAX); 875 return; 876 } 877 if (!is_power_of_2(cpu->cfg.elen)) { 878 error_setg(errp, 879 "Vector extension ELEN must be power of 2"); 880 return; 881 } 882 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 883 error_setg(errp, 884 "Vector extension implementation only supports ELEN " 885 "in the range [8, 64]"); 886 return; 887 } 888 if (cpu->cfg.vext_spec) { 889 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 890 vext_version = VEXT_VERSION_1_00_0; 891 } else { 892 error_setg(errp, 893 "Unsupported vector spec version '%s'", 894 cpu->cfg.vext_spec); 895 return; 896 } 897 } else { 898 qemu_log("vector version is not specified, " 899 "use the default value v1.0\n"); 900 } 901 set_vext_version(env, vext_version); 902 } 903 if (cpu->cfg.ext_j) { 904 ext |= RVJ; 905 } 906 907 set_misa(env, env->misa_mxl, ext); 908 } 909 910 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 911 { 912 CPUState *cs = CPU(dev); 913 RISCVCPU *cpu = RISCV_CPU(dev); 914 CPURISCVState *env = &cpu->env; 915 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 916 CPUClass *cc = CPU_CLASS(mcc); 917 int i, priv_version = -1; 918 Error *local_err = NULL; 919 920 cpu_exec_realizefn(cs, &local_err); 921 if (local_err != NULL) { 922 error_propagate(errp, local_err); 923 return; 924 } 925 926 if (cpu->cfg.priv_spec) { 927 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 928 priv_version = PRIV_VERSION_1_12_0; 929 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 930 priv_version = PRIV_VERSION_1_11_0; 931 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 932 priv_version = PRIV_VERSION_1_10_0; 933 } else { 934 error_setg(errp, 935 "Unsupported privilege spec version '%s'", 936 cpu->cfg.priv_spec); 937 return; 938 } 939 } 940 941 if (priv_version >= PRIV_VERSION_1_10_0) { 942 set_priv_version(env, priv_version); 943 } 944 945 /* Force disable extensions if priv spec version does not match */ 946 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 947 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 948 (env->priv_ver < isa_edata_arr[i].min_version)) { 949 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 950 #ifndef CONFIG_USER_ONLY 951 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 952 " because privilege spec version does not match", 953 isa_edata_arr[i].name, env->mhartid); 954 #else 955 warn_report("disabling %s extension because " 956 "privilege spec version does not match", 957 isa_edata_arr[i].name); 958 #endif 959 } 960 } 961 962 if (cpu->cfg.epmp && !cpu->cfg.pmp) { 963 /* 964 * Enhanced PMP should only be available 965 * on harts with PMP support 966 */ 967 error_setg(errp, "Invalid configuration: EPMP requires PMP support"); 968 return; 969 } 970 971 972 #ifndef CONFIG_USER_ONLY 973 if (cpu->cfg.ext_sstc) { 974 riscv_timer_init(cpu); 975 } 976 #endif /* CONFIG_USER_ONLY */ 977 978 /* Validate that MISA_MXL is set properly. */ 979 switch (env->misa_mxl_max) { 980 #ifdef TARGET_RISCV64 981 case MXL_RV64: 982 case MXL_RV128: 983 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 984 break; 985 #endif 986 case MXL_RV32: 987 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 988 break; 989 default: 990 g_assert_not_reached(); 991 } 992 assert(env->misa_mxl_max == env->misa_mxl); 993 994 riscv_cpu_validate_set_extensions(cpu, &local_err); 995 if (local_err != NULL) { 996 error_propagate(errp, local_err); 997 return; 998 } 999 1000 #ifndef CONFIG_USER_ONLY 1001 if (cpu->cfg.pmu_num) { 1002 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 1003 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1004 riscv_pmu_timer_cb, cpu); 1005 } 1006 } 1007 #endif 1008 1009 riscv_cpu_register_gdb_regs_for_features(cs); 1010 1011 qemu_init_vcpu(cs); 1012 cpu_reset(cs); 1013 1014 mcc->parent_realize(dev, errp); 1015 } 1016 1017 #ifndef CONFIG_USER_ONLY 1018 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1019 { 1020 RISCVCPU *cpu = RISCV_CPU(opaque); 1021 CPURISCVState *env = &cpu->env; 1022 1023 if (irq < IRQ_LOCAL_MAX) { 1024 switch (irq) { 1025 case IRQ_U_SOFT: 1026 case IRQ_S_SOFT: 1027 case IRQ_VS_SOFT: 1028 case IRQ_M_SOFT: 1029 case IRQ_U_TIMER: 1030 case IRQ_S_TIMER: 1031 case IRQ_VS_TIMER: 1032 case IRQ_M_TIMER: 1033 case IRQ_U_EXT: 1034 case IRQ_VS_EXT: 1035 case IRQ_M_EXT: 1036 if (kvm_enabled()) { 1037 kvm_riscv_set_irq(cpu, irq, level); 1038 } else { 1039 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 1040 } 1041 break; 1042 case IRQ_S_EXT: 1043 if (kvm_enabled()) { 1044 kvm_riscv_set_irq(cpu, irq, level); 1045 } else { 1046 env->external_seip = level; 1047 riscv_cpu_update_mip(cpu, 1 << irq, 1048 BOOL_TO_MASK(level | env->software_seip)); 1049 } 1050 break; 1051 default: 1052 g_assert_not_reached(); 1053 } 1054 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1055 /* Require H-extension for handling guest local interrupts */ 1056 if (!riscv_has_ext(env, RVH)) { 1057 g_assert_not_reached(); 1058 } 1059 1060 /* Compute bit position in HGEIP CSR */ 1061 irq = irq - IRQ_LOCAL_MAX + 1; 1062 if (env->geilen < irq) { 1063 g_assert_not_reached(); 1064 } 1065 1066 /* Update HGEIP CSR */ 1067 env->hgeip &= ~((target_ulong)1 << irq); 1068 if (level) { 1069 env->hgeip |= (target_ulong)1 << irq; 1070 } 1071 1072 /* Update mip.SGEIP bit */ 1073 riscv_cpu_update_mip(cpu, MIP_SGEIP, 1074 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1075 } else { 1076 g_assert_not_reached(); 1077 } 1078 } 1079 #endif /* CONFIG_USER_ONLY */ 1080 1081 static void riscv_cpu_init(Object *obj) 1082 { 1083 RISCVCPU *cpu = RISCV_CPU(obj); 1084 1085 cpu->cfg.ext_ifencei = true; 1086 cpu->cfg.ext_icsr = true; 1087 cpu->cfg.mmu = true; 1088 cpu->cfg.pmp = true; 1089 1090 cpu_set_cpustate_pointers(cpu); 1091 1092 #ifndef CONFIG_USER_ONLY 1093 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1094 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1095 #endif /* CONFIG_USER_ONLY */ 1096 } 1097 1098 static Property riscv_cpu_extensions[] = { 1099 /* Defaults for standard extensions */ 1100 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 1101 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 1102 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1103 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 1104 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 1105 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 1106 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 1107 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 1108 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 1109 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1110 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1111 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1112 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1113 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1114 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1115 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1116 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1117 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1118 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1119 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1120 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1121 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1122 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), 1123 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1124 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1125 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1126 1127 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1128 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1129 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1130 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1131 1132 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1133 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1134 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1135 1136 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1137 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1138 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1139 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1140 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1141 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1142 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1143 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1144 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1145 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1146 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1147 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1148 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1149 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1150 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1151 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1152 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1153 1154 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1155 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1156 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1157 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1158 1159 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1160 1161 /* Vendor-specific custom extensions */ 1162 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1163 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1164 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1165 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1166 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1167 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1168 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1169 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1170 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1171 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1172 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1173 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1174 1175 /* These are experimental so mark with 'x-' */ 1176 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), 1177 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1178 /* ePMP 0.9.3 */ 1179 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1180 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1181 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1182 1183 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), 1184 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), 1185 1186 DEFINE_PROP_END_OF_LIST(), 1187 }; 1188 1189 /* 1190 * Register CPU props based on env.misa_ext. If a non-zero 1191 * value was set, register only the required cpu->cfg.ext_* 1192 * properties and leave. env.misa_ext = 0 means that we want 1193 * all the default properties to be registered. 1194 */ 1195 static void register_cpu_props(DeviceState *dev) 1196 { 1197 RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); 1198 uint32_t misa_ext = cpu->env.misa_ext; 1199 Property *prop; 1200 1201 /* 1202 * If misa_ext is not zero, set cfg properties now to 1203 * allow them to be read during riscv_cpu_realize() 1204 * later on. 1205 */ 1206 if (cpu->env.misa_ext != 0) { 1207 cpu->cfg.ext_i = misa_ext & RVI; 1208 cpu->cfg.ext_e = misa_ext & RVE; 1209 cpu->cfg.ext_m = misa_ext & RVM; 1210 cpu->cfg.ext_a = misa_ext & RVA; 1211 cpu->cfg.ext_f = misa_ext & RVF; 1212 cpu->cfg.ext_d = misa_ext & RVD; 1213 cpu->cfg.ext_v = misa_ext & RVV; 1214 cpu->cfg.ext_c = misa_ext & RVC; 1215 cpu->cfg.ext_s = misa_ext & RVS; 1216 cpu->cfg.ext_u = misa_ext & RVU; 1217 cpu->cfg.ext_h = misa_ext & RVH; 1218 cpu->cfg.ext_j = misa_ext & RVJ; 1219 1220 /* 1221 * We don't want to set the default riscv_cpu_extensions 1222 * in this case. 1223 */ 1224 return; 1225 } 1226 1227 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1228 qdev_property_add_static(dev, prop); 1229 } 1230 } 1231 1232 static Property riscv_cpu_properties[] = { 1233 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1234 1235 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1236 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1237 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1238 1239 #ifndef CONFIG_USER_ONLY 1240 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1241 #endif 1242 1243 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1244 1245 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1246 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1247 1248 /* 1249 * write_misa() is marked as experimental for now so mark 1250 * it with -x and default to 'false'. 1251 */ 1252 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1253 DEFINE_PROP_END_OF_LIST(), 1254 }; 1255 1256 static gchar *riscv_gdb_arch_name(CPUState *cs) 1257 { 1258 RISCVCPU *cpu = RISCV_CPU(cs); 1259 CPURISCVState *env = &cpu->env; 1260 1261 switch (riscv_cpu_mxl(env)) { 1262 case MXL_RV32: 1263 return g_strdup("riscv:rv32"); 1264 case MXL_RV64: 1265 case MXL_RV128: 1266 return g_strdup("riscv:rv64"); 1267 default: 1268 g_assert_not_reached(); 1269 } 1270 } 1271 1272 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1273 { 1274 RISCVCPU *cpu = RISCV_CPU(cs); 1275 1276 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1277 return cpu->dyn_csr_xml; 1278 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1279 return cpu->dyn_vreg_xml; 1280 } 1281 1282 return NULL; 1283 } 1284 1285 #ifndef CONFIG_USER_ONLY 1286 #include "hw/core/sysemu-cpu-ops.h" 1287 1288 static const struct SysemuCPUOps riscv_sysemu_ops = { 1289 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1290 .write_elf64_note = riscv_cpu_write_elf64_note, 1291 .write_elf32_note = riscv_cpu_write_elf32_note, 1292 .legacy_vmsd = &vmstate_riscv_cpu, 1293 }; 1294 #endif 1295 1296 #include "hw/core/tcg-cpu-ops.h" 1297 1298 static const struct TCGCPUOps riscv_tcg_ops = { 1299 .initialize = riscv_translate_init, 1300 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1301 .restore_state_to_opc = riscv_restore_state_to_opc, 1302 1303 #ifndef CONFIG_USER_ONLY 1304 .tlb_fill = riscv_cpu_tlb_fill, 1305 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1306 .do_interrupt = riscv_cpu_do_interrupt, 1307 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1308 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1309 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1310 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1311 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1312 #endif /* !CONFIG_USER_ONLY */ 1313 }; 1314 1315 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1316 { 1317 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1318 CPUClass *cc = CPU_CLASS(c); 1319 DeviceClass *dc = DEVICE_CLASS(c); 1320 ResettableClass *rc = RESETTABLE_CLASS(c); 1321 1322 device_class_set_parent_realize(dc, riscv_cpu_realize, 1323 &mcc->parent_realize); 1324 1325 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1326 &mcc->parent_phases); 1327 1328 cc->class_by_name = riscv_cpu_class_by_name; 1329 cc->has_work = riscv_cpu_has_work; 1330 cc->dump_state = riscv_cpu_dump_state; 1331 cc->set_pc = riscv_cpu_set_pc; 1332 cc->get_pc = riscv_cpu_get_pc; 1333 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1334 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1335 cc->gdb_num_core_regs = 33; 1336 cc->gdb_stop_before_watchpoint = true; 1337 cc->disas_set_info = riscv_cpu_disas_set_info; 1338 #ifndef CONFIG_USER_ONLY 1339 cc->sysemu_ops = &riscv_sysemu_ops; 1340 #endif 1341 cc->gdb_arch_name = riscv_gdb_arch_name; 1342 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1343 cc->tcg_ops = &riscv_tcg_ops; 1344 1345 device_class_set_props(dc, riscv_cpu_properties); 1346 } 1347 1348 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1349 { 1350 char *old = *isa_str; 1351 char *new = *isa_str; 1352 int i; 1353 1354 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1355 if (isa_edata_arr[i].multi_letter && 1356 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1357 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1358 g_free(old); 1359 old = new; 1360 } 1361 } 1362 1363 *isa_str = new; 1364 } 1365 1366 char *riscv_isa_string(RISCVCPU *cpu) 1367 { 1368 int i; 1369 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1370 char *isa_str = g_new(char, maxlen); 1371 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1372 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1373 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1374 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1375 } 1376 } 1377 *p = '\0'; 1378 if (!cpu->cfg.short_isa_string) { 1379 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1380 } 1381 return isa_str; 1382 } 1383 1384 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1385 { 1386 ObjectClass *class_a = (ObjectClass *)a; 1387 ObjectClass *class_b = (ObjectClass *)b; 1388 const char *name_a, *name_b; 1389 1390 name_a = object_class_get_name(class_a); 1391 name_b = object_class_get_name(class_b); 1392 return strcmp(name_a, name_b); 1393 } 1394 1395 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1396 { 1397 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1398 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1399 1400 qemu_printf("%.*s\n", len, typename); 1401 } 1402 1403 void riscv_cpu_list(void) 1404 { 1405 GSList *list; 1406 1407 list = object_class_get_list(TYPE_RISCV_CPU, false); 1408 list = g_slist_sort(list, riscv_cpu_list_compare); 1409 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1410 g_slist_free(list); 1411 } 1412 1413 #define DEFINE_CPU(type_name, initfn) \ 1414 { \ 1415 .name = type_name, \ 1416 .parent = TYPE_RISCV_CPU, \ 1417 .instance_init = initfn \ 1418 } 1419 1420 static const TypeInfo riscv_cpu_type_infos[] = { 1421 { 1422 .name = TYPE_RISCV_CPU, 1423 .parent = TYPE_CPU, 1424 .instance_size = sizeof(RISCVCPU), 1425 .instance_align = __alignof__(RISCVCPU), 1426 .instance_init = riscv_cpu_init, 1427 .abstract = true, 1428 .class_size = sizeof(RISCVCPUClass), 1429 .class_init = riscv_cpu_class_init, 1430 }, 1431 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1432 #if defined(CONFIG_KVM) 1433 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1434 #endif 1435 #if defined(TARGET_RISCV32) 1436 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1437 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1438 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1439 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1440 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1441 #elif defined(TARGET_RISCV64) 1442 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1443 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1444 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1445 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1446 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1447 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1448 #endif 1449 }; 1450 1451 DEFINE_TYPES(riscv_cpu_type_infos) 1452