1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "pmu.h" 26 #include "internals.h" 27 #include "time_helper.h" 28 #include "exec/exec-all.h" 29 #include "qapi/error.h" 30 #include "qemu/error-report.h" 31 #include "hw/qdev-properties.h" 32 #include "migration/vmstate.h" 33 #include "fpu/softfloat-helpers.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_riscv.h" 36 37 /* RISC-V CPU definitions */ 38 39 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 40 (QEMU_VERSION_MINOR << 8) | \ 41 (QEMU_VERSION_MICRO)) 42 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 43 44 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 45 46 struct isa_ext_data { 47 const char *name; 48 bool multi_letter; 49 int min_version; 50 int ext_enable_offset; 51 }; 52 53 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ 54 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 55 56 /** 57 * Here are the ordering rules of extension naming defined by RISC-V 58 * specification : 59 * 1. All extensions should be separated from other multi-letter extensions 60 * by an underscore. 61 * 2. The first letter following the 'Z' conventionally indicates the most 62 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 63 * If multiple 'Z' extensions are named, they should be ordered first 64 * by category, then alphabetically within a category. 65 * 3. Standard supervisor-level extensions (starts with 'S') should be 66 * listed after standard unprivileged extensions. If multiple 67 * supervisor-level extensions are listed, they should be ordered 68 * alphabetically. 69 * 4. Non-standard extensions (starts with 'X') must be listed after all 70 * standard extensions. They must be separated from other multi-letter 71 * extensions by an underscore. 72 */ 73 static const struct isa_ext_data isa_edata_arr[] = { 74 ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), 75 ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), 76 ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), 77 ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), 78 ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), 79 ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), 80 ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), 81 ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), 82 ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), 83 ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), 84 ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), 85 ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), 86 ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), 87 ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), 88 ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), 89 ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), 90 ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), 91 ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), 92 ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), 93 ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), 94 ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), 95 ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), 96 ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), 97 ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), 98 ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), 99 ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), 100 ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), 101 ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), 102 ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), 103 ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), 104 ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), 105 ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), 106 ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), 107 ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), 108 ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), 109 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), 110 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), 111 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), 112 ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), 113 ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), 114 ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), 115 ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), 116 ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 117 ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), 118 ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), 119 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 120 }; 121 122 static bool isa_ext_is_enabled(RISCVCPU *cpu, 123 const struct isa_ext_data *edata) 124 { 125 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 126 127 return *ext_enabled; 128 } 129 130 static void isa_ext_update_enabled(RISCVCPU *cpu, 131 const struct isa_ext_data *edata, bool en) 132 { 133 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 134 135 *ext_enabled = en; 136 } 137 138 const char * const riscv_int_regnames[] = { 139 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 140 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 141 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 142 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 143 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 144 }; 145 146 const char * const riscv_int_regnamesh[] = { 147 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 148 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 149 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 150 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 151 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 152 "x30h/t5h", "x31h/t6h" 153 }; 154 155 const char * const riscv_fpr_regnames[] = { 156 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 157 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 158 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 159 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 160 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 161 "f30/ft10", "f31/ft11" 162 }; 163 164 static const char * const riscv_excp_names[] = { 165 "misaligned_fetch", 166 "fault_fetch", 167 "illegal_instruction", 168 "breakpoint", 169 "misaligned_load", 170 "fault_load", 171 "misaligned_store", 172 "fault_store", 173 "user_ecall", 174 "supervisor_ecall", 175 "hypervisor_ecall", 176 "machine_ecall", 177 "exec_page_fault", 178 "load_page_fault", 179 "reserved", 180 "store_page_fault", 181 "reserved", 182 "reserved", 183 "reserved", 184 "reserved", 185 "guest_exec_page_fault", 186 "guest_load_page_fault", 187 "reserved", 188 "guest_store_page_fault", 189 }; 190 191 static const char * const riscv_intr_names[] = { 192 "u_software", 193 "s_software", 194 "vs_software", 195 "m_software", 196 "u_timer", 197 "s_timer", 198 "vs_timer", 199 "m_timer", 200 "u_external", 201 "s_external", 202 "vs_external", 203 "m_external", 204 "reserved", 205 "reserved", 206 "reserved", 207 "reserved" 208 }; 209 210 static void register_cpu_props(DeviceState *dev); 211 212 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 213 { 214 if (async) { 215 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 216 riscv_intr_names[cause] : "(unknown)"; 217 } else { 218 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 219 riscv_excp_names[cause] : "(unknown)"; 220 } 221 } 222 223 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 224 { 225 env->misa_mxl_max = env->misa_mxl = mxl; 226 env->misa_ext_mask = env->misa_ext = ext; 227 } 228 229 static void set_priv_version(CPURISCVState *env, int priv_ver) 230 { 231 env->priv_ver = priv_ver; 232 } 233 234 static void set_vext_version(CPURISCVState *env, int vext_ver) 235 { 236 env->vext_ver = vext_ver; 237 } 238 239 static void riscv_any_cpu_init(Object *obj) 240 { 241 CPURISCVState *env = &RISCV_CPU(obj)->env; 242 #if defined(TARGET_RISCV32) 243 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 244 #elif defined(TARGET_RISCV64) 245 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 246 #endif 247 set_priv_version(env, PRIV_VERSION_1_12_0); 248 register_cpu_props(DEVICE(obj)); 249 } 250 251 #if defined(TARGET_RISCV64) 252 static void rv64_base_cpu_init(Object *obj) 253 { 254 CPURISCVState *env = &RISCV_CPU(obj)->env; 255 /* We set this in the realise function */ 256 set_misa(env, MXL_RV64, 0); 257 register_cpu_props(DEVICE(obj)); 258 /* Set latest version of privileged specification */ 259 set_priv_version(env, PRIV_VERSION_1_12_0); 260 } 261 262 static void rv64_sifive_u_cpu_init(Object *obj) 263 { 264 CPURISCVState *env = &RISCV_CPU(obj)->env; 265 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 266 register_cpu_props(DEVICE(obj)); 267 set_priv_version(env, PRIV_VERSION_1_10_0); 268 } 269 270 static void rv64_sifive_e_cpu_init(Object *obj) 271 { 272 CPURISCVState *env = &RISCV_CPU(obj)->env; 273 RISCVCPU *cpu = RISCV_CPU(obj); 274 275 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 276 register_cpu_props(DEVICE(obj)); 277 set_priv_version(env, PRIV_VERSION_1_10_0); 278 cpu->cfg.mmu = false; 279 } 280 281 static void rv128_base_cpu_init(Object *obj) 282 { 283 if (qemu_tcg_mttcg_enabled()) { 284 /* Missing 128-bit aligned atomics */ 285 error_report("128-bit RISC-V currently does not work with Multi " 286 "Threaded TCG. Please use: -accel tcg,thread=single"); 287 exit(EXIT_FAILURE); 288 } 289 CPURISCVState *env = &RISCV_CPU(obj)->env; 290 /* We set this in the realise function */ 291 set_misa(env, MXL_RV128, 0); 292 register_cpu_props(DEVICE(obj)); 293 /* Set latest version of privileged specification */ 294 set_priv_version(env, PRIV_VERSION_1_12_0); 295 } 296 #else 297 static void rv32_base_cpu_init(Object *obj) 298 { 299 CPURISCVState *env = &RISCV_CPU(obj)->env; 300 /* We set this in the realise function */ 301 set_misa(env, MXL_RV32, 0); 302 register_cpu_props(DEVICE(obj)); 303 /* Set latest version of privileged specification */ 304 set_priv_version(env, PRIV_VERSION_1_12_0); 305 } 306 307 static void rv32_sifive_u_cpu_init(Object *obj) 308 { 309 CPURISCVState *env = &RISCV_CPU(obj)->env; 310 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 311 register_cpu_props(DEVICE(obj)); 312 set_priv_version(env, PRIV_VERSION_1_10_0); 313 } 314 315 static void rv32_sifive_e_cpu_init(Object *obj) 316 { 317 CPURISCVState *env = &RISCV_CPU(obj)->env; 318 RISCVCPU *cpu = RISCV_CPU(obj); 319 320 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 321 register_cpu_props(DEVICE(obj)); 322 set_priv_version(env, PRIV_VERSION_1_10_0); 323 cpu->cfg.mmu = false; 324 } 325 326 static void rv32_ibex_cpu_init(Object *obj) 327 { 328 CPURISCVState *env = &RISCV_CPU(obj)->env; 329 RISCVCPU *cpu = RISCV_CPU(obj); 330 331 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 332 register_cpu_props(DEVICE(obj)); 333 set_priv_version(env, PRIV_VERSION_1_11_0); 334 cpu->cfg.mmu = false; 335 cpu->cfg.epmp = true; 336 } 337 338 static void rv32_imafcu_nommu_cpu_init(Object *obj) 339 { 340 CPURISCVState *env = &RISCV_CPU(obj)->env; 341 RISCVCPU *cpu = RISCV_CPU(obj); 342 343 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 344 register_cpu_props(DEVICE(obj)); 345 set_priv_version(env, PRIV_VERSION_1_10_0); 346 cpu->cfg.mmu = false; 347 } 348 #endif 349 350 #if defined(CONFIG_KVM) 351 static void riscv_host_cpu_init(Object *obj) 352 { 353 CPURISCVState *env = &RISCV_CPU(obj)->env; 354 #if defined(TARGET_RISCV32) 355 set_misa(env, MXL_RV32, 0); 356 #elif defined(TARGET_RISCV64) 357 set_misa(env, MXL_RV64, 0); 358 #endif 359 register_cpu_props(DEVICE(obj)); 360 } 361 #endif 362 363 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 364 { 365 ObjectClass *oc; 366 char *typename; 367 char **cpuname; 368 369 cpuname = g_strsplit(cpu_model, ",", 1); 370 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 371 oc = object_class_by_name(typename); 372 g_strfreev(cpuname); 373 g_free(typename); 374 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 375 object_class_is_abstract(oc)) { 376 return NULL; 377 } 378 return oc; 379 } 380 381 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 382 { 383 RISCVCPU *cpu = RISCV_CPU(cs); 384 CPURISCVState *env = &cpu->env; 385 int i; 386 387 #if !defined(CONFIG_USER_ONLY) 388 if (riscv_has_ext(env, RVH)) { 389 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 390 } 391 #endif 392 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 393 #ifndef CONFIG_USER_ONLY 394 { 395 static const int dump_csrs[] = { 396 CSR_MHARTID, 397 CSR_MSTATUS, 398 CSR_MSTATUSH, 399 /* 400 * CSR_SSTATUS is intentionally omitted here as its value 401 * can be figured out by looking at CSR_MSTATUS 402 */ 403 CSR_HSTATUS, 404 CSR_VSSTATUS, 405 CSR_MIP, 406 CSR_MIE, 407 CSR_MIDELEG, 408 CSR_HIDELEG, 409 CSR_MEDELEG, 410 CSR_HEDELEG, 411 CSR_MTVEC, 412 CSR_STVEC, 413 CSR_VSTVEC, 414 CSR_MEPC, 415 CSR_SEPC, 416 CSR_VSEPC, 417 CSR_MCAUSE, 418 CSR_SCAUSE, 419 CSR_VSCAUSE, 420 CSR_MTVAL, 421 CSR_STVAL, 422 CSR_HTVAL, 423 CSR_MTVAL2, 424 CSR_MSCRATCH, 425 CSR_SSCRATCH, 426 CSR_SATP, 427 CSR_MMTE, 428 CSR_UPMBASE, 429 CSR_UPMMASK, 430 CSR_SPMBASE, 431 CSR_SPMMASK, 432 CSR_MPMBASE, 433 CSR_MPMMASK, 434 }; 435 436 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 437 int csrno = dump_csrs[i]; 438 target_ulong val = 0; 439 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 440 441 /* 442 * Rely on the smode, hmode, etc, predicates within csr.c 443 * to do the filtering of the registers that are present. 444 */ 445 if (res == RISCV_EXCP_NONE) { 446 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 447 csr_ops[csrno].name, val); 448 } 449 } 450 } 451 #endif 452 453 for (i = 0; i < 32; i++) { 454 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 455 riscv_int_regnames[i], env->gpr[i]); 456 if ((i & 3) == 3) { 457 qemu_fprintf(f, "\n"); 458 } 459 } 460 if (flags & CPU_DUMP_FPU) { 461 for (i = 0; i < 32; i++) { 462 qemu_fprintf(f, " %-8s %016" PRIx64, 463 riscv_fpr_regnames[i], env->fpr[i]); 464 if ((i & 3) == 3) { 465 qemu_fprintf(f, "\n"); 466 } 467 } 468 } 469 } 470 471 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 472 { 473 RISCVCPU *cpu = RISCV_CPU(cs); 474 CPURISCVState *env = &cpu->env; 475 476 if (env->xl == MXL_RV32) { 477 env->pc = (int32_t)value; 478 } else { 479 env->pc = value; 480 } 481 } 482 483 static vaddr riscv_cpu_get_pc(CPUState *cs) 484 { 485 RISCVCPU *cpu = RISCV_CPU(cs); 486 CPURISCVState *env = &cpu->env; 487 488 /* Match cpu_get_tb_cpu_state. */ 489 if (env->xl == MXL_RV32) { 490 return env->pc & UINT32_MAX; 491 } 492 return env->pc; 493 } 494 495 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 496 const TranslationBlock *tb) 497 { 498 RISCVCPU *cpu = RISCV_CPU(cs); 499 CPURISCVState *env = &cpu->env; 500 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 501 502 if (xl == MXL_RV32) { 503 env->pc = (int32_t)tb_pc(tb); 504 } else { 505 env->pc = tb_pc(tb); 506 } 507 } 508 509 static bool riscv_cpu_has_work(CPUState *cs) 510 { 511 #ifndef CONFIG_USER_ONLY 512 RISCVCPU *cpu = RISCV_CPU(cs); 513 CPURISCVState *env = &cpu->env; 514 /* 515 * Definition of the WFI instruction requires it to ignore the privilege 516 * mode and delegation registers, but respect individual enables 517 */ 518 return riscv_cpu_all_pending(env) != 0; 519 #else 520 return true; 521 #endif 522 } 523 524 static void riscv_restore_state_to_opc(CPUState *cs, 525 const TranslationBlock *tb, 526 const uint64_t *data) 527 { 528 RISCVCPU *cpu = RISCV_CPU(cs); 529 CPURISCVState *env = &cpu->env; 530 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 531 532 if (xl == MXL_RV32) { 533 env->pc = (int32_t)data[0]; 534 } else { 535 env->pc = data[0]; 536 } 537 env->bins = data[1]; 538 } 539 540 static void riscv_cpu_reset_hold(Object *obj) 541 { 542 #ifndef CONFIG_USER_ONLY 543 uint8_t iprio; 544 int i, irq, rdzero; 545 #endif 546 CPUState *cs = CPU(obj); 547 RISCVCPU *cpu = RISCV_CPU(cs); 548 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 549 CPURISCVState *env = &cpu->env; 550 551 if (mcc->parent_phases.hold) { 552 mcc->parent_phases.hold(obj); 553 } 554 #ifndef CONFIG_USER_ONLY 555 env->misa_mxl = env->misa_mxl_max; 556 env->priv = PRV_M; 557 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 558 if (env->misa_mxl > MXL_RV32) { 559 /* 560 * The reset status of SXL/UXL is undefined, but mstatus is WARL 561 * and we must ensure that the value after init is valid for read. 562 */ 563 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 564 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 565 if (riscv_has_ext(env, RVH)) { 566 env->vsstatus = set_field(env->vsstatus, 567 MSTATUS64_SXL, env->misa_mxl); 568 env->vsstatus = set_field(env->vsstatus, 569 MSTATUS64_UXL, env->misa_mxl); 570 env->mstatus_hs = set_field(env->mstatus_hs, 571 MSTATUS64_SXL, env->misa_mxl); 572 env->mstatus_hs = set_field(env->mstatus_hs, 573 MSTATUS64_UXL, env->misa_mxl); 574 } 575 } 576 env->mcause = 0; 577 env->miclaim = MIP_SGEIP; 578 env->pc = env->resetvec; 579 env->bins = 0; 580 env->two_stage_lookup = false; 581 582 /* Initialized default priorities of local interrupts. */ 583 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 584 iprio = riscv_cpu_default_priority(i); 585 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 586 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 587 env->hviprio[i] = 0; 588 } 589 i = 0; 590 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 591 if (!rdzero) { 592 env->hviprio[irq] = env->miprio[irq]; 593 } 594 i++; 595 } 596 /* mmte is supposed to have pm.current hardwired to 1 */ 597 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 598 #endif 599 env->xl = riscv_cpu_mxl(env); 600 riscv_cpu_update_mask(env); 601 cs->exception_index = RISCV_EXCP_NONE; 602 env->load_res = -1; 603 set_default_nan_mode(1, &env->fp_status); 604 605 #ifndef CONFIG_USER_ONLY 606 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 607 riscv_trigger_init(env); 608 } 609 610 if (kvm_enabled()) { 611 kvm_riscv_reset_vcpu(cpu); 612 } 613 #endif 614 } 615 616 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 617 { 618 RISCVCPU *cpu = RISCV_CPU(s); 619 620 switch (riscv_cpu_mxl(&cpu->env)) { 621 case MXL_RV32: 622 info->print_insn = print_insn_riscv32; 623 break; 624 case MXL_RV64: 625 info->print_insn = print_insn_riscv64; 626 break; 627 case MXL_RV128: 628 info->print_insn = print_insn_riscv128; 629 break; 630 default: 631 g_assert_not_reached(); 632 } 633 } 634 635 /* 636 * Check consistency between chosen extensions while setting 637 * cpu->cfg accordingly, doing a set_misa() in the end. 638 */ 639 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 640 { 641 CPURISCVState *env = &cpu->env; 642 uint32_t ext = 0; 643 644 /* Do some ISA extension error checking */ 645 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 646 cpu->cfg.ext_a && cpu->cfg.ext_f && 647 cpu->cfg.ext_d && 648 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 649 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 650 cpu->cfg.ext_i = true; 651 cpu->cfg.ext_m = true; 652 cpu->cfg.ext_a = true; 653 cpu->cfg.ext_f = true; 654 cpu->cfg.ext_d = true; 655 cpu->cfg.ext_icsr = true; 656 cpu->cfg.ext_ifencei = true; 657 } 658 659 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 660 error_setg(errp, 661 "I and E extensions are incompatible"); 662 return; 663 } 664 665 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 666 error_setg(errp, 667 "Either I or E extension must be set"); 668 return; 669 } 670 671 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 672 error_setg(errp, 673 "Setting S extension without U extension is illegal"); 674 return; 675 } 676 677 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { 678 error_setg(errp, 679 "H depends on an I base integer ISA with 32 x registers"); 680 return; 681 } 682 683 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 684 error_setg(errp, "H extension implicitly requires S-mode"); 685 return; 686 } 687 688 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 689 error_setg(errp, "F extension requires Zicsr"); 690 return; 691 } 692 693 if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { 694 error_setg(errp, "Zawrs extension requires A extension"); 695 return; 696 } 697 698 if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { 699 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 700 return; 701 } 702 703 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 704 error_setg(errp, "D extension requires F extension"); 705 return; 706 } 707 708 if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { 709 error_setg(errp, "V extension requires D extension"); 710 return; 711 } 712 713 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 714 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 715 return; 716 } 717 718 /* Set the ISA extensions, checks should have happened above */ 719 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || 720 cpu->cfg.ext_zhinxmin) { 721 cpu->cfg.ext_zfinx = true; 722 } 723 724 if (cpu->cfg.ext_zfinx) { 725 if (!cpu->cfg.ext_icsr) { 726 error_setg(errp, "Zfinx extension requires Zicsr"); 727 return; 728 } 729 if (cpu->cfg.ext_f) { 730 error_setg(errp, 731 "Zfinx cannot be supported together with F extension"); 732 return; 733 } 734 } 735 736 if (cpu->cfg.ext_zk) { 737 cpu->cfg.ext_zkn = true; 738 cpu->cfg.ext_zkr = true; 739 cpu->cfg.ext_zkt = true; 740 } 741 742 if (cpu->cfg.ext_zkn) { 743 cpu->cfg.ext_zbkb = true; 744 cpu->cfg.ext_zbkc = true; 745 cpu->cfg.ext_zbkx = true; 746 cpu->cfg.ext_zkne = true; 747 cpu->cfg.ext_zknd = true; 748 cpu->cfg.ext_zknh = true; 749 } 750 751 if (cpu->cfg.ext_zks) { 752 cpu->cfg.ext_zbkb = true; 753 cpu->cfg.ext_zbkc = true; 754 cpu->cfg.ext_zbkx = true; 755 cpu->cfg.ext_zksed = true; 756 cpu->cfg.ext_zksh = true; 757 } 758 759 if (cpu->cfg.ext_i) { 760 ext |= RVI; 761 } 762 if (cpu->cfg.ext_e) { 763 ext |= RVE; 764 } 765 if (cpu->cfg.ext_m) { 766 ext |= RVM; 767 } 768 if (cpu->cfg.ext_a) { 769 ext |= RVA; 770 } 771 if (cpu->cfg.ext_f) { 772 ext |= RVF; 773 } 774 if (cpu->cfg.ext_d) { 775 ext |= RVD; 776 } 777 if (cpu->cfg.ext_c) { 778 ext |= RVC; 779 } 780 if (cpu->cfg.ext_s) { 781 ext |= RVS; 782 } 783 if (cpu->cfg.ext_u) { 784 ext |= RVU; 785 } 786 if (cpu->cfg.ext_h) { 787 ext |= RVH; 788 } 789 if (cpu->cfg.ext_v) { 790 int vext_version = VEXT_VERSION_1_00_0; 791 ext |= RVV; 792 if (!is_power_of_2(cpu->cfg.vlen)) { 793 error_setg(errp, 794 "Vector extension VLEN must be power of 2"); 795 return; 796 } 797 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 798 error_setg(errp, 799 "Vector extension implementation only supports VLEN " 800 "in the range [128, %d]", RV_VLEN_MAX); 801 return; 802 } 803 if (!is_power_of_2(cpu->cfg.elen)) { 804 error_setg(errp, 805 "Vector extension ELEN must be power of 2"); 806 return; 807 } 808 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 809 error_setg(errp, 810 "Vector extension implementation only supports ELEN " 811 "in the range [8, 64]"); 812 return; 813 } 814 if (cpu->cfg.vext_spec) { 815 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 816 vext_version = VEXT_VERSION_1_00_0; 817 } else { 818 error_setg(errp, 819 "Unsupported vector spec version '%s'", 820 cpu->cfg.vext_spec); 821 return; 822 } 823 } else { 824 qemu_log("vector version is not specified, " 825 "use the default value v1.0\n"); 826 } 827 set_vext_version(env, vext_version); 828 } 829 if (cpu->cfg.ext_j) { 830 ext |= RVJ; 831 } 832 833 set_misa(env, env->misa_mxl, ext); 834 } 835 836 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 837 { 838 CPUState *cs = CPU(dev); 839 RISCVCPU *cpu = RISCV_CPU(dev); 840 CPURISCVState *env = &cpu->env; 841 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 842 CPUClass *cc = CPU_CLASS(mcc); 843 int i, priv_version = -1; 844 Error *local_err = NULL; 845 846 cpu_exec_realizefn(cs, &local_err); 847 if (local_err != NULL) { 848 error_propagate(errp, local_err); 849 return; 850 } 851 852 if (cpu->cfg.priv_spec) { 853 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 854 priv_version = PRIV_VERSION_1_12_0; 855 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 856 priv_version = PRIV_VERSION_1_11_0; 857 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 858 priv_version = PRIV_VERSION_1_10_0; 859 } else { 860 error_setg(errp, 861 "Unsupported privilege spec version '%s'", 862 cpu->cfg.priv_spec); 863 return; 864 } 865 } 866 867 if (priv_version >= PRIV_VERSION_1_10_0) { 868 set_priv_version(env, priv_version); 869 } 870 871 /* Force disable extensions if priv spec version does not match */ 872 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 873 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 874 (env->priv_ver < isa_edata_arr[i].min_version)) { 875 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 876 #ifndef CONFIG_USER_ONLY 877 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 878 " because privilege spec version does not match", 879 isa_edata_arr[i].name, env->mhartid); 880 #else 881 warn_report("disabling %s extension because " 882 "privilege spec version does not match", 883 isa_edata_arr[i].name); 884 #endif 885 } 886 } 887 888 if (cpu->cfg.mmu) { 889 riscv_set_feature(env, RISCV_FEATURE_MMU); 890 } 891 892 if (cpu->cfg.pmp) { 893 riscv_set_feature(env, RISCV_FEATURE_PMP); 894 895 /* 896 * Enhanced PMP should only be available 897 * on harts with PMP support 898 */ 899 if (cpu->cfg.epmp) { 900 riscv_set_feature(env, RISCV_FEATURE_EPMP); 901 } 902 } 903 904 if (cpu->cfg.debug) { 905 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 906 } 907 908 909 #ifndef CONFIG_USER_ONLY 910 if (cpu->cfg.ext_sstc) { 911 riscv_timer_init(cpu); 912 } 913 #endif /* CONFIG_USER_ONLY */ 914 915 /* Validate that MISA_MXL is set properly. */ 916 switch (env->misa_mxl_max) { 917 #ifdef TARGET_RISCV64 918 case MXL_RV64: 919 case MXL_RV128: 920 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 921 break; 922 #endif 923 case MXL_RV32: 924 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 925 break; 926 default: 927 g_assert_not_reached(); 928 } 929 assert(env->misa_mxl_max == env->misa_mxl); 930 931 riscv_cpu_validate_set_extensions(cpu, &local_err); 932 if (local_err != NULL) { 933 error_propagate(errp, local_err); 934 return; 935 } 936 937 #ifndef CONFIG_USER_ONLY 938 if (cpu->cfg.pmu_num) { 939 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 940 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 941 riscv_pmu_timer_cb, cpu); 942 } 943 } 944 #endif 945 946 riscv_cpu_register_gdb_regs_for_features(cs); 947 948 qemu_init_vcpu(cs); 949 cpu_reset(cs); 950 951 mcc->parent_realize(dev, errp); 952 } 953 954 #ifndef CONFIG_USER_ONLY 955 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 956 { 957 RISCVCPU *cpu = RISCV_CPU(opaque); 958 CPURISCVState *env = &cpu->env; 959 960 if (irq < IRQ_LOCAL_MAX) { 961 switch (irq) { 962 case IRQ_U_SOFT: 963 case IRQ_S_SOFT: 964 case IRQ_VS_SOFT: 965 case IRQ_M_SOFT: 966 case IRQ_U_TIMER: 967 case IRQ_S_TIMER: 968 case IRQ_VS_TIMER: 969 case IRQ_M_TIMER: 970 case IRQ_U_EXT: 971 case IRQ_VS_EXT: 972 case IRQ_M_EXT: 973 if (kvm_enabled()) { 974 kvm_riscv_set_irq(cpu, irq, level); 975 } else { 976 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 977 } 978 break; 979 case IRQ_S_EXT: 980 if (kvm_enabled()) { 981 kvm_riscv_set_irq(cpu, irq, level); 982 } else { 983 env->external_seip = level; 984 riscv_cpu_update_mip(cpu, 1 << irq, 985 BOOL_TO_MASK(level | env->software_seip)); 986 } 987 break; 988 default: 989 g_assert_not_reached(); 990 } 991 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 992 /* Require H-extension for handling guest local interrupts */ 993 if (!riscv_has_ext(env, RVH)) { 994 g_assert_not_reached(); 995 } 996 997 /* Compute bit position in HGEIP CSR */ 998 irq = irq - IRQ_LOCAL_MAX + 1; 999 if (env->geilen < irq) { 1000 g_assert_not_reached(); 1001 } 1002 1003 /* Update HGEIP CSR */ 1004 env->hgeip &= ~((target_ulong)1 << irq); 1005 if (level) { 1006 env->hgeip |= (target_ulong)1 << irq; 1007 } 1008 1009 /* Update mip.SGEIP bit */ 1010 riscv_cpu_update_mip(cpu, MIP_SGEIP, 1011 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1012 } else { 1013 g_assert_not_reached(); 1014 } 1015 } 1016 #endif /* CONFIG_USER_ONLY */ 1017 1018 static void riscv_cpu_init(Object *obj) 1019 { 1020 RISCVCPU *cpu = RISCV_CPU(obj); 1021 1022 cpu->cfg.ext_ifencei = true; 1023 cpu->cfg.ext_icsr = true; 1024 cpu->cfg.mmu = true; 1025 cpu->cfg.pmp = true; 1026 1027 cpu_set_cpustate_pointers(cpu); 1028 1029 #ifndef CONFIG_USER_ONLY 1030 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1031 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1032 #endif /* CONFIG_USER_ONLY */ 1033 } 1034 1035 static Property riscv_cpu_extensions[] = { 1036 /* Defaults for standard extensions */ 1037 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 1038 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 1039 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1040 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 1041 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 1042 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 1043 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 1044 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 1045 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 1046 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1047 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1048 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1049 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1050 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1051 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1052 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1053 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1054 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1055 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1056 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1057 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1058 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1059 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1060 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1061 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1062 1063 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1064 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1065 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1066 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1067 1068 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1069 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1070 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1071 1072 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1073 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1074 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1075 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1076 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1077 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1078 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1079 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1080 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1081 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1082 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1083 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1084 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1085 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1086 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1087 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1088 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1089 1090 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1091 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1092 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1093 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1094 1095 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1096 1097 /* Vendor-specific custom extensions */ 1098 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1099 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1100 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1101 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1102 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1103 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1104 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1105 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1106 1107 /* These are experimental so mark with 'x-' */ 1108 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1109 /* ePMP 0.9.3 */ 1110 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1111 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1112 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1113 1114 DEFINE_PROP_END_OF_LIST(), 1115 }; 1116 1117 /* 1118 * Register CPU props based on env.misa_ext. If a non-zero 1119 * value was set, register only the required cpu->cfg.ext_* 1120 * properties and leave. env.misa_ext = 0 means that we want 1121 * all the default properties to be registered. 1122 */ 1123 static void register_cpu_props(DeviceState *dev) 1124 { 1125 RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); 1126 uint32_t misa_ext = cpu->env.misa_ext; 1127 Property *prop; 1128 1129 /* 1130 * If misa_ext is not zero, set cfg properties now to 1131 * allow them to be read during riscv_cpu_realize() 1132 * later on. 1133 */ 1134 if (cpu->env.misa_ext != 0) { 1135 cpu->cfg.ext_i = misa_ext & RVI; 1136 cpu->cfg.ext_e = misa_ext & RVE; 1137 cpu->cfg.ext_m = misa_ext & RVM; 1138 cpu->cfg.ext_a = misa_ext & RVA; 1139 cpu->cfg.ext_f = misa_ext & RVF; 1140 cpu->cfg.ext_d = misa_ext & RVD; 1141 cpu->cfg.ext_v = misa_ext & RVV; 1142 cpu->cfg.ext_c = misa_ext & RVC; 1143 cpu->cfg.ext_s = misa_ext & RVS; 1144 cpu->cfg.ext_u = misa_ext & RVU; 1145 cpu->cfg.ext_h = misa_ext & RVH; 1146 cpu->cfg.ext_j = misa_ext & RVJ; 1147 1148 /* 1149 * We don't want to set the default riscv_cpu_extensions 1150 * in this case. 1151 */ 1152 return; 1153 } 1154 1155 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1156 qdev_property_add_static(dev, prop); 1157 } 1158 } 1159 1160 static Property riscv_cpu_properties[] = { 1161 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1162 1163 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1164 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1165 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1166 1167 #ifndef CONFIG_USER_ONLY 1168 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1169 #endif 1170 1171 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1172 1173 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1174 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1175 DEFINE_PROP_END_OF_LIST(), 1176 }; 1177 1178 static gchar *riscv_gdb_arch_name(CPUState *cs) 1179 { 1180 RISCVCPU *cpu = RISCV_CPU(cs); 1181 CPURISCVState *env = &cpu->env; 1182 1183 switch (riscv_cpu_mxl(env)) { 1184 case MXL_RV32: 1185 return g_strdup("riscv:rv32"); 1186 case MXL_RV64: 1187 case MXL_RV128: 1188 return g_strdup("riscv:rv64"); 1189 default: 1190 g_assert_not_reached(); 1191 } 1192 } 1193 1194 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1195 { 1196 RISCVCPU *cpu = RISCV_CPU(cs); 1197 1198 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1199 return cpu->dyn_csr_xml; 1200 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1201 return cpu->dyn_vreg_xml; 1202 } 1203 1204 return NULL; 1205 } 1206 1207 #ifndef CONFIG_USER_ONLY 1208 #include "hw/core/sysemu-cpu-ops.h" 1209 1210 static const struct SysemuCPUOps riscv_sysemu_ops = { 1211 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1212 .write_elf64_note = riscv_cpu_write_elf64_note, 1213 .write_elf32_note = riscv_cpu_write_elf32_note, 1214 .legacy_vmsd = &vmstate_riscv_cpu, 1215 }; 1216 #endif 1217 1218 #include "hw/core/tcg-cpu-ops.h" 1219 1220 static const struct TCGCPUOps riscv_tcg_ops = { 1221 .initialize = riscv_translate_init, 1222 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1223 .restore_state_to_opc = riscv_restore_state_to_opc, 1224 1225 #ifndef CONFIG_USER_ONLY 1226 .tlb_fill = riscv_cpu_tlb_fill, 1227 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1228 .do_interrupt = riscv_cpu_do_interrupt, 1229 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1230 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1231 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1232 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1233 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1234 #endif /* !CONFIG_USER_ONLY */ 1235 }; 1236 1237 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1238 { 1239 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1240 CPUClass *cc = CPU_CLASS(c); 1241 DeviceClass *dc = DEVICE_CLASS(c); 1242 ResettableClass *rc = RESETTABLE_CLASS(c); 1243 1244 device_class_set_parent_realize(dc, riscv_cpu_realize, 1245 &mcc->parent_realize); 1246 1247 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1248 &mcc->parent_phases); 1249 1250 cc->class_by_name = riscv_cpu_class_by_name; 1251 cc->has_work = riscv_cpu_has_work; 1252 cc->dump_state = riscv_cpu_dump_state; 1253 cc->set_pc = riscv_cpu_set_pc; 1254 cc->get_pc = riscv_cpu_get_pc; 1255 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1256 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1257 cc->gdb_num_core_regs = 33; 1258 cc->gdb_stop_before_watchpoint = true; 1259 cc->disas_set_info = riscv_cpu_disas_set_info; 1260 #ifndef CONFIG_USER_ONLY 1261 cc->sysemu_ops = &riscv_sysemu_ops; 1262 #endif 1263 cc->gdb_arch_name = riscv_gdb_arch_name; 1264 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1265 cc->tcg_ops = &riscv_tcg_ops; 1266 1267 device_class_set_props(dc, riscv_cpu_properties); 1268 } 1269 1270 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1271 { 1272 char *old = *isa_str; 1273 char *new = *isa_str; 1274 int i; 1275 1276 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1277 if (isa_edata_arr[i].multi_letter && 1278 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1279 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1280 g_free(old); 1281 old = new; 1282 } 1283 } 1284 1285 *isa_str = new; 1286 } 1287 1288 char *riscv_isa_string(RISCVCPU *cpu) 1289 { 1290 int i; 1291 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1292 char *isa_str = g_new(char, maxlen); 1293 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1294 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1295 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1296 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1297 } 1298 } 1299 *p = '\0'; 1300 if (!cpu->cfg.short_isa_string) { 1301 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1302 } 1303 return isa_str; 1304 } 1305 1306 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1307 { 1308 ObjectClass *class_a = (ObjectClass *)a; 1309 ObjectClass *class_b = (ObjectClass *)b; 1310 const char *name_a, *name_b; 1311 1312 name_a = object_class_get_name(class_a); 1313 name_b = object_class_get_name(class_b); 1314 return strcmp(name_a, name_b); 1315 } 1316 1317 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1318 { 1319 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1320 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1321 1322 qemu_printf("%.*s\n", len, typename); 1323 } 1324 1325 void riscv_cpu_list(void) 1326 { 1327 GSList *list; 1328 1329 list = object_class_get_list(TYPE_RISCV_CPU, false); 1330 list = g_slist_sort(list, riscv_cpu_list_compare); 1331 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1332 g_slist_free(list); 1333 } 1334 1335 #define DEFINE_CPU(type_name, initfn) \ 1336 { \ 1337 .name = type_name, \ 1338 .parent = TYPE_RISCV_CPU, \ 1339 .instance_init = initfn \ 1340 } 1341 1342 static const TypeInfo riscv_cpu_type_infos[] = { 1343 { 1344 .name = TYPE_RISCV_CPU, 1345 .parent = TYPE_CPU, 1346 .instance_size = sizeof(RISCVCPU), 1347 .instance_align = __alignof__(RISCVCPU), 1348 .instance_init = riscv_cpu_init, 1349 .abstract = true, 1350 .class_size = sizeof(RISCVCPUClass), 1351 .class_init = riscv_cpu_class_init, 1352 }, 1353 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1354 #if defined(CONFIG_KVM) 1355 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1356 #endif 1357 #if defined(TARGET_RISCV32) 1358 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1359 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1360 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1361 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1362 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1363 #elif defined(TARGET_RISCV64) 1364 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1365 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1366 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1367 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1368 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1369 #endif 1370 }; 1371 1372 DEFINE_TYPES(riscv_cpu_type_infos) 1373