1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "exec/exec-all.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 #include "fpu/softfloat-helpers.h" 31 32 /* RISC-V CPU definitions */ 33 34 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 35 36 const char * const riscv_int_regnames[] = { 37 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 38 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 39 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 40 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 41 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 42 }; 43 44 const char * const riscv_fpr_regnames[] = { 45 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 46 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 47 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 48 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 49 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 50 "f30/ft10", "f31/ft11" 51 }; 52 53 const char * const riscv_excp_names[] = { 54 "misaligned_fetch", 55 "fault_fetch", 56 "illegal_instruction", 57 "breakpoint", 58 "misaligned_load", 59 "fault_load", 60 "misaligned_store", 61 "fault_store", 62 "user_ecall", 63 "supervisor_ecall", 64 "hypervisor_ecall", 65 "machine_ecall", 66 "exec_page_fault", 67 "load_page_fault", 68 "reserved", 69 "store_page_fault", 70 "reserved", 71 "reserved", 72 "reserved", 73 "reserved", 74 "guest_exec_page_fault", 75 "guest_load_page_fault", 76 "reserved", 77 "guest_store_page_fault", 78 }; 79 80 const char * const riscv_intr_names[] = { 81 "u_software", 82 "s_software", 83 "vs_software", 84 "m_software", 85 "u_timer", 86 "s_timer", 87 "vs_timer", 88 "m_timer", 89 "u_external", 90 "vs_external", 91 "h_external", 92 "m_external", 93 "reserved", 94 "reserved", 95 "reserved", 96 "reserved" 97 }; 98 99 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 100 { 101 if (async) { 102 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 103 riscv_intr_names[cause] : "(unknown)"; 104 } else { 105 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 106 riscv_excp_names[cause] : "(unknown)"; 107 } 108 } 109 110 static void set_misa(CPURISCVState *env, target_ulong misa) 111 { 112 env->misa_mask = env->misa = misa; 113 } 114 115 static void set_priv_version(CPURISCVState *env, int priv_ver) 116 { 117 env->priv_ver = priv_ver; 118 } 119 120 static void set_vext_version(CPURISCVState *env, int vext_ver) 121 { 122 env->vext_ver = vext_ver; 123 } 124 125 static void set_feature(CPURISCVState *env, int feature) 126 { 127 env->features |= (1ULL << feature); 128 } 129 130 static void set_resetvec(CPURISCVState *env, int resetvec) 131 { 132 #ifndef CONFIG_USER_ONLY 133 env->resetvec = resetvec; 134 #endif 135 } 136 137 static void riscv_any_cpu_init(Object *obj) 138 { 139 CPURISCVState *env = &RISCV_CPU(obj)->env; 140 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); 141 set_priv_version(env, PRIV_VERSION_1_11_0); 142 set_resetvec(env, DEFAULT_RSTVEC); 143 } 144 145 static void riscv_base_cpu_init(Object *obj) 146 { 147 CPURISCVState *env = &RISCV_CPU(obj)->env; 148 /* We set this in the realise function */ 149 set_misa(env, 0); 150 set_resetvec(env, DEFAULT_RSTVEC); 151 } 152 153 static void rvxx_sifive_u_cpu_init(Object *obj) 154 { 155 CPURISCVState *env = &RISCV_CPU(obj)->env; 156 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 157 set_priv_version(env, PRIV_VERSION_1_10_0); 158 set_resetvec(env, 0x1004); 159 } 160 161 static void rvxx_sifive_e_cpu_init(Object *obj) 162 { 163 CPURISCVState *env = &RISCV_CPU(obj)->env; 164 set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU); 165 set_priv_version(env, PRIV_VERSION_1_10_0); 166 set_resetvec(env, 0x1004); 167 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 168 } 169 170 #if defined(TARGET_RISCV32) 171 172 static void rv32_ibex_cpu_init(Object *obj) 173 { 174 CPURISCVState *env = &RISCV_CPU(obj)->env; 175 set_misa(env, RV32 | RVI | RVM | RVC | RVU); 176 set_priv_version(env, PRIV_VERSION_1_10_0); 177 set_resetvec(env, 0x8090); 178 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 179 } 180 181 static void rv32_imafcu_nommu_cpu_init(Object *obj) 182 { 183 CPURISCVState *env = &RISCV_CPU(obj)->env; 184 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); 185 set_priv_version(env, PRIV_VERSION_1_10_0); 186 set_resetvec(env, DEFAULT_RSTVEC); 187 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 188 } 189 190 #endif 191 192 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 193 { 194 ObjectClass *oc; 195 char *typename; 196 char **cpuname; 197 198 cpuname = g_strsplit(cpu_model, ",", 1); 199 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 200 oc = object_class_by_name(typename); 201 g_strfreev(cpuname); 202 g_free(typename); 203 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 204 object_class_is_abstract(oc)) { 205 return NULL; 206 } 207 return oc; 208 } 209 210 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 211 { 212 RISCVCPU *cpu = RISCV_CPU(cs); 213 CPURISCVState *env = &cpu->env; 214 int i; 215 216 #if !defined(CONFIG_USER_ONLY) 217 if (riscv_has_ext(env, RVH)) { 218 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 219 } 220 #endif 221 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 222 #ifndef CONFIG_USER_ONLY 223 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); 224 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); 225 #ifdef TARGET_RISCV32 226 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush); 227 #endif 228 if (riscv_has_ext(env, RVH)) { 229 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); 230 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus); 231 } 232 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); 233 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); 234 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); 235 if (riscv_has_ext(env, RVH)) { 236 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); 237 } 238 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); 239 if (riscv_has_ext(env, RVH)) { 240 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); 241 } 242 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); 243 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); 244 if (riscv_has_ext(env, RVH)) { 245 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); 246 } 247 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); 248 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); 249 if (riscv_has_ext(env, RVH)) { 250 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); 251 } 252 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); 253 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); 254 if (riscv_has_ext(env, RVH)) { 255 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); 256 } 257 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); 258 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr); 259 if (riscv_has_ext(env, RVH)) { 260 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); 261 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); 262 } 263 #endif 264 265 for (i = 0; i < 32; i++) { 266 qemu_fprintf(f, " %s " TARGET_FMT_lx, 267 riscv_int_regnames[i], env->gpr[i]); 268 if ((i & 3) == 3) { 269 qemu_fprintf(f, "\n"); 270 } 271 } 272 if (flags & CPU_DUMP_FPU) { 273 for (i = 0; i < 32; i++) { 274 qemu_fprintf(f, " %s %016" PRIx64, 275 riscv_fpr_regnames[i], env->fpr[i]); 276 if ((i & 3) == 3) { 277 qemu_fprintf(f, "\n"); 278 } 279 } 280 } 281 } 282 283 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 284 { 285 RISCVCPU *cpu = RISCV_CPU(cs); 286 CPURISCVState *env = &cpu->env; 287 env->pc = value; 288 } 289 290 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 291 { 292 RISCVCPU *cpu = RISCV_CPU(cs); 293 CPURISCVState *env = &cpu->env; 294 env->pc = tb->pc; 295 } 296 297 static bool riscv_cpu_has_work(CPUState *cs) 298 { 299 #ifndef CONFIG_USER_ONLY 300 RISCVCPU *cpu = RISCV_CPU(cs); 301 CPURISCVState *env = &cpu->env; 302 /* 303 * Definition of the WFI instruction requires it to ignore the privilege 304 * mode and delegation registers, but respect individual enables 305 */ 306 return (env->mip & env->mie) != 0; 307 #else 308 return true; 309 #endif 310 } 311 312 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 313 target_ulong *data) 314 { 315 env->pc = data[0]; 316 } 317 318 static void riscv_cpu_reset(DeviceState *dev) 319 { 320 CPUState *cs = CPU(dev); 321 RISCVCPU *cpu = RISCV_CPU(cs); 322 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 323 CPURISCVState *env = &cpu->env; 324 325 mcc->parent_reset(dev); 326 #ifndef CONFIG_USER_ONLY 327 env->priv = PRV_M; 328 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 329 env->mcause = 0; 330 env->pc = env->resetvec; 331 #endif 332 cs->exception_index = EXCP_NONE; 333 env->load_res = -1; 334 set_default_nan_mode(1, &env->fp_status); 335 } 336 337 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 338 { 339 #if defined(TARGET_RISCV32) 340 info->print_insn = print_insn_riscv32; 341 #elif defined(TARGET_RISCV64) 342 info->print_insn = print_insn_riscv64; 343 #endif 344 } 345 346 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 347 { 348 CPUState *cs = CPU(dev); 349 RISCVCPU *cpu = RISCV_CPU(dev); 350 CPURISCVState *env = &cpu->env; 351 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 352 int priv_version = PRIV_VERSION_1_11_0; 353 int vext_version = VEXT_VERSION_0_07_1; 354 target_ulong target_misa = 0; 355 Error *local_err = NULL; 356 357 cpu_exec_realizefn(cs, &local_err); 358 if (local_err != NULL) { 359 error_propagate(errp, local_err); 360 return; 361 } 362 363 if (cpu->cfg.priv_spec) { 364 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 365 priv_version = PRIV_VERSION_1_11_0; 366 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 367 priv_version = PRIV_VERSION_1_10_0; 368 } else { 369 error_setg(errp, 370 "Unsupported privilege spec version '%s'", 371 cpu->cfg.priv_spec); 372 return; 373 } 374 } 375 376 set_priv_version(env, priv_version); 377 set_vext_version(env, vext_version); 378 379 if (cpu->cfg.mmu) { 380 set_feature(env, RISCV_FEATURE_MMU); 381 } 382 383 if (cpu->cfg.pmp) { 384 set_feature(env, RISCV_FEATURE_PMP); 385 } 386 387 /* If misa isn't set (rv32 and rv64 machines) set it here */ 388 if (!env->misa) { 389 /* Do some ISA extension error checking */ 390 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 391 error_setg(errp, 392 "I and E extensions are incompatible"); 393 return; 394 } 395 396 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 397 error_setg(errp, 398 "Either I or E extension must be set"); 399 return; 400 } 401 402 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 403 cpu->cfg.ext_a & cpu->cfg.ext_f & 404 cpu->cfg.ext_d)) { 405 warn_report("Setting G will also set IMAFD"); 406 cpu->cfg.ext_i = true; 407 cpu->cfg.ext_m = true; 408 cpu->cfg.ext_a = true; 409 cpu->cfg.ext_f = true; 410 cpu->cfg.ext_d = true; 411 } 412 413 /* Set the ISA extensions, checks should have happened above */ 414 if (cpu->cfg.ext_i) { 415 target_misa |= RVI; 416 } 417 if (cpu->cfg.ext_e) { 418 target_misa |= RVE; 419 } 420 if (cpu->cfg.ext_m) { 421 target_misa |= RVM; 422 } 423 if (cpu->cfg.ext_a) { 424 target_misa |= RVA; 425 } 426 if (cpu->cfg.ext_f) { 427 target_misa |= RVF; 428 } 429 if (cpu->cfg.ext_d) { 430 target_misa |= RVD; 431 } 432 if (cpu->cfg.ext_c) { 433 target_misa |= RVC; 434 } 435 if (cpu->cfg.ext_s) { 436 target_misa |= RVS; 437 } 438 if (cpu->cfg.ext_u) { 439 target_misa |= RVU; 440 } 441 if (cpu->cfg.ext_h) { 442 target_misa |= RVH; 443 } 444 if (cpu->cfg.ext_v) { 445 target_misa |= RVV; 446 if (!is_power_of_2(cpu->cfg.vlen)) { 447 error_setg(errp, 448 "Vector extension VLEN must be power of 2"); 449 return; 450 } 451 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 452 error_setg(errp, 453 "Vector extension implementation only supports VLEN " 454 "in the range [128, %d]", RV_VLEN_MAX); 455 return; 456 } 457 if (!is_power_of_2(cpu->cfg.elen)) { 458 error_setg(errp, 459 "Vector extension ELEN must be power of 2"); 460 return; 461 } 462 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 463 error_setg(errp, 464 "Vector extension implementation only supports ELEN " 465 "in the range [8, 64]"); 466 return; 467 } 468 if (cpu->cfg.vext_spec) { 469 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { 470 vext_version = VEXT_VERSION_0_07_1; 471 } else { 472 error_setg(errp, 473 "Unsupported vector spec version '%s'", 474 cpu->cfg.vext_spec); 475 return; 476 } 477 } else { 478 qemu_log("vector verison is not specified, " 479 "use the default value v0.7.1\n"); 480 } 481 set_vext_version(env, vext_version); 482 } 483 484 set_misa(env, RVXLEN | target_misa); 485 } 486 487 riscv_cpu_register_gdb_regs_for_features(cs); 488 489 qemu_init_vcpu(cs); 490 cpu_reset(cs); 491 492 mcc->parent_realize(dev, errp); 493 } 494 495 static void riscv_cpu_init(Object *obj) 496 { 497 RISCVCPU *cpu = RISCV_CPU(obj); 498 499 cpu_set_cpustate_pointers(cpu); 500 } 501 502 #ifndef CONFIG_USER_ONLY 503 static const VMStateDescription vmstate_riscv_cpu = { 504 .name = "cpu", 505 .unmigratable = 1, 506 }; 507 #endif 508 509 static Property riscv_cpu_properties[] = { 510 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 511 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 512 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 513 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 514 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 515 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 516 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 517 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 518 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 519 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 520 /* This is experimental so mark with 'x-' */ 521 DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), 522 DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), 523 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 524 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 525 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 526 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 527 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 528 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 529 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 530 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 531 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 532 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 533 DEFINE_PROP_END_OF_LIST(), 534 }; 535 536 static void riscv_cpu_class_init(ObjectClass *c, void *data) 537 { 538 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 539 CPUClass *cc = CPU_CLASS(c); 540 DeviceClass *dc = DEVICE_CLASS(c); 541 542 device_class_set_parent_realize(dc, riscv_cpu_realize, 543 &mcc->parent_realize); 544 545 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 546 547 cc->class_by_name = riscv_cpu_class_by_name; 548 cc->has_work = riscv_cpu_has_work; 549 cc->do_interrupt = riscv_cpu_do_interrupt; 550 cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt; 551 cc->dump_state = riscv_cpu_dump_state; 552 cc->set_pc = riscv_cpu_set_pc; 553 cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb; 554 cc->gdb_read_register = riscv_cpu_gdb_read_register; 555 cc->gdb_write_register = riscv_cpu_gdb_write_register; 556 cc->gdb_num_core_regs = 33; 557 #if defined(TARGET_RISCV32) 558 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 559 #elif defined(TARGET_RISCV64) 560 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 561 #endif 562 cc->gdb_stop_before_watchpoint = true; 563 cc->disas_set_info = riscv_cpu_disas_set_info; 564 #ifndef CONFIG_USER_ONLY 565 cc->do_transaction_failed = riscv_cpu_do_transaction_failed; 566 cc->do_unaligned_access = riscv_cpu_do_unaligned_access; 567 cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; 568 /* For now, mark unmigratable: */ 569 cc->vmsd = &vmstate_riscv_cpu; 570 #endif 571 #ifdef CONFIG_TCG 572 cc->tcg_initialize = riscv_translate_init; 573 cc->tlb_fill = riscv_cpu_tlb_fill; 574 #endif 575 device_class_set_props(dc, riscv_cpu_properties); 576 } 577 578 char *riscv_isa_string(RISCVCPU *cpu) 579 { 580 int i; 581 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 582 char *isa_str = g_new(char, maxlen); 583 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 584 for (i = 0; i < sizeof(riscv_exts); i++) { 585 if (cpu->env.misa & RV(riscv_exts[i])) { 586 *p++ = qemu_tolower(riscv_exts[i]); 587 } 588 } 589 *p = '\0'; 590 return isa_str; 591 } 592 593 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 594 { 595 ObjectClass *class_a = (ObjectClass *)a; 596 ObjectClass *class_b = (ObjectClass *)b; 597 const char *name_a, *name_b; 598 599 name_a = object_class_get_name(class_a); 600 name_b = object_class_get_name(class_b); 601 return strcmp(name_a, name_b); 602 } 603 604 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 605 { 606 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 607 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 608 609 qemu_printf("%.*s\n", len, typename); 610 } 611 612 void riscv_cpu_list(void) 613 { 614 GSList *list; 615 616 list = object_class_get_list(TYPE_RISCV_CPU, false); 617 list = g_slist_sort(list, riscv_cpu_list_compare); 618 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 619 g_slist_free(list); 620 } 621 622 #define DEFINE_CPU(type_name, initfn) \ 623 { \ 624 .name = type_name, \ 625 .parent = TYPE_RISCV_CPU, \ 626 .instance_init = initfn \ 627 } 628 629 static const TypeInfo riscv_cpu_type_infos[] = { 630 { 631 .name = TYPE_RISCV_CPU, 632 .parent = TYPE_CPU, 633 .instance_size = sizeof(RISCVCPU), 634 .instance_init = riscv_cpu_init, 635 .abstract = true, 636 .class_size = sizeof(RISCVCPUClass), 637 .class_init = riscv_cpu_class_init, 638 }, 639 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 640 #if defined(TARGET_RISCV32) 641 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init), 642 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 643 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init), 644 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 645 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init), 646 #elif defined(TARGET_RISCV64) 647 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), 648 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init), 649 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init), 650 #endif 651 }; 652 653 DEFINE_TYPES(riscv_cpu_type_infos) 654