1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qemu/error-report.h" 32 #include "hw/qdev-properties.h" 33 #include "migration/vmstate.h" 34 #include "fpu/softfloat-helpers.h" 35 #include "sysemu/kvm.h" 36 #include "kvm_riscv.h" 37 38 /* RISC-V CPU definitions */ 39 40 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 41 (QEMU_VERSION_MINOR << 8) | \ 42 (QEMU_VERSION_MICRO)) 43 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 44 45 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 46 47 struct isa_ext_data { 48 const char *name; 49 bool multi_letter; 50 int min_version; 51 int ext_enable_offset; 52 }; 53 54 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ 55 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 56 57 /** 58 * Here are the ordering rules of extension naming defined by RISC-V 59 * specification : 60 * 1. All extensions should be separated from other multi-letter extensions 61 * by an underscore. 62 * 2. The first letter following the 'Z' conventionally indicates the most 63 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 64 * If multiple 'Z' extensions are named, they should be ordered first 65 * by category, then alphabetically within a category. 66 * 3. Standard supervisor-level extensions (starts with 'S') should be 67 * listed after standard unprivileged extensions. If multiple 68 * supervisor-level extensions are listed, they should be ordered 69 * alphabetically. 70 * 4. Non-standard extensions (starts with 'X') must be listed after all 71 * standard extensions. They must be separated from other multi-letter 72 * extensions by an underscore. 73 */ 74 static const struct isa_ext_data isa_edata_arr[] = { 75 ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), 76 ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), 77 ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), 78 ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), 79 ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), 80 ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), 81 ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), 82 ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), 83 ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), 84 ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), 85 ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), 86 ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), 87 ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), 88 ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), 89 ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), 90 ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), 91 ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), 92 ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), 93 ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), 94 ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), 95 ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), 96 ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), 97 ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), 98 ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), 99 ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), 100 ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), 101 ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), 102 ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), 103 ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), 104 ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), 105 ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), 106 ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), 107 ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), 108 ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), 109 ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), 110 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), 111 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), 112 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), 113 ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), 114 ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), 115 ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), 116 ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), 117 ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 118 ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 119 ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), 120 ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 121 ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), 122 ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), 123 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 124 }; 125 126 static bool isa_ext_is_enabled(RISCVCPU *cpu, 127 const struct isa_ext_data *edata) 128 { 129 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 130 131 return *ext_enabled; 132 } 133 134 static void isa_ext_update_enabled(RISCVCPU *cpu, 135 const struct isa_ext_data *edata, bool en) 136 { 137 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 138 139 *ext_enabled = en; 140 } 141 142 const char * const riscv_int_regnames[] = { 143 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 144 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 145 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 146 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 147 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 148 }; 149 150 const char * const riscv_int_regnamesh[] = { 151 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 152 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 153 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 154 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 155 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 156 "x30h/t5h", "x31h/t6h" 157 }; 158 159 const char * const riscv_fpr_regnames[] = { 160 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 161 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 162 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 163 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 164 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 165 "f30/ft10", "f31/ft11" 166 }; 167 168 static const char * const riscv_excp_names[] = { 169 "misaligned_fetch", 170 "fault_fetch", 171 "illegal_instruction", 172 "breakpoint", 173 "misaligned_load", 174 "fault_load", 175 "misaligned_store", 176 "fault_store", 177 "user_ecall", 178 "supervisor_ecall", 179 "hypervisor_ecall", 180 "machine_ecall", 181 "exec_page_fault", 182 "load_page_fault", 183 "reserved", 184 "store_page_fault", 185 "reserved", 186 "reserved", 187 "reserved", 188 "reserved", 189 "guest_exec_page_fault", 190 "guest_load_page_fault", 191 "reserved", 192 "guest_store_page_fault", 193 }; 194 195 static const char * const riscv_intr_names[] = { 196 "u_software", 197 "s_software", 198 "vs_software", 199 "m_software", 200 "u_timer", 201 "s_timer", 202 "vs_timer", 203 "m_timer", 204 "u_external", 205 "s_external", 206 "vs_external", 207 "m_external", 208 "reserved", 209 "reserved", 210 "reserved", 211 "reserved" 212 }; 213 214 static void register_cpu_props(DeviceState *dev); 215 216 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 217 { 218 if (async) { 219 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 220 riscv_intr_names[cause] : "(unknown)"; 221 } else { 222 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 223 riscv_excp_names[cause] : "(unknown)"; 224 } 225 } 226 227 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 228 { 229 env->misa_mxl_max = env->misa_mxl = mxl; 230 env->misa_ext_mask = env->misa_ext = ext; 231 } 232 233 static void set_priv_version(CPURISCVState *env, int priv_ver) 234 { 235 env->priv_ver = priv_ver; 236 } 237 238 static void set_vext_version(CPURISCVState *env, int vext_ver) 239 { 240 env->vext_ver = vext_ver; 241 } 242 243 static void riscv_any_cpu_init(Object *obj) 244 { 245 CPURISCVState *env = &RISCV_CPU(obj)->env; 246 #if defined(TARGET_RISCV32) 247 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 248 #elif defined(TARGET_RISCV64) 249 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 250 #endif 251 set_priv_version(env, PRIV_VERSION_1_12_0); 252 register_cpu_props(DEVICE(obj)); 253 } 254 255 #if defined(TARGET_RISCV64) 256 static void rv64_base_cpu_init(Object *obj) 257 { 258 CPURISCVState *env = &RISCV_CPU(obj)->env; 259 /* We set this in the realise function */ 260 set_misa(env, MXL_RV64, 0); 261 register_cpu_props(DEVICE(obj)); 262 /* Set latest version of privileged specification */ 263 set_priv_version(env, PRIV_VERSION_1_12_0); 264 } 265 266 static void rv64_sifive_u_cpu_init(Object *obj) 267 { 268 CPURISCVState *env = &RISCV_CPU(obj)->env; 269 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 270 register_cpu_props(DEVICE(obj)); 271 set_priv_version(env, PRIV_VERSION_1_10_0); 272 } 273 274 static void rv64_sifive_e_cpu_init(Object *obj) 275 { 276 CPURISCVState *env = &RISCV_CPU(obj)->env; 277 RISCVCPU *cpu = RISCV_CPU(obj); 278 279 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 280 register_cpu_props(DEVICE(obj)); 281 set_priv_version(env, PRIV_VERSION_1_10_0); 282 cpu->cfg.mmu = false; 283 } 284 285 static void rv64_thead_c906_cpu_init(Object *obj) 286 { 287 CPURISCVState *env = &RISCV_CPU(obj)->env; 288 RISCVCPU *cpu = RISCV_CPU(obj); 289 290 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 291 set_priv_version(env, PRIV_VERSION_1_11_0); 292 293 cpu->cfg.ext_g = true; 294 cpu->cfg.ext_c = true; 295 cpu->cfg.ext_u = true; 296 cpu->cfg.ext_s = true; 297 cpu->cfg.ext_icsr = true; 298 cpu->cfg.ext_zfh = true; 299 cpu->cfg.mmu = true; 300 cpu->cfg.ext_xtheadba = true; 301 cpu->cfg.ext_xtheadbb = true; 302 cpu->cfg.ext_xtheadbs = true; 303 cpu->cfg.ext_xtheadcmo = true; 304 cpu->cfg.ext_xtheadcondmov = true; 305 cpu->cfg.ext_xtheadfmemidx = true; 306 cpu->cfg.ext_xtheadmac = true; 307 cpu->cfg.ext_xtheadmemidx = true; 308 cpu->cfg.ext_xtheadmempair = true; 309 cpu->cfg.ext_xtheadsync = true; 310 311 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 312 } 313 314 static void rv128_base_cpu_init(Object *obj) 315 { 316 if (qemu_tcg_mttcg_enabled()) { 317 /* Missing 128-bit aligned atomics */ 318 error_report("128-bit RISC-V currently does not work with Multi " 319 "Threaded TCG. Please use: -accel tcg,thread=single"); 320 exit(EXIT_FAILURE); 321 } 322 CPURISCVState *env = &RISCV_CPU(obj)->env; 323 /* We set this in the realise function */ 324 set_misa(env, MXL_RV128, 0); 325 register_cpu_props(DEVICE(obj)); 326 /* Set latest version of privileged specification */ 327 set_priv_version(env, PRIV_VERSION_1_12_0); 328 } 329 #else 330 static void rv32_base_cpu_init(Object *obj) 331 { 332 CPURISCVState *env = &RISCV_CPU(obj)->env; 333 /* We set this in the realise function */ 334 set_misa(env, MXL_RV32, 0); 335 register_cpu_props(DEVICE(obj)); 336 /* Set latest version of privileged specification */ 337 set_priv_version(env, PRIV_VERSION_1_12_0); 338 } 339 340 static void rv32_sifive_u_cpu_init(Object *obj) 341 { 342 CPURISCVState *env = &RISCV_CPU(obj)->env; 343 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 344 register_cpu_props(DEVICE(obj)); 345 set_priv_version(env, PRIV_VERSION_1_10_0); 346 } 347 348 static void rv32_sifive_e_cpu_init(Object *obj) 349 { 350 CPURISCVState *env = &RISCV_CPU(obj)->env; 351 RISCVCPU *cpu = RISCV_CPU(obj); 352 353 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 354 register_cpu_props(DEVICE(obj)); 355 set_priv_version(env, PRIV_VERSION_1_10_0); 356 cpu->cfg.mmu = false; 357 } 358 359 static void rv32_ibex_cpu_init(Object *obj) 360 { 361 CPURISCVState *env = &RISCV_CPU(obj)->env; 362 RISCVCPU *cpu = RISCV_CPU(obj); 363 364 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 365 register_cpu_props(DEVICE(obj)); 366 set_priv_version(env, PRIV_VERSION_1_11_0); 367 cpu->cfg.mmu = false; 368 cpu->cfg.epmp = true; 369 } 370 371 static void rv32_imafcu_nommu_cpu_init(Object *obj) 372 { 373 CPURISCVState *env = &RISCV_CPU(obj)->env; 374 RISCVCPU *cpu = RISCV_CPU(obj); 375 376 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 377 register_cpu_props(DEVICE(obj)); 378 set_priv_version(env, PRIV_VERSION_1_10_0); 379 cpu->cfg.mmu = false; 380 } 381 #endif 382 383 #if defined(CONFIG_KVM) 384 static void riscv_host_cpu_init(Object *obj) 385 { 386 CPURISCVState *env = &RISCV_CPU(obj)->env; 387 #if defined(TARGET_RISCV32) 388 set_misa(env, MXL_RV32, 0); 389 #elif defined(TARGET_RISCV64) 390 set_misa(env, MXL_RV64, 0); 391 #endif 392 register_cpu_props(DEVICE(obj)); 393 } 394 #endif 395 396 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 397 { 398 ObjectClass *oc; 399 char *typename; 400 char **cpuname; 401 402 cpuname = g_strsplit(cpu_model, ",", 1); 403 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 404 oc = object_class_by_name(typename); 405 g_strfreev(cpuname); 406 g_free(typename); 407 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 408 object_class_is_abstract(oc)) { 409 return NULL; 410 } 411 return oc; 412 } 413 414 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 415 { 416 RISCVCPU *cpu = RISCV_CPU(cs); 417 CPURISCVState *env = &cpu->env; 418 int i; 419 420 #if !defined(CONFIG_USER_ONLY) 421 if (riscv_has_ext(env, RVH)) { 422 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 423 } 424 #endif 425 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 426 #ifndef CONFIG_USER_ONLY 427 { 428 static const int dump_csrs[] = { 429 CSR_MHARTID, 430 CSR_MSTATUS, 431 CSR_MSTATUSH, 432 /* 433 * CSR_SSTATUS is intentionally omitted here as its value 434 * can be figured out by looking at CSR_MSTATUS 435 */ 436 CSR_HSTATUS, 437 CSR_VSSTATUS, 438 CSR_MIP, 439 CSR_MIE, 440 CSR_MIDELEG, 441 CSR_HIDELEG, 442 CSR_MEDELEG, 443 CSR_HEDELEG, 444 CSR_MTVEC, 445 CSR_STVEC, 446 CSR_VSTVEC, 447 CSR_MEPC, 448 CSR_SEPC, 449 CSR_VSEPC, 450 CSR_MCAUSE, 451 CSR_SCAUSE, 452 CSR_VSCAUSE, 453 CSR_MTVAL, 454 CSR_STVAL, 455 CSR_HTVAL, 456 CSR_MTVAL2, 457 CSR_MSCRATCH, 458 CSR_SSCRATCH, 459 CSR_SATP, 460 CSR_MMTE, 461 CSR_UPMBASE, 462 CSR_UPMMASK, 463 CSR_SPMBASE, 464 CSR_SPMMASK, 465 CSR_MPMBASE, 466 CSR_MPMMASK, 467 }; 468 469 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 470 int csrno = dump_csrs[i]; 471 target_ulong val = 0; 472 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 473 474 /* 475 * Rely on the smode, hmode, etc, predicates within csr.c 476 * to do the filtering of the registers that are present. 477 */ 478 if (res == RISCV_EXCP_NONE) { 479 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 480 csr_ops[csrno].name, val); 481 } 482 } 483 } 484 #endif 485 486 for (i = 0; i < 32; i++) { 487 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 488 riscv_int_regnames[i], env->gpr[i]); 489 if ((i & 3) == 3) { 490 qemu_fprintf(f, "\n"); 491 } 492 } 493 if (flags & CPU_DUMP_FPU) { 494 for (i = 0; i < 32; i++) { 495 qemu_fprintf(f, " %-8s %016" PRIx64, 496 riscv_fpr_regnames[i], env->fpr[i]); 497 if ((i & 3) == 3) { 498 qemu_fprintf(f, "\n"); 499 } 500 } 501 } 502 } 503 504 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 505 { 506 RISCVCPU *cpu = RISCV_CPU(cs); 507 CPURISCVState *env = &cpu->env; 508 509 if (env->xl == MXL_RV32) { 510 env->pc = (int32_t)value; 511 } else { 512 env->pc = value; 513 } 514 } 515 516 static vaddr riscv_cpu_get_pc(CPUState *cs) 517 { 518 RISCVCPU *cpu = RISCV_CPU(cs); 519 CPURISCVState *env = &cpu->env; 520 521 /* Match cpu_get_tb_cpu_state. */ 522 if (env->xl == MXL_RV32) { 523 return env->pc & UINT32_MAX; 524 } 525 return env->pc; 526 } 527 528 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 529 const TranslationBlock *tb) 530 { 531 RISCVCPU *cpu = RISCV_CPU(cs); 532 CPURISCVState *env = &cpu->env; 533 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 534 535 if (xl == MXL_RV32) { 536 env->pc = (int32_t)tb_pc(tb); 537 } else { 538 env->pc = tb_pc(tb); 539 } 540 } 541 542 static bool riscv_cpu_has_work(CPUState *cs) 543 { 544 #ifndef CONFIG_USER_ONLY 545 RISCVCPU *cpu = RISCV_CPU(cs); 546 CPURISCVState *env = &cpu->env; 547 /* 548 * Definition of the WFI instruction requires it to ignore the privilege 549 * mode and delegation registers, but respect individual enables 550 */ 551 return riscv_cpu_all_pending(env) != 0; 552 #else 553 return true; 554 #endif 555 } 556 557 static void riscv_restore_state_to_opc(CPUState *cs, 558 const TranslationBlock *tb, 559 const uint64_t *data) 560 { 561 RISCVCPU *cpu = RISCV_CPU(cs); 562 CPURISCVState *env = &cpu->env; 563 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 564 565 if (xl == MXL_RV32) { 566 env->pc = (int32_t)data[0]; 567 } else { 568 env->pc = data[0]; 569 } 570 env->bins = data[1]; 571 } 572 573 static void riscv_cpu_reset_hold(Object *obj) 574 { 575 #ifndef CONFIG_USER_ONLY 576 uint8_t iprio; 577 int i, irq, rdzero; 578 #endif 579 CPUState *cs = CPU(obj); 580 RISCVCPU *cpu = RISCV_CPU(cs); 581 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 582 CPURISCVState *env = &cpu->env; 583 584 if (mcc->parent_phases.hold) { 585 mcc->parent_phases.hold(obj); 586 } 587 #ifndef CONFIG_USER_ONLY 588 env->misa_mxl = env->misa_mxl_max; 589 env->priv = PRV_M; 590 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 591 if (env->misa_mxl > MXL_RV32) { 592 /* 593 * The reset status of SXL/UXL is undefined, but mstatus is WARL 594 * and we must ensure that the value after init is valid for read. 595 */ 596 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 597 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 598 if (riscv_has_ext(env, RVH)) { 599 env->vsstatus = set_field(env->vsstatus, 600 MSTATUS64_SXL, env->misa_mxl); 601 env->vsstatus = set_field(env->vsstatus, 602 MSTATUS64_UXL, env->misa_mxl); 603 env->mstatus_hs = set_field(env->mstatus_hs, 604 MSTATUS64_SXL, env->misa_mxl); 605 env->mstatus_hs = set_field(env->mstatus_hs, 606 MSTATUS64_UXL, env->misa_mxl); 607 } 608 } 609 env->mcause = 0; 610 env->miclaim = MIP_SGEIP; 611 env->pc = env->resetvec; 612 env->bins = 0; 613 env->two_stage_lookup = false; 614 615 /* Initialized default priorities of local interrupts. */ 616 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 617 iprio = riscv_cpu_default_priority(i); 618 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 619 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 620 env->hviprio[i] = 0; 621 } 622 i = 0; 623 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 624 if (!rdzero) { 625 env->hviprio[irq] = env->miprio[irq]; 626 } 627 i++; 628 } 629 /* mmte is supposed to have pm.current hardwired to 1 */ 630 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 631 #endif 632 env->xl = riscv_cpu_mxl(env); 633 riscv_cpu_update_mask(env); 634 cs->exception_index = RISCV_EXCP_NONE; 635 env->load_res = -1; 636 set_default_nan_mode(1, &env->fp_status); 637 638 #ifndef CONFIG_USER_ONLY 639 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 640 riscv_trigger_init(env); 641 } 642 643 if (kvm_enabled()) { 644 kvm_riscv_reset_vcpu(cpu); 645 } 646 #endif 647 } 648 649 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 650 { 651 RISCVCPU *cpu = RISCV_CPU(s); 652 653 switch (riscv_cpu_mxl(&cpu->env)) { 654 case MXL_RV32: 655 info->print_insn = print_insn_riscv32; 656 break; 657 case MXL_RV64: 658 info->print_insn = print_insn_riscv64; 659 break; 660 case MXL_RV128: 661 info->print_insn = print_insn_riscv128; 662 break; 663 default: 664 g_assert_not_reached(); 665 } 666 } 667 668 /* 669 * Check consistency between chosen extensions while setting 670 * cpu->cfg accordingly, doing a set_misa() in the end. 671 */ 672 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 673 { 674 CPURISCVState *env = &cpu->env; 675 uint32_t ext = 0; 676 677 /* Do some ISA extension error checking */ 678 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 679 cpu->cfg.ext_a && cpu->cfg.ext_f && 680 cpu->cfg.ext_d && 681 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 682 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 683 cpu->cfg.ext_i = true; 684 cpu->cfg.ext_m = true; 685 cpu->cfg.ext_a = true; 686 cpu->cfg.ext_f = true; 687 cpu->cfg.ext_d = true; 688 cpu->cfg.ext_icsr = true; 689 cpu->cfg.ext_ifencei = true; 690 } 691 692 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 693 error_setg(errp, 694 "I and E extensions are incompatible"); 695 return; 696 } 697 698 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 699 error_setg(errp, 700 "Either I or E extension must be set"); 701 return; 702 } 703 704 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 705 error_setg(errp, 706 "Setting S extension without U extension is illegal"); 707 return; 708 } 709 710 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { 711 error_setg(errp, 712 "H depends on an I base integer ISA with 32 x registers"); 713 return; 714 } 715 716 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 717 error_setg(errp, "H extension implicitly requires S-mode"); 718 return; 719 } 720 721 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 722 error_setg(errp, "F extension requires Zicsr"); 723 return; 724 } 725 726 if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { 727 error_setg(errp, "Zawrs extension requires A extension"); 728 return; 729 } 730 731 if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { 732 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 733 return; 734 } 735 736 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 737 error_setg(errp, "D extension requires F extension"); 738 return; 739 } 740 741 if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { 742 error_setg(errp, "V extension requires D extension"); 743 return; 744 } 745 746 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 747 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 748 return; 749 } 750 751 /* Set the ISA extensions, checks should have happened above */ 752 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || 753 cpu->cfg.ext_zhinxmin) { 754 cpu->cfg.ext_zfinx = true; 755 } 756 757 if (cpu->cfg.ext_zfinx) { 758 if (!cpu->cfg.ext_icsr) { 759 error_setg(errp, "Zfinx extension requires Zicsr"); 760 return; 761 } 762 if (cpu->cfg.ext_f) { 763 error_setg(errp, 764 "Zfinx cannot be supported together with F extension"); 765 return; 766 } 767 } 768 769 if (cpu->cfg.ext_zk) { 770 cpu->cfg.ext_zkn = true; 771 cpu->cfg.ext_zkr = true; 772 cpu->cfg.ext_zkt = true; 773 } 774 775 if (cpu->cfg.ext_zkn) { 776 cpu->cfg.ext_zbkb = true; 777 cpu->cfg.ext_zbkc = true; 778 cpu->cfg.ext_zbkx = true; 779 cpu->cfg.ext_zkne = true; 780 cpu->cfg.ext_zknd = true; 781 cpu->cfg.ext_zknh = true; 782 } 783 784 if (cpu->cfg.ext_zks) { 785 cpu->cfg.ext_zbkb = true; 786 cpu->cfg.ext_zbkc = true; 787 cpu->cfg.ext_zbkx = true; 788 cpu->cfg.ext_zksed = true; 789 cpu->cfg.ext_zksh = true; 790 } 791 792 if (cpu->cfg.ext_i) { 793 ext |= RVI; 794 } 795 if (cpu->cfg.ext_e) { 796 ext |= RVE; 797 } 798 if (cpu->cfg.ext_m) { 799 ext |= RVM; 800 } 801 if (cpu->cfg.ext_a) { 802 ext |= RVA; 803 } 804 if (cpu->cfg.ext_f) { 805 ext |= RVF; 806 } 807 if (cpu->cfg.ext_d) { 808 ext |= RVD; 809 } 810 if (cpu->cfg.ext_c) { 811 ext |= RVC; 812 } 813 if (cpu->cfg.ext_s) { 814 ext |= RVS; 815 } 816 if (cpu->cfg.ext_u) { 817 ext |= RVU; 818 } 819 if (cpu->cfg.ext_h) { 820 ext |= RVH; 821 } 822 if (cpu->cfg.ext_v) { 823 int vext_version = VEXT_VERSION_1_00_0; 824 ext |= RVV; 825 if (!is_power_of_2(cpu->cfg.vlen)) { 826 error_setg(errp, 827 "Vector extension VLEN must be power of 2"); 828 return; 829 } 830 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 831 error_setg(errp, 832 "Vector extension implementation only supports VLEN " 833 "in the range [128, %d]", RV_VLEN_MAX); 834 return; 835 } 836 if (!is_power_of_2(cpu->cfg.elen)) { 837 error_setg(errp, 838 "Vector extension ELEN must be power of 2"); 839 return; 840 } 841 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 842 error_setg(errp, 843 "Vector extension implementation only supports ELEN " 844 "in the range [8, 64]"); 845 return; 846 } 847 if (cpu->cfg.vext_spec) { 848 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 849 vext_version = VEXT_VERSION_1_00_0; 850 } else { 851 error_setg(errp, 852 "Unsupported vector spec version '%s'", 853 cpu->cfg.vext_spec); 854 return; 855 } 856 } else { 857 qemu_log("vector version is not specified, " 858 "use the default value v1.0\n"); 859 } 860 set_vext_version(env, vext_version); 861 } 862 if (cpu->cfg.ext_j) { 863 ext |= RVJ; 864 } 865 866 set_misa(env, env->misa_mxl, ext); 867 } 868 869 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 870 { 871 CPUState *cs = CPU(dev); 872 RISCVCPU *cpu = RISCV_CPU(dev); 873 CPURISCVState *env = &cpu->env; 874 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 875 CPUClass *cc = CPU_CLASS(mcc); 876 int i, priv_version = -1; 877 Error *local_err = NULL; 878 879 cpu_exec_realizefn(cs, &local_err); 880 if (local_err != NULL) { 881 error_propagate(errp, local_err); 882 return; 883 } 884 885 if (cpu->cfg.priv_spec) { 886 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 887 priv_version = PRIV_VERSION_1_12_0; 888 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 889 priv_version = PRIV_VERSION_1_11_0; 890 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 891 priv_version = PRIV_VERSION_1_10_0; 892 } else { 893 error_setg(errp, 894 "Unsupported privilege spec version '%s'", 895 cpu->cfg.priv_spec); 896 return; 897 } 898 } 899 900 if (priv_version >= PRIV_VERSION_1_10_0) { 901 set_priv_version(env, priv_version); 902 } 903 904 /* Force disable extensions if priv spec version does not match */ 905 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 906 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 907 (env->priv_ver < isa_edata_arr[i].min_version)) { 908 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 909 #ifndef CONFIG_USER_ONLY 910 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 911 " because privilege spec version does not match", 912 isa_edata_arr[i].name, env->mhartid); 913 #else 914 warn_report("disabling %s extension because " 915 "privilege spec version does not match", 916 isa_edata_arr[i].name); 917 #endif 918 } 919 } 920 921 if (cpu->cfg.mmu) { 922 riscv_set_feature(env, RISCV_FEATURE_MMU); 923 } 924 925 if (cpu->cfg.pmp) { 926 riscv_set_feature(env, RISCV_FEATURE_PMP); 927 928 /* 929 * Enhanced PMP should only be available 930 * on harts with PMP support 931 */ 932 if (cpu->cfg.epmp) { 933 riscv_set_feature(env, RISCV_FEATURE_EPMP); 934 } 935 } 936 937 if (cpu->cfg.debug) { 938 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 939 } 940 941 942 #ifndef CONFIG_USER_ONLY 943 if (cpu->cfg.ext_sstc) { 944 riscv_timer_init(cpu); 945 } 946 #endif /* CONFIG_USER_ONLY */ 947 948 /* Validate that MISA_MXL is set properly. */ 949 switch (env->misa_mxl_max) { 950 #ifdef TARGET_RISCV64 951 case MXL_RV64: 952 case MXL_RV128: 953 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 954 break; 955 #endif 956 case MXL_RV32: 957 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 958 break; 959 default: 960 g_assert_not_reached(); 961 } 962 assert(env->misa_mxl_max == env->misa_mxl); 963 964 riscv_cpu_validate_set_extensions(cpu, &local_err); 965 if (local_err != NULL) { 966 error_propagate(errp, local_err); 967 return; 968 } 969 970 #ifndef CONFIG_USER_ONLY 971 if (cpu->cfg.pmu_num) { 972 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 973 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 974 riscv_pmu_timer_cb, cpu); 975 } 976 } 977 #endif 978 979 riscv_cpu_register_gdb_regs_for_features(cs); 980 981 qemu_init_vcpu(cs); 982 cpu_reset(cs); 983 984 mcc->parent_realize(dev, errp); 985 } 986 987 #ifndef CONFIG_USER_ONLY 988 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 989 { 990 RISCVCPU *cpu = RISCV_CPU(opaque); 991 CPURISCVState *env = &cpu->env; 992 993 if (irq < IRQ_LOCAL_MAX) { 994 switch (irq) { 995 case IRQ_U_SOFT: 996 case IRQ_S_SOFT: 997 case IRQ_VS_SOFT: 998 case IRQ_M_SOFT: 999 case IRQ_U_TIMER: 1000 case IRQ_S_TIMER: 1001 case IRQ_VS_TIMER: 1002 case IRQ_M_TIMER: 1003 case IRQ_U_EXT: 1004 case IRQ_VS_EXT: 1005 case IRQ_M_EXT: 1006 if (kvm_enabled()) { 1007 kvm_riscv_set_irq(cpu, irq, level); 1008 } else { 1009 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 1010 } 1011 break; 1012 case IRQ_S_EXT: 1013 if (kvm_enabled()) { 1014 kvm_riscv_set_irq(cpu, irq, level); 1015 } else { 1016 env->external_seip = level; 1017 riscv_cpu_update_mip(cpu, 1 << irq, 1018 BOOL_TO_MASK(level | env->software_seip)); 1019 } 1020 break; 1021 default: 1022 g_assert_not_reached(); 1023 } 1024 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1025 /* Require H-extension for handling guest local interrupts */ 1026 if (!riscv_has_ext(env, RVH)) { 1027 g_assert_not_reached(); 1028 } 1029 1030 /* Compute bit position in HGEIP CSR */ 1031 irq = irq - IRQ_LOCAL_MAX + 1; 1032 if (env->geilen < irq) { 1033 g_assert_not_reached(); 1034 } 1035 1036 /* Update HGEIP CSR */ 1037 env->hgeip &= ~((target_ulong)1 << irq); 1038 if (level) { 1039 env->hgeip |= (target_ulong)1 << irq; 1040 } 1041 1042 /* Update mip.SGEIP bit */ 1043 riscv_cpu_update_mip(cpu, MIP_SGEIP, 1044 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1045 } else { 1046 g_assert_not_reached(); 1047 } 1048 } 1049 #endif /* CONFIG_USER_ONLY */ 1050 1051 static void riscv_cpu_init(Object *obj) 1052 { 1053 RISCVCPU *cpu = RISCV_CPU(obj); 1054 1055 cpu->cfg.ext_ifencei = true; 1056 cpu->cfg.ext_icsr = true; 1057 cpu->cfg.mmu = true; 1058 cpu->cfg.pmp = true; 1059 1060 cpu_set_cpustate_pointers(cpu); 1061 1062 #ifndef CONFIG_USER_ONLY 1063 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1064 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1065 #endif /* CONFIG_USER_ONLY */ 1066 } 1067 1068 static Property riscv_cpu_extensions[] = { 1069 /* Defaults for standard extensions */ 1070 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 1071 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 1072 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1073 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 1074 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 1075 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 1076 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 1077 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 1078 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 1079 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1080 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1081 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1082 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1083 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1084 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1085 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1086 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1087 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1088 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1089 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1090 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1091 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1092 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1093 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1094 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1095 1096 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1097 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1098 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1099 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1100 1101 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1102 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1103 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1104 1105 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1106 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1107 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1108 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1109 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1110 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1111 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1112 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1113 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1114 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1115 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1116 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1117 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1118 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1119 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1120 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1121 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1122 1123 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1124 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1125 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1126 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1127 1128 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1129 1130 /* Vendor-specific custom extensions */ 1131 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1132 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1133 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1134 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1135 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1136 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1137 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1138 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1139 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1140 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1141 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1142 1143 /* These are experimental so mark with 'x-' */ 1144 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1145 /* ePMP 0.9.3 */ 1146 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1147 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1148 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1149 1150 DEFINE_PROP_END_OF_LIST(), 1151 }; 1152 1153 /* 1154 * Register CPU props based on env.misa_ext. If a non-zero 1155 * value was set, register only the required cpu->cfg.ext_* 1156 * properties and leave. env.misa_ext = 0 means that we want 1157 * all the default properties to be registered. 1158 */ 1159 static void register_cpu_props(DeviceState *dev) 1160 { 1161 RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); 1162 uint32_t misa_ext = cpu->env.misa_ext; 1163 Property *prop; 1164 1165 /* 1166 * If misa_ext is not zero, set cfg properties now to 1167 * allow them to be read during riscv_cpu_realize() 1168 * later on. 1169 */ 1170 if (cpu->env.misa_ext != 0) { 1171 cpu->cfg.ext_i = misa_ext & RVI; 1172 cpu->cfg.ext_e = misa_ext & RVE; 1173 cpu->cfg.ext_m = misa_ext & RVM; 1174 cpu->cfg.ext_a = misa_ext & RVA; 1175 cpu->cfg.ext_f = misa_ext & RVF; 1176 cpu->cfg.ext_d = misa_ext & RVD; 1177 cpu->cfg.ext_v = misa_ext & RVV; 1178 cpu->cfg.ext_c = misa_ext & RVC; 1179 cpu->cfg.ext_s = misa_ext & RVS; 1180 cpu->cfg.ext_u = misa_ext & RVU; 1181 cpu->cfg.ext_h = misa_ext & RVH; 1182 cpu->cfg.ext_j = misa_ext & RVJ; 1183 1184 /* 1185 * We don't want to set the default riscv_cpu_extensions 1186 * in this case. 1187 */ 1188 return; 1189 } 1190 1191 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1192 qdev_property_add_static(dev, prop); 1193 } 1194 } 1195 1196 static Property riscv_cpu_properties[] = { 1197 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1198 1199 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1200 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1201 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1202 1203 #ifndef CONFIG_USER_ONLY 1204 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1205 #endif 1206 1207 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1208 1209 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1210 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1211 DEFINE_PROP_END_OF_LIST(), 1212 }; 1213 1214 static gchar *riscv_gdb_arch_name(CPUState *cs) 1215 { 1216 RISCVCPU *cpu = RISCV_CPU(cs); 1217 CPURISCVState *env = &cpu->env; 1218 1219 switch (riscv_cpu_mxl(env)) { 1220 case MXL_RV32: 1221 return g_strdup("riscv:rv32"); 1222 case MXL_RV64: 1223 case MXL_RV128: 1224 return g_strdup("riscv:rv64"); 1225 default: 1226 g_assert_not_reached(); 1227 } 1228 } 1229 1230 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1231 { 1232 RISCVCPU *cpu = RISCV_CPU(cs); 1233 1234 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1235 return cpu->dyn_csr_xml; 1236 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1237 return cpu->dyn_vreg_xml; 1238 } 1239 1240 return NULL; 1241 } 1242 1243 #ifndef CONFIG_USER_ONLY 1244 #include "hw/core/sysemu-cpu-ops.h" 1245 1246 static const struct SysemuCPUOps riscv_sysemu_ops = { 1247 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1248 .write_elf64_note = riscv_cpu_write_elf64_note, 1249 .write_elf32_note = riscv_cpu_write_elf32_note, 1250 .legacy_vmsd = &vmstate_riscv_cpu, 1251 }; 1252 #endif 1253 1254 #include "hw/core/tcg-cpu-ops.h" 1255 1256 static const struct TCGCPUOps riscv_tcg_ops = { 1257 .initialize = riscv_translate_init, 1258 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1259 .restore_state_to_opc = riscv_restore_state_to_opc, 1260 1261 #ifndef CONFIG_USER_ONLY 1262 .tlb_fill = riscv_cpu_tlb_fill, 1263 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1264 .do_interrupt = riscv_cpu_do_interrupt, 1265 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1266 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1267 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1268 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1269 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1270 #endif /* !CONFIG_USER_ONLY */ 1271 }; 1272 1273 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1274 { 1275 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1276 CPUClass *cc = CPU_CLASS(c); 1277 DeviceClass *dc = DEVICE_CLASS(c); 1278 ResettableClass *rc = RESETTABLE_CLASS(c); 1279 1280 device_class_set_parent_realize(dc, riscv_cpu_realize, 1281 &mcc->parent_realize); 1282 1283 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1284 &mcc->parent_phases); 1285 1286 cc->class_by_name = riscv_cpu_class_by_name; 1287 cc->has_work = riscv_cpu_has_work; 1288 cc->dump_state = riscv_cpu_dump_state; 1289 cc->set_pc = riscv_cpu_set_pc; 1290 cc->get_pc = riscv_cpu_get_pc; 1291 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1292 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1293 cc->gdb_num_core_regs = 33; 1294 cc->gdb_stop_before_watchpoint = true; 1295 cc->disas_set_info = riscv_cpu_disas_set_info; 1296 #ifndef CONFIG_USER_ONLY 1297 cc->sysemu_ops = &riscv_sysemu_ops; 1298 #endif 1299 cc->gdb_arch_name = riscv_gdb_arch_name; 1300 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1301 cc->tcg_ops = &riscv_tcg_ops; 1302 1303 device_class_set_props(dc, riscv_cpu_properties); 1304 } 1305 1306 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1307 { 1308 char *old = *isa_str; 1309 char *new = *isa_str; 1310 int i; 1311 1312 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1313 if (isa_edata_arr[i].multi_letter && 1314 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1315 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1316 g_free(old); 1317 old = new; 1318 } 1319 } 1320 1321 *isa_str = new; 1322 } 1323 1324 char *riscv_isa_string(RISCVCPU *cpu) 1325 { 1326 int i; 1327 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1328 char *isa_str = g_new(char, maxlen); 1329 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1330 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1331 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1332 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1333 } 1334 } 1335 *p = '\0'; 1336 if (!cpu->cfg.short_isa_string) { 1337 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1338 } 1339 return isa_str; 1340 } 1341 1342 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1343 { 1344 ObjectClass *class_a = (ObjectClass *)a; 1345 ObjectClass *class_b = (ObjectClass *)b; 1346 const char *name_a, *name_b; 1347 1348 name_a = object_class_get_name(class_a); 1349 name_b = object_class_get_name(class_b); 1350 return strcmp(name_a, name_b); 1351 } 1352 1353 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1354 { 1355 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1356 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1357 1358 qemu_printf("%.*s\n", len, typename); 1359 } 1360 1361 void riscv_cpu_list(void) 1362 { 1363 GSList *list; 1364 1365 list = object_class_get_list(TYPE_RISCV_CPU, false); 1366 list = g_slist_sort(list, riscv_cpu_list_compare); 1367 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1368 g_slist_free(list); 1369 } 1370 1371 #define DEFINE_CPU(type_name, initfn) \ 1372 { \ 1373 .name = type_name, \ 1374 .parent = TYPE_RISCV_CPU, \ 1375 .instance_init = initfn \ 1376 } 1377 1378 static const TypeInfo riscv_cpu_type_infos[] = { 1379 { 1380 .name = TYPE_RISCV_CPU, 1381 .parent = TYPE_CPU, 1382 .instance_size = sizeof(RISCVCPU), 1383 .instance_align = __alignof__(RISCVCPU), 1384 .instance_init = riscv_cpu_init, 1385 .abstract = true, 1386 .class_size = sizeof(RISCVCPUClass), 1387 .class_init = riscv_cpu_class_init, 1388 }, 1389 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1390 #if defined(CONFIG_KVM) 1391 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1392 #endif 1393 #if defined(TARGET_RISCV32) 1394 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1395 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1396 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1397 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1398 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1399 #elif defined(TARGET_RISCV64) 1400 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1401 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1402 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1403 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1404 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1405 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1406 #endif 1407 }; 1408 1409 DEFINE_TYPES(riscv_cpu_type_infos) 1410