1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "exec/exec-all.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 #include "fpu/softfloat-helpers.h" 31 32 /* RISC-V CPU definitions */ 33 34 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 35 36 const char * const riscv_int_regnames[] = { 37 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 38 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 39 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 40 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 41 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 42 }; 43 44 const char * const riscv_fpr_regnames[] = { 45 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 46 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 47 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 48 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 49 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 50 "f30/ft10", "f31/ft11" 51 }; 52 53 const char * const riscv_excp_names[] = { 54 "misaligned_fetch", 55 "fault_fetch", 56 "illegal_instruction", 57 "breakpoint", 58 "misaligned_load", 59 "fault_load", 60 "misaligned_store", 61 "fault_store", 62 "user_ecall", 63 "supervisor_ecall", 64 "hypervisor_ecall", 65 "machine_ecall", 66 "exec_page_fault", 67 "load_page_fault", 68 "reserved", 69 "store_page_fault", 70 "reserved", 71 "reserved", 72 "reserved", 73 "reserved", 74 "guest_exec_page_fault", 75 "guest_load_page_fault", 76 "reserved", 77 "guest_store_page_fault", 78 }; 79 80 const char * const riscv_intr_names[] = { 81 "u_software", 82 "s_software", 83 "vs_software", 84 "m_software", 85 "u_timer", 86 "s_timer", 87 "vs_timer", 88 "m_timer", 89 "u_external", 90 "vs_external", 91 "h_external", 92 "m_external", 93 "reserved", 94 "reserved", 95 "reserved", 96 "reserved" 97 }; 98 99 static void set_misa(CPURISCVState *env, target_ulong misa) 100 { 101 env->misa_mask = env->misa = misa; 102 } 103 104 static void set_priv_version(CPURISCVState *env, int priv_ver) 105 { 106 env->priv_ver = priv_ver; 107 } 108 109 static void set_feature(CPURISCVState *env, int feature) 110 { 111 env->features |= (1ULL << feature); 112 } 113 114 static void set_resetvec(CPURISCVState *env, int resetvec) 115 { 116 #ifndef CONFIG_USER_ONLY 117 env->resetvec = resetvec; 118 #endif 119 } 120 121 static void riscv_any_cpu_init(Object *obj) 122 { 123 CPURISCVState *env = &RISCV_CPU(obj)->env; 124 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); 125 set_priv_version(env, PRIV_VERSION_1_11_0); 126 set_resetvec(env, DEFAULT_RSTVEC); 127 } 128 129 #if defined(TARGET_RISCV32) 130 131 static void riscv_base32_cpu_init(Object *obj) 132 { 133 CPURISCVState *env = &RISCV_CPU(obj)->env; 134 /* We set this in the realise function */ 135 set_misa(env, 0); 136 } 137 138 static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) 139 { 140 CPURISCVState *env = &RISCV_CPU(obj)->env; 141 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 142 set_priv_version(env, PRIV_VERSION_1_09_1); 143 set_resetvec(env, DEFAULT_RSTVEC); 144 set_feature(env, RISCV_FEATURE_MMU); 145 set_feature(env, RISCV_FEATURE_PMP); 146 } 147 148 static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) 149 { 150 CPURISCVState *env = &RISCV_CPU(obj)->env; 151 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 152 set_priv_version(env, PRIV_VERSION_1_10_0); 153 set_resetvec(env, DEFAULT_RSTVEC); 154 set_feature(env, RISCV_FEATURE_MMU); 155 set_feature(env, RISCV_FEATURE_PMP); 156 } 157 158 static void rv32imacu_nommu_cpu_init(Object *obj) 159 { 160 CPURISCVState *env = &RISCV_CPU(obj)->env; 161 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); 162 set_priv_version(env, PRIV_VERSION_1_10_0); 163 set_resetvec(env, DEFAULT_RSTVEC); 164 set_feature(env, RISCV_FEATURE_PMP); 165 } 166 167 static void rv32imafcu_nommu_cpu_init(Object *obj) 168 { 169 CPURISCVState *env = &RISCV_CPU(obj)->env; 170 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); 171 set_priv_version(env, PRIV_VERSION_1_10_0); 172 set_resetvec(env, DEFAULT_RSTVEC); 173 set_feature(env, RISCV_FEATURE_PMP); 174 } 175 176 #elif defined(TARGET_RISCV64) 177 178 static void riscv_base64_cpu_init(Object *obj) 179 { 180 CPURISCVState *env = &RISCV_CPU(obj)->env; 181 /* We set this in the realise function */ 182 set_misa(env, 0); 183 } 184 185 static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) 186 { 187 CPURISCVState *env = &RISCV_CPU(obj)->env; 188 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 189 set_priv_version(env, PRIV_VERSION_1_09_1); 190 set_resetvec(env, DEFAULT_RSTVEC); 191 set_feature(env, RISCV_FEATURE_MMU); 192 set_feature(env, RISCV_FEATURE_PMP); 193 } 194 195 static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) 196 { 197 CPURISCVState *env = &RISCV_CPU(obj)->env; 198 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 199 set_priv_version(env, PRIV_VERSION_1_10_0); 200 set_resetvec(env, DEFAULT_RSTVEC); 201 set_feature(env, RISCV_FEATURE_MMU); 202 set_feature(env, RISCV_FEATURE_PMP); 203 } 204 205 static void rv64imacu_nommu_cpu_init(Object *obj) 206 { 207 CPURISCVState *env = &RISCV_CPU(obj)->env; 208 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); 209 set_priv_version(env, PRIV_VERSION_1_10_0); 210 set_resetvec(env, DEFAULT_RSTVEC); 211 set_feature(env, RISCV_FEATURE_PMP); 212 } 213 214 #endif 215 216 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 217 { 218 ObjectClass *oc; 219 char *typename; 220 char **cpuname; 221 222 cpuname = g_strsplit(cpu_model, ",", 1); 223 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 224 oc = object_class_by_name(typename); 225 g_strfreev(cpuname); 226 g_free(typename); 227 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 228 object_class_is_abstract(oc)) { 229 return NULL; 230 } 231 return oc; 232 } 233 234 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 235 { 236 RISCVCPU *cpu = RISCV_CPU(cs); 237 CPURISCVState *env = &cpu->env; 238 int i; 239 240 #if !defined(CONFIG_USER_ONLY) 241 if (riscv_has_ext(env, RVH)) { 242 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 243 } 244 #endif 245 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 246 #ifndef CONFIG_USER_ONLY 247 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); 248 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); 249 #ifdef TARGET_RISCV32 250 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", env->mstatush); 251 #endif 252 if (riscv_has_ext(env, RVH)) { 253 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); 254 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", env->vsstatus); 255 } 256 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); 257 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); 258 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); 259 if (riscv_has_ext(env, RVH)) { 260 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); 261 } 262 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); 263 if (riscv_has_ext(env, RVH)) { 264 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); 265 } 266 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); 267 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); 268 if (riscv_has_ext(env, RVH)) { 269 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); 270 } 271 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); 272 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); 273 if (riscv_has_ext(env, RVH)) { 274 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); 275 } 276 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); 277 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); 278 if (riscv_has_ext(env, RVH)) { 279 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); 280 } 281 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); 282 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr); 283 if (riscv_has_ext(env, RVH)) { 284 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); 285 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); 286 } 287 #endif 288 289 for (i = 0; i < 32; i++) { 290 qemu_fprintf(f, " %s " TARGET_FMT_lx, 291 riscv_int_regnames[i], env->gpr[i]); 292 if ((i & 3) == 3) { 293 qemu_fprintf(f, "\n"); 294 } 295 } 296 if (flags & CPU_DUMP_FPU) { 297 for (i = 0; i < 32; i++) { 298 qemu_fprintf(f, " %s %016" PRIx64, 299 riscv_fpr_regnames[i], env->fpr[i]); 300 if ((i & 3) == 3) { 301 qemu_fprintf(f, "\n"); 302 } 303 } 304 } 305 } 306 307 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 308 { 309 RISCVCPU *cpu = RISCV_CPU(cs); 310 CPURISCVState *env = &cpu->env; 311 env->pc = value; 312 } 313 314 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 315 { 316 RISCVCPU *cpu = RISCV_CPU(cs); 317 CPURISCVState *env = &cpu->env; 318 env->pc = tb->pc; 319 } 320 321 static bool riscv_cpu_has_work(CPUState *cs) 322 { 323 #ifndef CONFIG_USER_ONLY 324 RISCVCPU *cpu = RISCV_CPU(cs); 325 CPURISCVState *env = &cpu->env; 326 /* 327 * Definition of the WFI instruction requires it to ignore the privilege 328 * mode and delegation registers, but respect individual enables 329 */ 330 return (env->mip & env->mie) != 0; 331 #else 332 return true; 333 #endif 334 } 335 336 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 337 target_ulong *data) 338 { 339 env->pc = data[0]; 340 } 341 342 static void riscv_cpu_reset(DeviceState *dev) 343 { 344 CPUState *cs = CPU(dev); 345 RISCVCPU *cpu = RISCV_CPU(cs); 346 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 347 CPURISCVState *env = &cpu->env; 348 349 mcc->parent_reset(dev); 350 #ifndef CONFIG_USER_ONLY 351 env->priv = PRV_M; 352 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 353 env->mcause = 0; 354 env->pc = env->resetvec; 355 #endif 356 cs->exception_index = EXCP_NONE; 357 env->load_res = -1; 358 set_default_nan_mode(1, &env->fp_status); 359 } 360 361 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 362 { 363 #if defined(TARGET_RISCV32) 364 info->print_insn = print_insn_riscv32; 365 #elif defined(TARGET_RISCV64) 366 info->print_insn = print_insn_riscv64; 367 #endif 368 } 369 370 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 371 { 372 CPUState *cs = CPU(dev); 373 RISCVCPU *cpu = RISCV_CPU(dev); 374 CPURISCVState *env = &cpu->env; 375 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 376 int priv_version = PRIV_VERSION_1_11_0; 377 target_ulong target_misa = 0; 378 Error *local_err = NULL; 379 380 cpu_exec_realizefn(cs, &local_err); 381 if (local_err != NULL) { 382 error_propagate(errp, local_err); 383 return; 384 } 385 386 if (cpu->cfg.priv_spec) { 387 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 388 priv_version = PRIV_VERSION_1_11_0; 389 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 390 priv_version = PRIV_VERSION_1_10_0; 391 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) { 392 priv_version = PRIV_VERSION_1_09_1; 393 } else { 394 error_setg(errp, 395 "Unsupported privilege spec version '%s'", 396 cpu->cfg.priv_spec); 397 return; 398 } 399 } 400 401 set_priv_version(env, priv_version); 402 set_resetvec(env, DEFAULT_RSTVEC); 403 404 if (cpu->cfg.mmu) { 405 set_feature(env, RISCV_FEATURE_MMU); 406 } 407 408 if (cpu->cfg.pmp) { 409 set_feature(env, RISCV_FEATURE_PMP); 410 } 411 412 /* If misa isn't set (rv32 and rv64 machines) set it here */ 413 if (!env->misa) { 414 /* Do some ISA extension error checking */ 415 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 416 error_setg(errp, 417 "I and E extensions are incompatible"); 418 return; 419 } 420 421 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 422 error_setg(errp, 423 "Either I or E extension must be set"); 424 return; 425 } 426 427 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 428 cpu->cfg.ext_a & cpu->cfg.ext_f & 429 cpu->cfg.ext_d)) { 430 warn_report("Setting G will also set IMAFD"); 431 cpu->cfg.ext_i = true; 432 cpu->cfg.ext_m = true; 433 cpu->cfg.ext_a = true; 434 cpu->cfg.ext_f = true; 435 cpu->cfg.ext_d = true; 436 } 437 438 /* Set the ISA extensions, checks should have happened above */ 439 if (cpu->cfg.ext_i) { 440 target_misa |= RVI; 441 } 442 if (cpu->cfg.ext_e) { 443 target_misa |= RVE; 444 } 445 if (cpu->cfg.ext_m) { 446 target_misa |= RVM; 447 } 448 if (cpu->cfg.ext_a) { 449 target_misa |= RVA; 450 } 451 if (cpu->cfg.ext_f) { 452 target_misa |= RVF; 453 } 454 if (cpu->cfg.ext_d) { 455 target_misa |= RVD; 456 } 457 if (cpu->cfg.ext_c) { 458 target_misa |= RVC; 459 } 460 if (cpu->cfg.ext_s) { 461 target_misa |= RVS; 462 } 463 if (cpu->cfg.ext_u) { 464 target_misa |= RVU; 465 } 466 if (cpu->cfg.ext_h) { 467 target_misa |= RVH; 468 } 469 470 set_misa(env, RVXLEN | target_misa); 471 } 472 473 riscv_cpu_register_gdb_regs_for_features(cs); 474 475 qemu_init_vcpu(cs); 476 cpu_reset(cs); 477 478 mcc->parent_realize(dev, errp); 479 } 480 481 static void riscv_cpu_init(Object *obj) 482 { 483 RISCVCPU *cpu = RISCV_CPU(obj); 484 485 cpu_set_cpustate_pointers(cpu); 486 } 487 488 #ifndef CONFIG_USER_ONLY 489 static const VMStateDescription vmstate_riscv_cpu = { 490 .name = "cpu", 491 .unmigratable = 1, 492 }; 493 #endif 494 495 static Property riscv_cpu_properties[] = { 496 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 497 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 498 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 499 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 500 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 501 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 502 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 503 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 504 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 505 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 506 /* This is experimental so mark with 'x-' */ 507 DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), 508 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 509 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 510 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 511 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 512 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 513 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 514 DEFINE_PROP_END_OF_LIST(), 515 }; 516 517 static void riscv_cpu_class_init(ObjectClass *c, void *data) 518 { 519 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 520 CPUClass *cc = CPU_CLASS(c); 521 DeviceClass *dc = DEVICE_CLASS(c); 522 523 device_class_set_parent_realize(dc, riscv_cpu_realize, 524 &mcc->parent_realize); 525 526 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 527 528 cc->class_by_name = riscv_cpu_class_by_name; 529 cc->has_work = riscv_cpu_has_work; 530 cc->do_interrupt = riscv_cpu_do_interrupt; 531 cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt; 532 cc->dump_state = riscv_cpu_dump_state; 533 cc->set_pc = riscv_cpu_set_pc; 534 cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb; 535 cc->gdb_read_register = riscv_cpu_gdb_read_register; 536 cc->gdb_write_register = riscv_cpu_gdb_write_register; 537 cc->gdb_num_core_regs = 33; 538 #if defined(TARGET_RISCV32) 539 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 540 #elif defined(TARGET_RISCV64) 541 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 542 #endif 543 cc->gdb_stop_before_watchpoint = true; 544 cc->disas_set_info = riscv_cpu_disas_set_info; 545 #ifndef CONFIG_USER_ONLY 546 cc->do_transaction_failed = riscv_cpu_do_transaction_failed; 547 cc->do_unaligned_access = riscv_cpu_do_unaligned_access; 548 cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; 549 /* For now, mark unmigratable: */ 550 cc->vmsd = &vmstate_riscv_cpu; 551 #endif 552 #ifdef CONFIG_TCG 553 cc->tcg_initialize = riscv_translate_init; 554 cc->tlb_fill = riscv_cpu_tlb_fill; 555 #endif 556 device_class_set_props(dc, riscv_cpu_properties); 557 } 558 559 char *riscv_isa_string(RISCVCPU *cpu) 560 { 561 int i; 562 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 563 char *isa_str = g_new(char, maxlen); 564 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 565 for (i = 0; i < sizeof(riscv_exts); i++) { 566 if (cpu->env.misa & RV(riscv_exts[i])) { 567 *p++ = qemu_tolower(riscv_exts[i]); 568 } 569 } 570 *p = '\0'; 571 return isa_str; 572 } 573 574 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 575 { 576 ObjectClass *class_a = (ObjectClass *)a; 577 ObjectClass *class_b = (ObjectClass *)b; 578 const char *name_a, *name_b; 579 580 name_a = object_class_get_name(class_a); 581 name_b = object_class_get_name(class_b); 582 return strcmp(name_a, name_b); 583 } 584 585 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 586 { 587 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 588 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 589 590 qemu_printf("%.*s\n", len, typename); 591 } 592 593 void riscv_cpu_list(void) 594 { 595 GSList *list; 596 597 list = object_class_get_list(TYPE_RISCV_CPU, false); 598 list = g_slist_sort(list, riscv_cpu_list_compare); 599 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 600 g_slist_free(list); 601 } 602 603 #define DEFINE_CPU(type_name, initfn) \ 604 { \ 605 .name = type_name, \ 606 .parent = TYPE_RISCV_CPU, \ 607 .instance_init = initfn \ 608 } 609 610 static const TypeInfo riscv_cpu_type_infos[] = { 611 { 612 .name = TYPE_RISCV_CPU, 613 .parent = TYPE_CPU, 614 .instance_size = sizeof(RISCVCPU), 615 .instance_init = riscv_cpu_init, 616 .abstract = true, 617 .class_size = sizeof(RISCVCPUClass), 618 .class_init = riscv_cpu_class_init, 619 }, 620 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 621 #if defined(TARGET_RISCV32) 622 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), 623 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), 624 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init), 625 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), 626 /* Depreacted */ 627 DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), 628 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init), 629 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init) 630 #elif defined(TARGET_RISCV64) 631 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), 632 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), 633 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init), 634 /* Deprecated */ 635 DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), 636 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init), 637 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init) 638 #endif 639 }; 640 641 DEFINE_TYPES(riscv_cpu_type_infos) 642