1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "qemu/error-report.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "fpu/softfloat-helpers.h" 36 #include "sysemu/kvm.h" 37 #include "kvm_riscv.h" 38 #include "tcg/tcg.h" 39 40 /* RISC-V CPU definitions */ 41 42 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 43 (QEMU_VERSION_MINOR << 8) | \ 44 (QEMU_VERSION_MICRO)) 45 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 46 47 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 48 49 struct isa_ext_data { 50 const char *name; 51 int min_version; 52 int ext_enable_offset; 53 }; 54 55 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ 56 {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 57 58 /* 59 * Here are the ordering rules of extension naming defined by RISC-V 60 * specification : 61 * 1. All extensions should be separated from other multi-letter extensions 62 * by an underscore. 63 * 2. The first letter following the 'Z' conventionally indicates the most 64 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 65 * If multiple 'Z' extensions are named, they should be ordered first 66 * by category, then alphabetically within a category. 67 * 3. Standard supervisor-level extensions (starts with 'S') should be 68 * listed after standard unprivileged extensions. If multiple 69 * supervisor-level extensions are listed, they should be ordered 70 * alphabetically. 71 * 4. Non-standard extensions (starts with 'X') must be listed after all 72 * standard extensions. They must be separated from other multi-letter 73 * extensions by an underscore. 74 * 75 * Single letter extensions are checked in riscv_cpu_validate_misa_priv() 76 * instead. 77 */ 78 static const struct isa_ext_data isa_edata_arr[] = { 79 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), 80 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), 81 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), 82 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), 83 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), 84 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), 85 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), 86 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), 87 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), 88 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), 89 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), 90 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), 91 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), 92 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), 93 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), 94 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), 95 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), 96 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), 97 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), 98 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), 99 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), 100 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), 101 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), 102 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), 103 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), 104 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), 105 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), 106 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), 107 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), 108 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), 109 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), 110 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), 111 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), 112 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), 113 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), 114 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), 115 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), 116 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), 117 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), 118 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), 119 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), 120 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), 121 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), 122 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), 123 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), 124 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), 125 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), 126 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), 127 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), 128 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), 129 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), 130 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), 131 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), 132 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), 133 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 134 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 135 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), 136 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), 137 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 138 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), 139 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), 140 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 141 }; 142 143 static bool isa_ext_is_enabled(RISCVCPU *cpu, 144 const struct isa_ext_data *edata) 145 { 146 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 147 148 return *ext_enabled; 149 } 150 151 static void isa_ext_update_enabled(RISCVCPU *cpu, 152 const struct isa_ext_data *edata, bool en) 153 { 154 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 155 156 *ext_enabled = en; 157 } 158 159 const char * const riscv_int_regnames[] = { 160 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 161 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 162 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 163 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 164 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 165 }; 166 167 const char * const riscv_int_regnamesh[] = { 168 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 169 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 170 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 171 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 172 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 173 "x30h/t5h", "x31h/t6h" 174 }; 175 176 const char * const riscv_fpr_regnames[] = { 177 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 178 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 179 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 180 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 181 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 182 "f30/ft10", "f31/ft11" 183 }; 184 185 static const char * const riscv_excp_names[] = { 186 "misaligned_fetch", 187 "fault_fetch", 188 "illegal_instruction", 189 "breakpoint", 190 "misaligned_load", 191 "fault_load", 192 "misaligned_store", 193 "fault_store", 194 "user_ecall", 195 "supervisor_ecall", 196 "hypervisor_ecall", 197 "machine_ecall", 198 "exec_page_fault", 199 "load_page_fault", 200 "reserved", 201 "store_page_fault", 202 "reserved", 203 "reserved", 204 "reserved", 205 "reserved", 206 "guest_exec_page_fault", 207 "guest_load_page_fault", 208 "reserved", 209 "guest_store_page_fault", 210 }; 211 212 static const char * const riscv_intr_names[] = { 213 "u_software", 214 "s_software", 215 "vs_software", 216 "m_software", 217 "u_timer", 218 "s_timer", 219 "vs_timer", 220 "m_timer", 221 "u_external", 222 "s_external", 223 "vs_external", 224 "m_external", 225 "reserved", 226 "reserved", 227 "reserved", 228 "reserved" 229 }; 230 231 static void riscv_cpu_add_user_properties(Object *obj); 232 233 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 234 { 235 if (async) { 236 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 237 riscv_intr_names[cause] : "(unknown)"; 238 } else { 239 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 240 riscv_excp_names[cause] : "(unknown)"; 241 } 242 } 243 244 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 245 { 246 env->misa_mxl_max = env->misa_mxl = mxl; 247 env->misa_ext_mask = env->misa_ext = ext; 248 } 249 250 #ifndef CONFIG_USER_ONLY 251 static uint8_t satp_mode_from_str(const char *satp_mode_str) 252 { 253 if (!strncmp(satp_mode_str, "mbare", 5)) { 254 return VM_1_10_MBARE; 255 } 256 257 if (!strncmp(satp_mode_str, "sv32", 4)) { 258 return VM_1_10_SV32; 259 } 260 261 if (!strncmp(satp_mode_str, "sv39", 4)) { 262 return VM_1_10_SV39; 263 } 264 265 if (!strncmp(satp_mode_str, "sv48", 4)) { 266 return VM_1_10_SV48; 267 } 268 269 if (!strncmp(satp_mode_str, "sv57", 4)) { 270 return VM_1_10_SV57; 271 } 272 273 if (!strncmp(satp_mode_str, "sv64", 4)) { 274 return VM_1_10_SV64; 275 } 276 277 g_assert_not_reached(); 278 } 279 280 uint8_t satp_mode_max_from_map(uint32_t map) 281 { 282 /* map here has at least one bit set, so no problem with clz */ 283 return 31 - __builtin_clz(map); 284 } 285 286 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) 287 { 288 if (is_32_bit) { 289 switch (satp_mode) { 290 case VM_1_10_SV32: 291 return "sv32"; 292 case VM_1_10_MBARE: 293 return "none"; 294 } 295 } else { 296 switch (satp_mode) { 297 case VM_1_10_SV64: 298 return "sv64"; 299 case VM_1_10_SV57: 300 return "sv57"; 301 case VM_1_10_SV48: 302 return "sv48"; 303 case VM_1_10_SV39: 304 return "sv39"; 305 case VM_1_10_MBARE: 306 return "none"; 307 } 308 } 309 310 g_assert_not_reached(); 311 } 312 313 static void set_satp_mode_max_supported(RISCVCPU *cpu, 314 uint8_t satp_mode) 315 { 316 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 317 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; 318 319 for (int i = 0; i <= satp_mode; ++i) { 320 if (valid_vm[i]) { 321 cpu->cfg.satp_mode.supported |= (1 << i); 322 } 323 } 324 } 325 326 /* Set the satp mode to the max supported */ 327 static void set_satp_mode_default_map(RISCVCPU *cpu) 328 { 329 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; 330 } 331 #endif 332 333 static void riscv_any_cpu_init(Object *obj) 334 { 335 CPURISCVState *env = &RISCV_CPU(obj)->env; 336 #if defined(TARGET_RISCV32) 337 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 338 #elif defined(TARGET_RISCV64) 339 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 340 #endif 341 342 #ifndef CONFIG_USER_ONLY 343 set_satp_mode_max_supported(RISCV_CPU(obj), 344 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? 345 VM_1_10_SV32 : VM_1_10_SV57); 346 #endif 347 348 env->priv_ver = PRIV_VERSION_1_12_0; 349 } 350 351 #if defined(TARGET_RISCV64) 352 static void rv64_base_cpu_init(Object *obj) 353 { 354 CPURISCVState *env = &RISCV_CPU(obj)->env; 355 /* We set this in the realise function */ 356 set_misa(env, MXL_RV64, 0); 357 riscv_cpu_add_user_properties(obj); 358 /* Set latest version of privileged specification */ 359 env->priv_ver = PRIV_VERSION_1_12_0; 360 #ifndef CONFIG_USER_ONLY 361 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 362 #endif 363 } 364 365 static void rv64_sifive_u_cpu_init(Object *obj) 366 { 367 CPURISCVState *env = &RISCV_CPU(obj)->env; 368 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 369 env->priv_ver = PRIV_VERSION_1_10_0; 370 #ifndef CONFIG_USER_ONLY 371 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); 372 #endif 373 } 374 375 static void rv64_sifive_e_cpu_init(Object *obj) 376 { 377 CPURISCVState *env = &RISCV_CPU(obj)->env; 378 RISCVCPU *cpu = RISCV_CPU(obj); 379 380 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 381 env->priv_ver = PRIV_VERSION_1_10_0; 382 cpu->cfg.mmu = false; 383 #ifndef CONFIG_USER_ONLY 384 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 385 #endif 386 } 387 388 static void rv64_thead_c906_cpu_init(Object *obj) 389 { 390 CPURISCVState *env = &RISCV_CPU(obj)->env; 391 RISCVCPU *cpu = RISCV_CPU(obj); 392 393 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); 394 env->priv_ver = PRIV_VERSION_1_11_0; 395 396 cpu->cfg.ext_zfh = true; 397 cpu->cfg.mmu = true; 398 cpu->cfg.ext_xtheadba = true; 399 cpu->cfg.ext_xtheadbb = true; 400 cpu->cfg.ext_xtheadbs = true; 401 cpu->cfg.ext_xtheadcmo = true; 402 cpu->cfg.ext_xtheadcondmov = true; 403 cpu->cfg.ext_xtheadfmemidx = true; 404 cpu->cfg.ext_xtheadmac = true; 405 cpu->cfg.ext_xtheadmemidx = true; 406 cpu->cfg.ext_xtheadmempair = true; 407 cpu->cfg.ext_xtheadsync = true; 408 409 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 410 #ifndef CONFIG_USER_ONLY 411 set_satp_mode_max_supported(cpu, VM_1_10_SV39); 412 #endif 413 } 414 415 static void rv64_veyron_v1_cpu_init(Object *obj) 416 { 417 CPURISCVState *env = &RISCV_CPU(obj)->env; 418 RISCVCPU *cpu = RISCV_CPU(obj); 419 420 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); 421 env->priv_ver = PRIV_VERSION_1_12_0; 422 423 /* Enable ISA extensions */ 424 cpu->cfg.mmu = true; 425 cpu->cfg.ext_icbom = true; 426 cpu->cfg.cbom_blocksize = 64; 427 cpu->cfg.cboz_blocksize = 64; 428 cpu->cfg.ext_icboz = true; 429 cpu->cfg.ext_smaia = true; 430 cpu->cfg.ext_ssaia = true; 431 cpu->cfg.ext_sscofpmf = true; 432 cpu->cfg.ext_sstc = true; 433 cpu->cfg.ext_svinval = true; 434 cpu->cfg.ext_svnapot = true; 435 cpu->cfg.ext_svpbmt = true; 436 cpu->cfg.ext_smstateen = true; 437 cpu->cfg.ext_zba = true; 438 cpu->cfg.ext_zbb = true; 439 cpu->cfg.ext_zbc = true; 440 cpu->cfg.ext_zbs = true; 441 cpu->cfg.ext_XVentanaCondOps = true; 442 443 cpu->cfg.mvendorid = VEYRON_V1_MVENDORID; 444 cpu->cfg.marchid = VEYRON_V1_MARCHID; 445 cpu->cfg.mimpid = VEYRON_V1_MIMPID; 446 447 #ifndef CONFIG_USER_ONLY 448 set_satp_mode_max_supported(cpu, VM_1_10_SV48); 449 #endif 450 } 451 452 static void rv128_base_cpu_init(Object *obj) 453 { 454 if (qemu_tcg_mttcg_enabled()) { 455 /* Missing 128-bit aligned atomics */ 456 error_report("128-bit RISC-V currently does not work with Multi " 457 "Threaded TCG. Please use: -accel tcg,thread=single"); 458 exit(EXIT_FAILURE); 459 } 460 CPURISCVState *env = &RISCV_CPU(obj)->env; 461 /* We set this in the realise function */ 462 set_misa(env, MXL_RV128, 0); 463 riscv_cpu_add_user_properties(obj); 464 /* Set latest version of privileged specification */ 465 env->priv_ver = PRIV_VERSION_1_12_0; 466 #ifndef CONFIG_USER_ONLY 467 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 468 #endif 469 } 470 #else 471 static void rv32_base_cpu_init(Object *obj) 472 { 473 CPURISCVState *env = &RISCV_CPU(obj)->env; 474 /* We set this in the realise function */ 475 set_misa(env, MXL_RV32, 0); 476 riscv_cpu_add_user_properties(obj); 477 /* Set latest version of privileged specification */ 478 env->priv_ver = PRIV_VERSION_1_12_0; 479 #ifndef CONFIG_USER_ONLY 480 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 481 #endif 482 } 483 484 static void rv32_sifive_u_cpu_init(Object *obj) 485 { 486 CPURISCVState *env = &RISCV_CPU(obj)->env; 487 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 488 env->priv_ver = PRIV_VERSION_1_10_0; 489 #ifndef CONFIG_USER_ONLY 490 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 491 #endif 492 } 493 494 static void rv32_sifive_e_cpu_init(Object *obj) 495 { 496 CPURISCVState *env = &RISCV_CPU(obj)->env; 497 RISCVCPU *cpu = RISCV_CPU(obj); 498 499 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 500 env->priv_ver = PRIV_VERSION_1_10_0; 501 cpu->cfg.mmu = false; 502 #ifndef CONFIG_USER_ONLY 503 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 504 #endif 505 } 506 507 static void rv32_ibex_cpu_init(Object *obj) 508 { 509 CPURISCVState *env = &RISCV_CPU(obj)->env; 510 RISCVCPU *cpu = RISCV_CPU(obj); 511 512 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 513 env->priv_ver = PRIV_VERSION_1_11_0; 514 cpu->cfg.mmu = false; 515 #ifndef CONFIG_USER_ONLY 516 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 517 #endif 518 cpu->cfg.epmp = true; 519 } 520 521 static void rv32_imafcu_nommu_cpu_init(Object *obj) 522 { 523 CPURISCVState *env = &RISCV_CPU(obj)->env; 524 RISCVCPU *cpu = RISCV_CPU(obj); 525 526 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 527 env->priv_ver = PRIV_VERSION_1_10_0; 528 cpu->cfg.mmu = false; 529 #ifndef CONFIG_USER_ONLY 530 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 531 #endif 532 } 533 #endif 534 535 #if defined(CONFIG_KVM) 536 static void riscv_host_cpu_init(Object *obj) 537 { 538 CPURISCVState *env = &RISCV_CPU(obj)->env; 539 #if defined(TARGET_RISCV32) 540 set_misa(env, MXL_RV32, 0); 541 #elif defined(TARGET_RISCV64) 542 set_misa(env, MXL_RV64, 0); 543 #endif 544 riscv_cpu_add_user_properties(obj); 545 } 546 #endif 547 548 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 549 { 550 ObjectClass *oc; 551 char *typename; 552 char **cpuname; 553 554 cpuname = g_strsplit(cpu_model, ",", 1); 555 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 556 oc = object_class_by_name(typename); 557 g_strfreev(cpuname); 558 g_free(typename); 559 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 560 object_class_is_abstract(oc)) { 561 return NULL; 562 } 563 return oc; 564 } 565 566 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 567 { 568 RISCVCPU *cpu = RISCV_CPU(cs); 569 CPURISCVState *env = &cpu->env; 570 int i; 571 572 #if !defined(CONFIG_USER_ONLY) 573 if (riscv_has_ext(env, RVH)) { 574 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); 575 } 576 #endif 577 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 578 #ifndef CONFIG_USER_ONLY 579 { 580 static const int dump_csrs[] = { 581 CSR_MHARTID, 582 CSR_MSTATUS, 583 CSR_MSTATUSH, 584 /* 585 * CSR_SSTATUS is intentionally omitted here as its value 586 * can be figured out by looking at CSR_MSTATUS 587 */ 588 CSR_HSTATUS, 589 CSR_VSSTATUS, 590 CSR_MIP, 591 CSR_MIE, 592 CSR_MIDELEG, 593 CSR_HIDELEG, 594 CSR_MEDELEG, 595 CSR_HEDELEG, 596 CSR_MTVEC, 597 CSR_STVEC, 598 CSR_VSTVEC, 599 CSR_MEPC, 600 CSR_SEPC, 601 CSR_VSEPC, 602 CSR_MCAUSE, 603 CSR_SCAUSE, 604 CSR_VSCAUSE, 605 CSR_MTVAL, 606 CSR_STVAL, 607 CSR_HTVAL, 608 CSR_MTVAL2, 609 CSR_MSCRATCH, 610 CSR_SSCRATCH, 611 CSR_SATP, 612 CSR_MMTE, 613 CSR_UPMBASE, 614 CSR_UPMMASK, 615 CSR_SPMBASE, 616 CSR_SPMMASK, 617 CSR_MPMBASE, 618 CSR_MPMMASK, 619 }; 620 621 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 622 int csrno = dump_csrs[i]; 623 target_ulong val = 0; 624 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 625 626 /* 627 * Rely on the smode, hmode, etc, predicates within csr.c 628 * to do the filtering of the registers that are present. 629 */ 630 if (res == RISCV_EXCP_NONE) { 631 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 632 csr_ops[csrno].name, val); 633 } 634 } 635 } 636 #endif 637 638 for (i = 0; i < 32; i++) { 639 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 640 riscv_int_regnames[i], env->gpr[i]); 641 if ((i & 3) == 3) { 642 qemu_fprintf(f, "\n"); 643 } 644 } 645 if (flags & CPU_DUMP_FPU) { 646 for (i = 0; i < 32; i++) { 647 qemu_fprintf(f, " %-8s %016" PRIx64, 648 riscv_fpr_regnames[i], env->fpr[i]); 649 if ((i & 3) == 3) { 650 qemu_fprintf(f, "\n"); 651 } 652 } 653 } 654 } 655 656 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 657 { 658 RISCVCPU *cpu = RISCV_CPU(cs); 659 CPURISCVState *env = &cpu->env; 660 661 if (env->xl == MXL_RV32) { 662 env->pc = (int32_t)value; 663 } else { 664 env->pc = value; 665 } 666 } 667 668 static vaddr riscv_cpu_get_pc(CPUState *cs) 669 { 670 RISCVCPU *cpu = RISCV_CPU(cs); 671 CPURISCVState *env = &cpu->env; 672 673 /* Match cpu_get_tb_cpu_state. */ 674 if (env->xl == MXL_RV32) { 675 return env->pc & UINT32_MAX; 676 } 677 return env->pc; 678 } 679 680 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 681 const TranslationBlock *tb) 682 { 683 RISCVCPU *cpu = RISCV_CPU(cs); 684 CPURISCVState *env = &cpu->env; 685 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 686 687 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 688 689 if (xl == MXL_RV32) { 690 env->pc = (int32_t) tb->pc; 691 } else { 692 env->pc = tb->pc; 693 } 694 } 695 696 static bool riscv_cpu_has_work(CPUState *cs) 697 { 698 #ifndef CONFIG_USER_ONLY 699 RISCVCPU *cpu = RISCV_CPU(cs); 700 CPURISCVState *env = &cpu->env; 701 /* 702 * Definition of the WFI instruction requires it to ignore the privilege 703 * mode and delegation registers, but respect individual enables 704 */ 705 return riscv_cpu_all_pending(env) != 0; 706 #else 707 return true; 708 #endif 709 } 710 711 static void riscv_restore_state_to_opc(CPUState *cs, 712 const TranslationBlock *tb, 713 const uint64_t *data) 714 { 715 RISCVCPU *cpu = RISCV_CPU(cs); 716 CPURISCVState *env = &cpu->env; 717 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 718 719 if (xl == MXL_RV32) { 720 env->pc = (int32_t)data[0]; 721 } else { 722 env->pc = data[0]; 723 } 724 env->bins = data[1]; 725 } 726 727 static void riscv_cpu_reset_hold(Object *obj) 728 { 729 #ifndef CONFIG_USER_ONLY 730 uint8_t iprio; 731 int i, irq, rdzero; 732 #endif 733 CPUState *cs = CPU(obj); 734 RISCVCPU *cpu = RISCV_CPU(cs); 735 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 736 CPURISCVState *env = &cpu->env; 737 738 if (mcc->parent_phases.hold) { 739 mcc->parent_phases.hold(obj); 740 } 741 #ifndef CONFIG_USER_ONLY 742 env->misa_mxl = env->misa_mxl_max; 743 env->priv = PRV_M; 744 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 745 if (env->misa_mxl > MXL_RV32) { 746 /* 747 * The reset status of SXL/UXL is undefined, but mstatus is WARL 748 * and we must ensure that the value after init is valid for read. 749 */ 750 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 751 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 752 if (riscv_has_ext(env, RVH)) { 753 env->vsstatus = set_field(env->vsstatus, 754 MSTATUS64_SXL, env->misa_mxl); 755 env->vsstatus = set_field(env->vsstatus, 756 MSTATUS64_UXL, env->misa_mxl); 757 env->mstatus_hs = set_field(env->mstatus_hs, 758 MSTATUS64_SXL, env->misa_mxl); 759 env->mstatus_hs = set_field(env->mstatus_hs, 760 MSTATUS64_UXL, env->misa_mxl); 761 } 762 } 763 env->mcause = 0; 764 env->miclaim = MIP_SGEIP; 765 env->pc = env->resetvec; 766 env->bins = 0; 767 env->two_stage_lookup = false; 768 769 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | 770 (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); 771 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | 772 (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); 773 774 /* Initialized default priorities of local interrupts. */ 775 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 776 iprio = riscv_cpu_default_priority(i); 777 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 778 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 779 env->hviprio[i] = 0; 780 } 781 i = 0; 782 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 783 if (!rdzero) { 784 env->hviprio[irq] = env->miprio[irq]; 785 } 786 i++; 787 } 788 /* mmte is supposed to have pm.current hardwired to 1 */ 789 env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); 790 #endif 791 env->xl = riscv_cpu_mxl(env); 792 riscv_cpu_update_mask(env); 793 cs->exception_index = RISCV_EXCP_NONE; 794 env->load_res = -1; 795 set_default_nan_mode(1, &env->fp_status); 796 797 #ifndef CONFIG_USER_ONLY 798 if (cpu->cfg.debug) { 799 riscv_trigger_init(env); 800 } 801 802 if (kvm_enabled()) { 803 kvm_riscv_reset_vcpu(cpu); 804 } 805 #endif 806 } 807 808 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 809 { 810 RISCVCPU *cpu = RISCV_CPU(s); 811 812 switch (riscv_cpu_mxl(&cpu->env)) { 813 case MXL_RV32: 814 info->print_insn = print_insn_riscv32; 815 break; 816 case MXL_RV64: 817 info->print_insn = print_insn_riscv64; 818 break; 819 case MXL_RV128: 820 info->print_insn = print_insn_riscv128; 821 break; 822 default: 823 g_assert_not_reached(); 824 } 825 } 826 827 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 828 Error **errp) 829 { 830 int vext_version = VEXT_VERSION_1_00_0; 831 832 if (!is_power_of_2(cfg->vlen)) { 833 error_setg(errp, "Vector extension VLEN must be power of 2"); 834 return; 835 } 836 if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { 837 error_setg(errp, 838 "Vector extension implementation only supports VLEN " 839 "in the range [128, %d]", RV_VLEN_MAX); 840 return; 841 } 842 if (!is_power_of_2(cfg->elen)) { 843 error_setg(errp, "Vector extension ELEN must be power of 2"); 844 return; 845 } 846 if (cfg->elen > 64 || cfg->elen < 8) { 847 error_setg(errp, 848 "Vector extension implementation only supports ELEN " 849 "in the range [8, 64]"); 850 return; 851 } 852 if (cfg->vext_spec) { 853 if (!g_strcmp0(cfg->vext_spec, "v1.0")) { 854 vext_version = VEXT_VERSION_1_00_0; 855 } else { 856 error_setg(errp, "Unsupported vector spec version '%s'", 857 cfg->vext_spec); 858 return; 859 } 860 } else { 861 qemu_log("vector version is not specified, " 862 "use the default value v1.0\n"); 863 } 864 env->vext_ver = vext_version; 865 } 866 867 /* 868 * Check consistency between chosen extensions while setting 869 * cpu->cfg accordingly. 870 */ 871 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 872 { 873 CPURISCVState *env = &cpu->env; 874 Error *local_err = NULL; 875 876 /* Do some ISA extension error checking */ 877 if (riscv_has_ext(env, RVG) && 878 !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && 879 riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && 880 riscv_has_ext(env, RVD) && 881 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 882 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 883 cpu->cfg.ext_icsr = true; 884 cpu->cfg.ext_ifencei = true; 885 886 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; 887 env->misa_ext_mask = env->misa_ext; 888 } 889 890 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 891 error_setg(errp, 892 "I and E extensions are incompatible"); 893 return; 894 } 895 896 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 897 error_setg(errp, 898 "Either I or E extension must be set"); 899 return; 900 } 901 902 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 903 error_setg(errp, 904 "Setting S extension without U extension is illegal"); 905 return; 906 } 907 908 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 909 error_setg(errp, 910 "H depends on an I base integer ISA with 32 x registers"); 911 return; 912 } 913 914 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 915 error_setg(errp, "H extension implicitly requires S-mode"); 916 return; 917 } 918 919 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { 920 error_setg(errp, "F extension requires Zicsr"); 921 return; 922 } 923 924 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 925 error_setg(errp, "Zawrs extension requires A extension"); 926 return; 927 } 928 929 if (cpu->cfg.ext_zfh) { 930 cpu->cfg.ext_zfhmin = true; 931 } 932 933 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 934 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 935 return; 936 } 937 938 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 939 error_setg(errp, "D extension requires F extension"); 940 return; 941 } 942 943 if (riscv_has_ext(env, RVV)) { 944 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 945 if (local_err != NULL) { 946 error_propagate(errp, local_err); 947 return; 948 } 949 950 /* The V vector extension depends on the Zve64d extension */ 951 cpu->cfg.ext_zve64d = true; 952 } 953 954 /* The Zve64d extension depends on the Zve64f extension */ 955 if (cpu->cfg.ext_zve64d) { 956 cpu->cfg.ext_zve64f = true; 957 } 958 959 /* The Zve64f extension depends on the Zve32f extension */ 960 if (cpu->cfg.ext_zve64f) { 961 cpu->cfg.ext_zve32f = true; 962 } 963 964 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 965 error_setg(errp, "Zve64d/V extensions require D extension"); 966 return; 967 } 968 969 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 970 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 971 return; 972 } 973 974 if (cpu->cfg.ext_zvfh) { 975 cpu->cfg.ext_zvfhmin = true; 976 } 977 978 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 979 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 980 return; 981 } 982 983 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 984 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 985 return; 986 } 987 988 /* Set the ISA extensions, checks should have happened above */ 989 if (cpu->cfg.ext_zhinx) { 990 cpu->cfg.ext_zhinxmin = true; 991 } 992 993 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 994 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 995 return; 996 } 997 998 if (cpu->cfg.ext_zfinx) { 999 if (!cpu->cfg.ext_icsr) { 1000 error_setg(errp, "Zfinx extension requires Zicsr"); 1001 return; 1002 } 1003 if (riscv_has_ext(env, RVF)) { 1004 error_setg(errp, 1005 "Zfinx cannot be supported together with F extension"); 1006 return; 1007 } 1008 } 1009 1010 if (cpu->cfg.ext_zce) { 1011 cpu->cfg.ext_zca = true; 1012 cpu->cfg.ext_zcb = true; 1013 cpu->cfg.ext_zcmp = true; 1014 cpu->cfg.ext_zcmt = true; 1015 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 1016 cpu->cfg.ext_zcf = true; 1017 } 1018 } 1019 1020 if (riscv_has_ext(env, RVC)) { 1021 cpu->cfg.ext_zca = true; 1022 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 1023 cpu->cfg.ext_zcf = true; 1024 } 1025 if (riscv_has_ext(env, RVD)) { 1026 cpu->cfg.ext_zcd = true; 1027 } 1028 } 1029 1030 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 1031 error_setg(errp, "Zcf extension is only relevant to RV32"); 1032 return; 1033 } 1034 1035 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 1036 error_setg(errp, "Zcf extension requires F extension"); 1037 return; 1038 } 1039 1040 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 1041 error_setg(errp, "Zcd extension requires D extension"); 1042 return; 1043 } 1044 1045 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 1046 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 1047 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 1048 "extension"); 1049 return; 1050 } 1051 1052 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 1053 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 1054 "Zcd extension"); 1055 return; 1056 } 1057 1058 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { 1059 error_setg(errp, "Zcmt extension requires Zicsr extension"); 1060 return; 1061 } 1062 1063 if (cpu->cfg.ext_zk) { 1064 cpu->cfg.ext_zkn = true; 1065 cpu->cfg.ext_zkr = true; 1066 cpu->cfg.ext_zkt = true; 1067 } 1068 1069 if (cpu->cfg.ext_zkn) { 1070 cpu->cfg.ext_zbkb = true; 1071 cpu->cfg.ext_zbkc = true; 1072 cpu->cfg.ext_zbkx = true; 1073 cpu->cfg.ext_zkne = true; 1074 cpu->cfg.ext_zknd = true; 1075 cpu->cfg.ext_zknh = true; 1076 } 1077 1078 if (cpu->cfg.ext_zks) { 1079 cpu->cfg.ext_zbkb = true; 1080 cpu->cfg.ext_zbkc = true; 1081 cpu->cfg.ext_zbkx = true; 1082 cpu->cfg.ext_zksed = true; 1083 cpu->cfg.ext_zksh = true; 1084 } 1085 } 1086 1087 #ifndef CONFIG_USER_ONLY 1088 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) 1089 { 1090 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 1091 uint8_t satp_mode_map_max; 1092 uint8_t satp_mode_supported_max = 1093 satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 1094 1095 if (cpu->cfg.satp_mode.map == 0) { 1096 if (cpu->cfg.satp_mode.init == 0) { 1097 /* If unset by the user, we fallback to the default satp mode. */ 1098 set_satp_mode_default_map(cpu); 1099 } else { 1100 /* 1101 * Find the lowest level that was disabled and then enable the 1102 * first valid level below which can be found in 1103 * valid_vm_1_10_32/64. 1104 */ 1105 for (int i = 1; i < 16; ++i) { 1106 if ((cpu->cfg.satp_mode.init & (1 << i)) && 1107 (cpu->cfg.satp_mode.supported & (1 << i))) { 1108 for (int j = i - 1; j >= 0; --j) { 1109 if (cpu->cfg.satp_mode.supported & (1 << j)) { 1110 cpu->cfg.satp_mode.map |= (1 << j); 1111 break; 1112 } 1113 } 1114 break; 1115 } 1116 } 1117 } 1118 } 1119 1120 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 1121 1122 /* Make sure the user asked for a supported configuration (HW and qemu) */ 1123 if (satp_mode_map_max > satp_mode_supported_max) { 1124 error_setg(errp, "satp_mode %s is higher than hw max capability %s", 1125 satp_mode_str(satp_mode_map_max, rv32), 1126 satp_mode_str(satp_mode_supported_max, rv32)); 1127 return; 1128 } 1129 1130 /* 1131 * Make sure the user did not ask for an invalid configuration as per 1132 * the specification. 1133 */ 1134 if (!rv32) { 1135 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1136 if (!(cpu->cfg.satp_mode.map & (1 << i)) && 1137 (cpu->cfg.satp_mode.init & (1 << i)) && 1138 (cpu->cfg.satp_mode.supported & (1 << i))) { 1139 error_setg(errp, "cannot disable %s satp mode if %s " 1140 "is enabled", satp_mode_str(i, false), 1141 satp_mode_str(satp_mode_map_max, false)); 1142 return; 1143 } 1144 } 1145 } 1146 1147 /* Finally expand the map so that all valid modes are set */ 1148 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1149 if (cpu->cfg.satp_mode.supported & (1 << i)) { 1150 cpu->cfg.satp_mode.map |= (1 << i); 1151 } 1152 } 1153 } 1154 #endif 1155 1156 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1157 { 1158 #ifndef CONFIG_USER_ONLY 1159 Error *local_err = NULL; 1160 1161 riscv_cpu_satp_mode_finalize(cpu, &local_err); 1162 if (local_err != NULL) { 1163 error_propagate(errp, local_err); 1164 return; 1165 } 1166 #endif 1167 } 1168 1169 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 1170 { 1171 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 1172 error_setg(errp, "H extension requires priv spec 1.12.0"); 1173 return; 1174 } 1175 } 1176 1177 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 1178 { 1179 CPUState *cs = CPU(dev); 1180 RISCVCPU *cpu = RISCV_CPU(dev); 1181 CPURISCVState *env = &cpu->env; 1182 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 1183 CPUClass *cc = CPU_CLASS(mcc); 1184 int i, priv_version = -1; 1185 Error *local_err = NULL; 1186 1187 cpu_exec_realizefn(cs, &local_err); 1188 if (local_err != NULL) { 1189 error_propagate(errp, local_err); 1190 return; 1191 } 1192 1193 if (cpu->cfg.priv_spec) { 1194 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 1195 priv_version = PRIV_VERSION_1_12_0; 1196 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 1197 priv_version = PRIV_VERSION_1_11_0; 1198 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 1199 priv_version = PRIV_VERSION_1_10_0; 1200 } else { 1201 error_setg(errp, 1202 "Unsupported privilege spec version '%s'", 1203 cpu->cfg.priv_spec); 1204 return; 1205 } 1206 } 1207 1208 if (priv_version >= PRIV_VERSION_1_10_0) { 1209 env->priv_ver = priv_version; 1210 } 1211 1212 riscv_cpu_validate_misa_priv(env, &local_err); 1213 if (local_err != NULL) { 1214 error_propagate(errp, local_err); 1215 return; 1216 } 1217 1218 /* Force disable extensions if priv spec version does not match */ 1219 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1220 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 1221 (env->priv_ver < isa_edata_arr[i].min_version)) { 1222 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 1223 #ifndef CONFIG_USER_ONLY 1224 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 1225 " because privilege spec version does not match", 1226 isa_edata_arr[i].name, env->mhartid); 1227 #else 1228 warn_report("disabling %s extension because " 1229 "privilege spec version does not match", 1230 isa_edata_arr[i].name); 1231 #endif 1232 } 1233 } 1234 1235 if (cpu->cfg.epmp && !cpu->cfg.pmp) { 1236 /* 1237 * Enhanced PMP should only be available 1238 * on harts with PMP support 1239 */ 1240 error_setg(errp, "Invalid configuration: EPMP requires PMP support"); 1241 return; 1242 } 1243 1244 1245 #ifndef CONFIG_USER_ONLY 1246 if (cpu->cfg.ext_sstc) { 1247 riscv_timer_init(cpu); 1248 } 1249 #endif /* CONFIG_USER_ONLY */ 1250 1251 /* Validate that MISA_MXL is set properly. */ 1252 switch (env->misa_mxl_max) { 1253 #ifdef TARGET_RISCV64 1254 case MXL_RV64: 1255 case MXL_RV128: 1256 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 1257 break; 1258 #endif 1259 case MXL_RV32: 1260 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 1261 break; 1262 default: 1263 g_assert_not_reached(); 1264 } 1265 assert(env->misa_mxl_max == env->misa_mxl); 1266 1267 riscv_cpu_validate_set_extensions(cpu, &local_err); 1268 if (local_err != NULL) { 1269 error_propagate(errp, local_err); 1270 return; 1271 } 1272 1273 #ifndef CONFIG_USER_ONLY 1274 if (cpu->cfg.pmu_num) { 1275 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 1276 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1277 riscv_pmu_timer_cb, cpu); 1278 } 1279 } 1280 #endif 1281 1282 riscv_cpu_finalize_features(cpu, &local_err); 1283 if (local_err != NULL) { 1284 error_propagate(errp, local_err); 1285 return; 1286 } 1287 1288 riscv_cpu_register_gdb_regs_for_features(cs); 1289 1290 qemu_init_vcpu(cs); 1291 cpu_reset(cs); 1292 1293 mcc->parent_realize(dev, errp); 1294 } 1295 1296 #ifndef CONFIG_USER_ONLY 1297 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, 1298 void *opaque, Error **errp) 1299 { 1300 RISCVSATPMap *satp_map = opaque; 1301 uint8_t satp = satp_mode_from_str(name); 1302 bool value; 1303 1304 value = satp_map->map & (1 << satp); 1305 1306 visit_type_bool(v, name, &value, errp); 1307 } 1308 1309 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, 1310 void *opaque, Error **errp) 1311 { 1312 RISCVSATPMap *satp_map = opaque; 1313 uint8_t satp = satp_mode_from_str(name); 1314 bool value; 1315 1316 if (!visit_type_bool(v, name, &value, errp)) { 1317 return; 1318 } 1319 1320 satp_map->map = deposit32(satp_map->map, satp, 1, value); 1321 satp_map->init |= 1 << satp; 1322 } 1323 1324 static void riscv_add_satp_mode_properties(Object *obj) 1325 { 1326 RISCVCPU *cpu = RISCV_CPU(obj); 1327 1328 if (cpu->env.misa_mxl == MXL_RV32) { 1329 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, 1330 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1331 } else { 1332 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, 1333 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1334 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, 1335 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1336 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, 1337 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1338 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, 1339 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1340 } 1341 } 1342 1343 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1344 { 1345 RISCVCPU *cpu = RISCV_CPU(opaque); 1346 CPURISCVState *env = &cpu->env; 1347 1348 if (irq < IRQ_LOCAL_MAX) { 1349 switch (irq) { 1350 case IRQ_U_SOFT: 1351 case IRQ_S_SOFT: 1352 case IRQ_VS_SOFT: 1353 case IRQ_M_SOFT: 1354 case IRQ_U_TIMER: 1355 case IRQ_S_TIMER: 1356 case IRQ_VS_TIMER: 1357 case IRQ_M_TIMER: 1358 case IRQ_U_EXT: 1359 case IRQ_VS_EXT: 1360 case IRQ_M_EXT: 1361 if (kvm_enabled()) { 1362 kvm_riscv_set_irq(cpu, irq, level); 1363 } else { 1364 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); 1365 } 1366 break; 1367 case IRQ_S_EXT: 1368 if (kvm_enabled()) { 1369 kvm_riscv_set_irq(cpu, irq, level); 1370 } else { 1371 env->external_seip = level; 1372 riscv_cpu_update_mip(env, 1 << irq, 1373 BOOL_TO_MASK(level | env->software_seip)); 1374 } 1375 break; 1376 default: 1377 g_assert_not_reached(); 1378 } 1379 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1380 /* Require H-extension for handling guest local interrupts */ 1381 if (!riscv_has_ext(env, RVH)) { 1382 g_assert_not_reached(); 1383 } 1384 1385 /* Compute bit position in HGEIP CSR */ 1386 irq = irq - IRQ_LOCAL_MAX + 1; 1387 if (env->geilen < irq) { 1388 g_assert_not_reached(); 1389 } 1390 1391 /* Update HGEIP CSR */ 1392 env->hgeip &= ~((target_ulong)1 << irq); 1393 if (level) { 1394 env->hgeip |= (target_ulong)1 << irq; 1395 } 1396 1397 /* Update mip.SGEIP bit */ 1398 riscv_cpu_update_mip(env, MIP_SGEIP, 1399 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1400 } else { 1401 g_assert_not_reached(); 1402 } 1403 } 1404 #endif /* CONFIG_USER_ONLY */ 1405 1406 static void riscv_cpu_init(Object *obj) 1407 { 1408 RISCVCPU *cpu = RISCV_CPU(obj); 1409 1410 cpu->cfg.ext_ifencei = true; 1411 cpu->cfg.ext_icsr = true; 1412 cpu->cfg.mmu = true; 1413 cpu->cfg.pmp = true; 1414 1415 cpu_set_cpustate_pointers(cpu); 1416 1417 #ifndef CONFIG_USER_ONLY 1418 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1419 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1420 #endif /* CONFIG_USER_ONLY */ 1421 } 1422 1423 typedef struct RISCVCPUMisaExtConfig { 1424 const char *name; 1425 const char *description; 1426 target_ulong misa_bit; 1427 bool enabled; 1428 } RISCVCPUMisaExtConfig; 1429 1430 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1431 void *opaque, Error **errp) 1432 { 1433 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1434 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1435 RISCVCPU *cpu = RISCV_CPU(obj); 1436 CPURISCVState *env = &cpu->env; 1437 bool value; 1438 1439 if (!visit_type_bool(v, name, &value, errp)) { 1440 return; 1441 } 1442 1443 if (value) { 1444 env->misa_ext |= misa_bit; 1445 env->misa_ext_mask |= misa_bit; 1446 } else { 1447 env->misa_ext &= ~misa_bit; 1448 env->misa_ext_mask &= ~misa_bit; 1449 } 1450 } 1451 1452 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1453 void *opaque, Error **errp) 1454 { 1455 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1456 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1457 RISCVCPU *cpu = RISCV_CPU(obj); 1458 CPURISCVState *env = &cpu->env; 1459 bool value; 1460 1461 value = env->misa_ext & misa_bit; 1462 1463 visit_type_bool(v, name, &value, errp); 1464 } 1465 1466 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1467 {.name = "a", .description = "Atomic instructions", 1468 .misa_bit = RVA, .enabled = true}, 1469 {.name = "c", .description = "Compressed instructions", 1470 .misa_bit = RVC, .enabled = true}, 1471 {.name = "d", .description = "Double-precision float point", 1472 .misa_bit = RVD, .enabled = true}, 1473 {.name = "f", .description = "Single-precision float point", 1474 .misa_bit = RVF, .enabled = true}, 1475 {.name = "i", .description = "Base integer instruction set", 1476 .misa_bit = RVI, .enabled = true}, 1477 {.name = "e", .description = "Base integer instruction set (embedded)", 1478 .misa_bit = RVE, .enabled = false}, 1479 {.name = "m", .description = "Integer multiplication and division", 1480 .misa_bit = RVM, .enabled = true}, 1481 {.name = "s", .description = "Supervisor-level instructions", 1482 .misa_bit = RVS, .enabled = true}, 1483 {.name = "u", .description = "User-level instructions", 1484 .misa_bit = RVU, .enabled = true}, 1485 {.name = "h", .description = "Hypervisor", 1486 .misa_bit = RVH, .enabled = true}, 1487 {.name = "x-j", .description = "Dynamic translated languages", 1488 .misa_bit = RVJ, .enabled = false}, 1489 {.name = "v", .description = "Vector operations", 1490 .misa_bit = RVV, .enabled = false}, 1491 {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)", 1492 .misa_bit = RVG, .enabled = false}, 1493 }; 1494 1495 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1496 { 1497 int i; 1498 1499 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1500 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1501 1502 object_property_add(cpu_obj, misa_cfg->name, "bool", 1503 cpu_get_misa_ext_cfg, 1504 cpu_set_misa_ext_cfg, 1505 NULL, (void *)misa_cfg); 1506 object_property_set_description(cpu_obj, misa_cfg->name, 1507 misa_cfg->description); 1508 object_property_set_bool(cpu_obj, misa_cfg->name, 1509 misa_cfg->enabled, NULL); 1510 } 1511 } 1512 1513 static Property riscv_cpu_extensions[] = { 1514 /* Defaults for standard extensions */ 1515 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1516 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1517 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1518 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1519 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1520 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1521 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1522 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1523 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1524 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1525 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), 1526 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1527 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1528 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1529 1530 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1531 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1532 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1533 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1534 1535 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), 1536 1537 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1538 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1539 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1540 1541 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1542 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1543 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1544 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1545 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1546 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1547 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1548 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1549 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1550 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1551 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1552 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1553 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1554 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1555 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1556 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1557 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1558 1559 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1560 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1561 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1562 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1563 1564 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), 1565 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), 1566 DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), 1567 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), 1568 1569 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1570 1571 DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false), 1572 DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false), 1573 DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false), 1574 DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false), 1575 DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), 1576 DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), 1577 DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), 1578 1579 /* Vendor-specific custom extensions */ 1580 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1581 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1582 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1583 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1584 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1585 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1586 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1587 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1588 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1589 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1590 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1591 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1592 1593 /* These are experimental so mark with 'x-' */ 1594 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), 1595 1596 /* ePMP 0.9.3 */ 1597 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1598 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1599 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1600 1601 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), 1602 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), 1603 1604 DEFINE_PROP_END_OF_LIST(), 1605 }; 1606 1607 /* 1608 * Add CPU properties with user-facing flags. 1609 * 1610 * This will overwrite existing env->misa_ext values with the 1611 * defaults set via riscv_cpu_add_misa_properties(). 1612 */ 1613 static void riscv_cpu_add_user_properties(Object *obj) 1614 { 1615 Property *prop; 1616 DeviceState *dev = DEVICE(obj); 1617 1618 riscv_cpu_add_misa_properties(obj); 1619 1620 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1621 qdev_property_add_static(dev, prop); 1622 } 1623 1624 #ifndef CONFIG_USER_ONLY 1625 riscv_add_satp_mode_properties(obj); 1626 #endif 1627 } 1628 1629 static Property riscv_cpu_properties[] = { 1630 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1631 1632 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1633 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1634 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1635 1636 #ifndef CONFIG_USER_ONLY 1637 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1638 #endif 1639 1640 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1641 1642 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1643 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1644 1645 /* 1646 * write_misa() is marked as experimental for now so mark 1647 * it with -x and default to 'false'. 1648 */ 1649 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1650 DEFINE_PROP_END_OF_LIST(), 1651 }; 1652 1653 static gchar *riscv_gdb_arch_name(CPUState *cs) 1654 { 1655 RISCVCPU *cpu = RISCV_CPU(cs); 1656 CPURISCVState *env = &cpu->env; 1657 1658 switch (riscv_cpu_mxl(env)) { 1659 case MXL_RV32: 1660 return g_strdup("riscv:rv32"); 1661 case MXL_RV64: 1662 case MXL_RV128: 1663 return g_strdup("riscv:rv64"); 1664 default: 1665 g_assert_not_reached(); 1666 } 1667 } 1668 1669 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1670 { 1671 RISCVCPU *cpu = RISCV_CPU(cs); 1672 1673 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1674 return cpu->dyn_csr_xml; 1675 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1676 return cpu->dyn_vreg_xml; 1677 } 1678 1679 return NULL; 1680 } 1681 1682 #ifndef CONFIG_USER_ONLY 1683 static int64_t riscv_get_arch_id(CPUState *cs) 1684 { 1685 RISCVCPU *cpu = RISCV_CPU(cs); 1686 1687 return cpu->env.mhartid; 1688 } 1689 1690 #include "hw/core/sysemu-cpu-ops.h" 1691 1692 static const struct SysemuCPUOps riscv_sysemu_ops = { 1693 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1694 .write_elf64_note = riscv_cpu_write_elf64_note, 1695 .write_elf32_note = riscv_cpu_write_elf32_note, 1696 .legacy_vmsd = &vmstate_riscv_cpu, 1697 }; 1698 #endif 1699 1700 #include "hw/core/tcg-cpu-ops.h" 1701 1702 static const struct TCGCPUOps riscv_tcg_ops = { 1703 .initialize = riscv_translate_init, 1704 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1705 .restore_state_to_opc = riscv_restore_state_to_opc, 1706 1707 #ifndef CONFIG_USER_ONLY 1708 .tlb_fill = riscv_cpu_tlb_fill, 1709 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1710 .do_interrupt = riscv_cpu_do_interrupt, 1711 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1712 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1713 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1714 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1715 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1716 #endif /* !CONFIG_USER_ONLY */ 1717 }; 1718 1719 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1720 { 1721 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1722 CPUClass *cc = CPU_CLASS(c); 1723 DeviceClass *dc = DEVICE_CLASS(c); 1724 ResettableClass *rc = RESETTABLE_CLASS(c); 1725 1726 device_class_set_parent_realize(dc, riscv_cpu_realize, 1727 &mcc->parent_realize); 1728 1729 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1730 &mcc->parent_phases); 1731 1732 cc->class_by_name = riscv_cpu_class_by_name; 1733 cc->has_work = riscv_cpu_has_work; 1734 cc->dump_state = riscv_cpu_dump_state; 1735 cc->set_pc = riscv_cpu_set_pc; 1736 cc->get_pc = riscv_cpu_get_pc; 1737 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1738 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1739 cc->gdb_num_core_regs = 33; 1740 cc->gdb_stop_before_watchpoint = true; 1741 cc->disas_set_info = riscv_cpu_disas_set_info; 1742 #ifndef CONFIG_USER_ONLY 1743 cc->sysemu_ops = &riscv_sysemu_ops; 1744 cc->get_arch_id = riscv_get_arch_id; 1745 #endif 1746 cc->gdb_arch_name = riscv_gdb_arch_name; 1747 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1748 cc->tcg_ops = &riscv_tcg_ops; 1749 1750 device_class_set_props(dc, riscv_cpu_properties); 1751 } 1752 1753 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, 1754 int max_str_len) 1755 { 1756 char *old = *isa_str; 1757 char *new = *isa_str; 1758 int i; 1759 1760 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1761 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1762 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1763 g_free(old); 1764 old = new; 1765 } 1766 } 1767 1768 *isa_str = new; 1769 } 1770 1771 char *riscv_isa_string(RISCVCPU *cpu) 1772 { 1773 int i; 1774 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1775 char *isa_str = g_new(char, maxlen); 1776 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1777 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1778 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1779 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1780 } 1781 } 1782 *p = '\0'; 1783 if (!cpu->cfg.short_isa_string) { 1784 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1785 } 1786 return isa_str; 1787 } 1788 1789 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1790 { 1791 ObjectClass *class_a = (ObjectClass *)a; 1792 ObjectClass *class_b = (ObjectClass *)b; 1793 const char *name_a, *name_b; 1794 1795 name_a = object_class_get_name(class_a); 1796 name_b = object_class_get_name(class_b); 1797 return strcmp(name_a, name_b); 1798 } 1799 1800 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1801 { 1802 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1803 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1804 1805 qemu_printf("%.*s\n", len, typename); 1806 } 1807 1808 void riscv_cpu_list(void) 1809 { 1810 GSList *list; 1811 1812 list = object_class_get_list(TYPE_RISCV_CPU, false); 1813 list = g_slist_sort(list, riscv_cpu_list_compare); 1814 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1815 g_slist_free(list); 1816 } 1817 1818 #define DEFINE_CPU(type_name, initfn) \ 1819 { \ 1820 .name = type_name, \ 1821 .parent = TYPE_RISCV_CPU, \ 1822 .instance_init = initfn \ 1823 } 1824 1825 #define DEFINE_DYNAMIC_CPU(type_name, initfn) \ 1826 { \ 1827 .name = type_name, \ 1828 .parent = TYPE_RISCV_DYNAMIC_CPU, \ 1829 .instance_init = initfn \ 1830 } 1831 1832 static const TypeInfo riscv_cpu_type_infos[] = { 1833 { 1834 .name = TYPE_RISCV_CPU, 1835 .parent = TYPE_CPU, 1836 .instance_size = sizeof(RISCVCPU), 1837 .instance_align = __alignof__(RISCVCPU), 1838 .instance_init = riscv_cpu_init, 1839 .abstract = true, 1840 .class_size = sizeof(RISCVCPUClass), 1841 .class_init = riscv_cpu_class_init, 1842 }, 1843 { 1844 .name = TYPE_RISCV_DYNAMIC_CPU, 1845 .parent = TYPE_RISCV_CPU, 1846 .abstract = true, 1847 }, 1848 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1849 #if defined(CONFIG_KVM) 1850 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1851 #endif 1852 #if defined(TARGET_RISCV32) 1853 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1854 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1855 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1856 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1857 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1858 #elif defined(TARGET_RISCV64) 1859 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1860 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1861 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1862 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1863 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1864 DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), 1865 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1866 #endif 1867 }; 1868 1869 DEFINE_TYPES(riscv_cpu_type_infos) 1870