1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/log.h" 23 #include "cpu.h" 24 #include "exec/exec-all.h" 25 #include "qapi/error.h" 26 #include "hw/qdev-properties.h" 27 #include "migration/vmstate.h" 28 29 /* RISC-V CPU definitions */ 30 31 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 32 33 const char * const riscv_int_regnames[] = { 34 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", 35 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 36 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", 37 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" 38 }; 39 40 const char * const riscv_fpr_regnames[] = { 41 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", 42 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", 43 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", 44 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" 45 }; 46 47 const char * const riscv_excp_names[] = { 48 "misaligned_fetch", 49 "fault_fetch", 50 "illegal_instruction", 51 "breakpoint", 52 "misaligned_load", 53 "fault_load", 54 "misaligned_store", 55 "fault_store", 56 "user_ecall", 57 "supervisor_ecall", 58 "hypervisor_ecall", 59 "machine_ecall", 60 "exec_page_fault", 61 "load_page_fault", 62 "reserved", 63 "store_page_fault" 64 }; 65 66 const char * const riscv_intr_names[] = { 67 "u_software", 68 "s_software", 69 "h_software", 70 "m_software", 71 "u_timer", 72 "s_timer", 73 "h_timer", 74 "m_timer", 75 "u_external", 76 "s_external", 77 "h_external", 78 "m_external", 79 "reserved", 80 "reserved", 81 "reserved", 82 "reserved" 83 }; 84 85 static void set_misa(CPURISCVState *env, target_ulong misa) 86 { 87 env->misa_mask = env->misa = misa; 88 } 89 90 static void set_versions(CPURISCVState *env, int user_ver, int priv_ver) 91 { 92 env->user_ver = user_ver; 93 env->priv_ver = priv_ver; 94 } 95 96 static void set_feature(CPURISCVState *env, int feature) 97 { 98 env->features |= (1ULL << feature); 99 } 100 101 static void set_resetvec(CPURISCVState *env, int resetvec) 102 { 103 #ifndef CONFIG_USER_ONLY 104 env->resetvec = resetvec; 105 #endif 106 } 107 108 static void riscv_any_cpu_init(Object *obj) 109 { 110 CPURISCVState *env = &RISCV_CPU(obj)->env; 111 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); 112 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); 113 set_resetvec(env, DEFAULT_RSTVEC); 114 } 115 116 #if defined(TARGET_RISCV32) 117 118 static void riscv_base32_cpu_init(Object *obj) 119 { 120 CPURISCVState *env = &RISCV_CPU(obj)->env; 121 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 122 } 123 124 static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) 125 { 126 CPURISCVState *env = &RISCV_CPU(obj)->env; 127 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 128 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1); 129 set_resetvec(env, DEFAULT_RSTVEC); 130 set_feature(env, RISCV_FEATURE_MMU); 131 set_feature(env, RISCV_FEATURE_PMP); 132 } 133 134 static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) 135 { 136 CPURISCVState *env = &RISCV_CPU(obj)->env; 137 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 138 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); 139 set_resetvec(env, DEFAULT_RSTVEC); 140 set_feature(env, RISCV_FEATURE_MMU); 141 set_feature(env, RISCV_FEATURE_PMP); 142 } 143 144 static void rv32imacu_nommu_cpu_init(Object *obj) 145 { 146 CPURISCVState *env = &RISCV_CPU(obj)->env; 147 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); 148 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); 149 set_resetvec(env, DEFAULT_RSTVEC); 150 set_feature(env, RISCV_FEATURE_PMP); 151 } 152 153 #elif defined(TARGET_RISCV64) 154 155 static void riscv_base64_cpu_init(Object *obj) 156 { 157 CPURISCVState *env = &RISCV_CPU(obj)->env; 158 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 159 } 160 161 static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) 162 { 163 CPURISCVState *env = &RISCV_CPU(obj)->env; 164 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 165 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1); 166 set_resetvec(env, DEFAULT_RSTVEC); 167 set_feature(env, RISCV_FEATURE_MMU); 168 set_feature(env, RISCV_FEATURE_PMP); 169 } 170 171 static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) 172 { 173 CPURISCVState *env = &RISCV_CPU(obj)->env; 174 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 175 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); 176 set_resetvec(env, DEFAULT_RSTVEC); 177 set_feature(env, RISCV_FEATURE_MMU); 178 set_feature(env, RISCV_FEATURE_PMP); 179 } 180 181 static void rv64imacu_nommu_cpu_init(Object *obj) 182 { 183 CPURISCVState *env = &RISCV_CPU(obj)->env; 184 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); 185 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); 186 set_resetvec(env, DEFAULT_RSTVEC); 187 set_feature(env, RISCV_FEATURE_PMP); 188 } 189 190 #endif 191 192 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 193 { 194 ObjectClass *oc; 195 char *typename; 196 char **cpuname; 197 198 cpuname = g_strsplit(cpu_model, ",", 1); 199 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 200 oc = object_class_by_name(typename); 201 g_strfreev(cpuname); 202 g_free(typename); 203 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 204 object_class_is_abstract(oc)) { 205 return NULL; 206 } 207 return oc; 208 } 209 210 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 211 { 212 RISCVCPU *cpu = RISCV_CPU(cs); 213 CPURISCVState *env = &cpu->env; 214 int i; 215 216 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 217 #ifndef CONFIG_USER_ONLY 218 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); 219 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); 220 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", 221 (target_ulong)atomic_read(&env->mip)); 222 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); 223 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); 224 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); 225 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); 226 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); 227 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); 228 #endif 229 230 for (i = 0; i < 32; i++) { 231 qemu_fprintf(f, " %s " TARGET_FMT_lx, 232 riscv_int_regnames[i], env->gpr[i]); 233 if ((i & 3) == 3) { 234 qemu_fprintf(f, "\n"); 235 } 236 } 237 if (flags & CPU_DUMP_FPU) { 238 for (i = 0; i < 32; i++) { 239 qemu_fprintf(f, " %s %016" PRIx64, 240 riscv_fpr_regnames[i], env->fpr[i]); 241 if ((i & 3) == 3) { 242 qemu_fprintf(f, "\n"); 243 } 244 } 245 } 246 } 247 248 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 249 { 250 RISCVCPU *cpu = RISCV_CPU(cs); 251 CPURISCVState *env = &cpu->env; 252 env->pc = value; 253 } 254 255 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 256 { 257 RISCVCPU *cpu = RISCV_CPU(cs); 258 CPURISCVState *env = &cpu->env; 259 env->pc = tb->pc; 260 } 261 262 static bool riscv_cpu_has_work(CPUState *cs) 263 { 264 #ifndef CONFIG_USER_ONLY 265 RISCVCPU *cpu = RISCV_CPU(cs); 266 CPURISCVState *env = &cpu->env; 267 /* 268 * Definition of the WFI instruction requires it to ignore the privilege 269 * mode and delegation registers, but respect individual enables 270 */ 271 return (atomic_read(&env->mip) & env->mie) != 0; 272 #else 273 return true; 274 #endif 275 } 276 277 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 278 target_ulong *data) 279 { 280 env->pc = data[0]; 281 } 282 283 static void riscv_cpu_reset(CPUState *cs) 284 { 285 RISCVCPU *cpu = RISCV_CPU(cs); 286 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 287 CPURISCVState *env = &cpu->env; 288 289 mcc->parent_reset(cs); 290 #ifndef CONFIG_USER_ONLY 291 env->priv = PRV_M; 292 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 293 env->mcause = 0; 294 env->pc = env->resetvec; 295 #endif 296 cs->exception_index = EXCP_NONE; 297 set_default_nan_mode(1, &env->fp_status); 298 } 299 300 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 301 { 302 #if defined(TARGET_RISCV32) 303 info->print_insn = print_insn_riscv32; 304 #elif defined(TARGET_RISCV64) 305 info->print_insn = print_insn_riscv64; 306 #endif 307 } 308 309 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 310 { 311 CPUState *cs = CPU(dev); 312 RISCVCPU *cpu = RISCV_CPU(dev); 313 CPURISCVState *env = &cpu->env; 314 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 315 int priv_version = PRIV_VERSION_1_10_0; 316 int user_version = USER_VERSION_2_02_0; 317 Error *local_err = NULL; 318 319 cpu_exec_realizefn(cs, &local_err); 320 if (local_err != NULL) { 321 error_propagate(errp, local_err); 322 return; 323 } 324 325 if (cpu->cfg.priv_spec) { 326 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 327 priv_version = PRIV_VERSION_1_10_0; 328 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) { 329 priv_version = PRIV_VERSION_1_09_1; 330 } else { 331 error_setg(errp, 332 "Unsupported privilege spec version '%s'", 333 cpu->cfg.priv_spec); 334 return; 335 } 336 } 337 338 if (cpu->cfg.user_spec) { 339 if (!g_strcmp0(cpu->cfg.user_spec, "v2.02.0")) { 340 user_version = USER_VERSION_2_02_0; 341 } else { 342 error_setg(errp, 343 "Unsupported user spec version '%s'", 344 cpu->cfg.user_spec); 345 return; 346 } 347 } 348 349 set_versions(env, user_version, priv_version); 350 set_resetvec(env, DEFAULT_RSTVEC); 351 352 if (cpu->cfg.mmu) { 353 set_feature(env, RISCV_FEATURE_MMU); 354 } 355 356 if (cpu->cfg.pmp) { 357 set_feature(env, RISCV_FEATURE_PMP); 358 } 359 360 riscv_cpu_register_gdb_regs_for_features(cs); 361 362 qemu_init_vcpu(cs); 363 cpu_reset(cs); 364 365 mcc->parent_realize(dev, errp); 366 } 367 368 static void riscv_cpu_init(Object *obj) 369 { 370 CPUState *cs = CPU(obj); 371 RISCVCPU *cpu = RISCV_CPU(obj); 372 373 cs->env_ptr = &cpu->env; 374 } 375 376 static const VMStateDescription vmstate_riscv_cpu = { 377 .name = "cpu", 378 .unmigratable = 1, 379 }; 380 381 static Property riscv_cpu_properties[] = { 382 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 383 DEFINE_PROP_STRING("user_spec", RISCVCPU, cfg.user_spec), 384 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 385 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 386 DEFINE_PROP_END_OF_LIST(), 387 }; 388 389 static void riscv_cpu_class_init(ObjectClass *c, void *data) 390 { 391 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 392 CPUClass *cc = CPU_CLASS(c); 393 DeviceClass *dc = DEVICE_CLASS(c); 394 395 device_class_set_parent_realize(dc, riscv_cpu_realize, 396 &mcc->parent_realize); 397 398 mcc->parent_reset = cc->reset; 399 cc->reset = riscv_cpu_reset; 400 401 cc->class_by_name = riscv_cpu_class_by_name; 402 cc->has_work = riscv_cpu_has_work; 403 cc->do_interrupt = riscv_cpu_do_interrupt; 404 cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt; 405 cc->dump_state = riscv_cpu_dump_state; 406 cc->set_pc = riscv_cpu_set_pc; 407 cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb; 408 cc->gdb_read_register = riscv_cpu_gdb_read_register; 409 cc->gdb_write_register = riscv_cpu_gdb_write_register; 410 cc->gdb_num_core_regs = 33; 411 #if defined(TARGET_RISCV32) 412 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 413 #elif defined(TARGET_RISCV64) 414 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 415 #endif 416 cc->gdb_stop_before_watchpoint = true; 417 cc->disas_set_info = riscv_cpu_disas_set_info; 418 #ifndef CONFIG_USER_ONLY 419 cc->do_unaligned_access = riscv_cpu_do_unaligned_access; 420 cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; 421 #endif 422 #ifdef CONFIG_TCG 423 cc->tcg_initialize = riscv_translate_init; 424 cc->tlb_fill = riscv_cpu_tlb_fill; 425 #endif 426 /* For now, mark unmigratable: */ 427 cc->vmsd = &vmstate_riscv_cpu; 428 dc->props = riscv_cpu_properties; 429 } 430 431 char *riscv_isa_string(RISCVCPU *cpu) 432 { 433 int i; 434 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 435 char *isa_str = g_new(char, maxlen); 436 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 437 for (i = 0; i < sizeof(riscv_exts); i++) { 438 if (cpu->env.misa & RV(riscv_exts[i])) { 439 *p++ = qemu_tolower(riscv_exts[i]); 440 } 441 } 442 *p = '\0'; 443 return isa_str; 444 } 445 446 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 447 { 448 ObjectClass *class_a = (ObjectClass *)a; 449 ObjectClass *class_b = (ObjectClass *)b; 450 const char *name_a, *name_b; 451 452 name_a = object_class_get_name(class_a); 453 name_b = object_class_get_name(class_b); 454 return strcmp(name_a, name_b); 455 } 456 457 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 458 { 459 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 460 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 461 462 qemu_printf("%.*s\n", len, typename); 463 } 464 465 void riscv_cpu_list(void) 466 { 467 GSList *list; 468 469 list = object_class_get_list(TYPE_RISCV_CPU, false); 470 list = g_slist_sort(list, riscv_cpu_list_compare); 471 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 472 g_slist_free(list); 473 } 474 475 #define DEFINE_CPU(type_name, initfn) \ 476 { \ 477 .name = type_name, \ 478 .parent = TYPE_RISCV_CPU, \ 479 .instance_init = initfn \ 480 } 481 482 static const TypeInfo riscv_cpu_type_infos[] = { 483 { 484 .name = TYPE_RISCV_CPU, 485 .parent = TYPE_CPU, 486 .instance_size = sizeof(RISCVCPU), 487 .instance_init = riscv_cpu_init, 488 .abstract = true, 489 .class_size = sizeof(RISCVCPUClass), 490 .class_init = riscv_cpu_class_init, 491 }, 492 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 493 #if defined(TARGET_RISCV32) 494 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), 495 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init), 496 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init), 497 DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), 498 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), 499 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init) 500 #elif defined(TARGET_RISCV64) 501 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), 502 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init), 503 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init), 504 DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), 505 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), 506 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init) 507 #endif 508 }; 509 510 DEFINE_TYPES(riscv_cpu_type_infos) 511