1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "exec/exec-all.h" 26 #include "qapi/error.h" 27 #include "qemu/error-report.h" 28 #include "hw/qdev-properties.h" 29 #include "migration/vmstate.h" 30 #include "fpu/softfloat-helpers.h" 31 32 /* RISC-V CPU definitions */ 33 34 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 35 36 const char * const riscv_int_regnames[] = { 37 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 38 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 39 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 40 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 41 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 42 }; 43 44 const char * const riscv_fpr_regnames[] = { 45 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 46 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 47 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 48 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 49 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 50 "f30/ft10", "f31/ft11" 51 }; 52 53 const char * const riscv_excp_names[] = { 54 "misaligned_fetch", 55 "fault_fetch", 56 "illegal_instruction", 57 "breakpoint", 58 "misaligned_load", 59 "fault_load", 60 "misaligned_store", 61 "fault_store", 62 "user_ecall", 63 "supervisor_ecall", 64 "hypervisor_ecall", 65 "machine_ecall", 66 "exec_page_fault", 67 "load_page_fault", 68 "reserved", 69 "store_page_fault" 70 }; 71 72 const char * const riscv_intr_names[] = { 73 "u_software", 74 "s_software", 75 "h_software", 76 "m_software", 77 "u_timer", 78 "s_timer", 79 "h_timer", 80 "m_timer", 81 "u_external", 82 "s_external", 83 "h_external", 84 "m_external", 85 "reserved", 86 "reserved", 87 "reserved", 88 "reserved" 89 }; 90 91 static void set_misa(CPURISCVState *env, target_ulong misa) 92 { 93 env->misa_mask = env->misa = misa; 94 } 95 96 static void set_priv_version(CPURISCVState *env, int priv_ver) 97 { 98 env->priv_ver = priv_ver; 99 } 100 101 static void set_feature(CPURISCVState *env, int feature) 102 { 103 env->features |= (1ULL << feature); 104 } 105 106 static void set_resetvec(CPURISCVState *env, int resetvec) 107 { 108 #ifndef CONFIG_USER_ONLY 109 env->resetvec = resetvec; 110 #endif 111 } 112 113 static void riscv_any_cpu_init(Object *obj) 114 { 115 CPURISCVState *env = &RISCV_CPU(obj)->env; 116 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); 117 set_priv_version(env, PRIV_VERSION_1_11_0); 118 set_resetvec(env, DEFAULT_RSTVEC); 119 } 120 121 #if defined(TARGET_RISCV32) 122 123 static void riscv_base32_cpu_init(Object *obj) 124 { 125 CPURISCVState *env = &RISCV_CPU(obj)->env; 126 /* We set this in the realise function */ 127 set_misa(env, 0); 128 } 129 130 static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) 131 { 132 CPURISCVState *env = &RISCV_CPU(obj)->env; 133 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 134 set_priv_version(env, PRIV_VERSION_1_09_1); 135 set_resetvec(env, DEFAULT_RSTVEC); 136 set_feature(env, RISCV_FEATURE_MMU); 137 set_feature(env, RISCV_FEATURE_PMP); 138 } 139 140 static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) 141 { 142 CPURISCVState *env = &RISCV_CPU(obj)->env; 143 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 144 set_priv_version(env, PRIV_VERSION_1_10_0); 145 set_resetvec(env, DEFAULT_RSTVEC); 146 set_feature(env, RISCV_FEATURE_MMU); 147 set_feature(env, RISCV_FEATURE_PMP); 148 } 149 150 static void rv32imacu_nommu_cpu_init(Object *obj) 151 { 152 CPURISCVState *env = &RISCV_CPU(obj)->env; 153 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); 154 set_priv_version(env, PRIV_VERSION_1_10_0); 155 set_resetvec(env, DEFAULT_RSTVEC); 156 set_feature(env, RISCV_FEATURE_PMP); 157 } 158 159 #elif defined(TARGET_RISCV64) 160 161 static void riscv_base64_cpu_init(Object *obj) 162 { 163 CPURISCVState *env = &RISCV_CPU(obj)->env; 164 /* We set this in the realise function */ 165 set_misa(env, 0); 166 } 167 168 static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) 169 { 170 CPURISCVState *env = &RISCV_CPU(obj)->env; 171 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 172 set_priv_version(env, PRIV_VERSION_1_09_1); 173 set_resetvec(env, DEFAULT_RSTVEC); 174 set_feature(env, RISCV_FEATURE_MMU); 175 set_feature(env, RISCV_FEATURE_PMP); 176 } 177 178 static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) 179 { 180 CPURISCVState *env = &RISCV_CPU(obj)->env; 181 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 182 set_priv_version(env, PRIV_VERSION_1_10_0); 183 set_resetvec(env, DEFAULT_RSTVEC); 184 set_feature(env, RISCV_FEATURE_MMU); 185 set_feature(env, RISCV_FEATURE_PMP); 186 } 187 188 static void rv64imacu_nommu_cpu_init(Object *obj) 189 { 190 CPURISCVState *env = &RISCV_CPU(obj)->env; 191 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); 192 set_priv_version(env, PRIV_VERSION_1_10_0); 193 set_resetvec(env, DEFAULT_RSTVEC); 194 set_feature(env, RISCV_FEATURE_PMP); 195 } 196 197 #endif 198 199 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 200 { 201 ObjectClass *oc; 202 char *typename; 203 char **cpuname; 204 205 cpuname = g_strsplit(cpu_model, ",", 1); 206 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 207 oc = object_class_by_name(typename); 208 g_strfreev(cpuname); 209 g_free(typename); 210 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 211 object_class_is_abstract(oc)) { 212 return NULL; 213 } 214 return oc; 215 } 216 217 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 218 { 219 RISCVCPU *cpu = RISCV_CPU(cs); 220 CPURISCVState *env = &cpu->env; 221 int i; 222 223 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 224 #ifndef CONFIG_USER_ONLY 225 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); 226 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); 227 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", 228 (target_ulong)atomic_read(&env->mip)); 229 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); 230 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); 231 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); 232 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); 233 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); 234 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); 235 #endif 236 237 for (i = 0; i < 32; i++) { 238 qemu_fprintf(f, " %s " TARGET_FMT_lx, 239 riscv_int_regnames[i], env->gpr[i]); 240 if ((i & 3) == 3) { 241 qemu_fprintf(f, "\n"); 242 } 243 } 244 if (flags & CPU_DUMP_FPU) { 245 for (i = 0; i < 32; i++) { 246 qemu_fprintf(f, " %s %016" PRIx64, 247 riscv_fpr_regnames[i], env->fpr[i]); 248 if ((i & 3) == 3) { 249 qemu_fprintf(f, "\n"); 250 } 251 } 252 } 253 } 254 255 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 256 { 257 RISCVCPU *cpu = RISCV_CPU(cs); 258 CPURISCVState *env = &cpu->env; 259 env->pc = value; 260 } 261 262 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 263 { 264 RISCVCPU *cpu = RISCV_CPU(cs); 265 CPURISCVState *env = &cpu->env; 266 env->pc = tb->pc; 267 } 268 269 static bool riscv_cpu_has_work(CPUState *cs) 270 { 271 #ifndef CONFIG_USER_ONLY 272 RISCVCPU *cpu = RISCV_CPU(cs); 273 CPURISCVState *env = &cpu->env; 274 /* 275 * Definition of the WFI instruction requires it to ignore the privilege 276 * mode and delegation registers, but respect individual enables 277 */ 278 return (atomic_read(&env->mip) & env->mie) != 0; 279 #else 280 return true; 281 #endif 282 } 283 284 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 285 target_ulong *data) 286 { 287 env->pc = data[0]; 288 } 289 290 static void riscv_cpu_reset(CPUState *cs) 291 { 292 RISCVCPU *cpu = RISCV_CPU(cs); 293 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 294 CPURISCVState *env = &cpu->env; 295 296 mcc->parent_reset(cs); 297 #ifndef CONFIG_USER_ONLY 298 env->priv = PRV_M; 299 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 300 env->mcause = 0; 301 env->pc = env->resetvec; 302 #endif 303 cs->exception_index = EXCP_NONE; 304 env->load_res = -1; 305 set_default_nan_mode(1, &env->fp_status); 306 } 307 308 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 309 { 310 #if defined(TARGET_RISCV32) 311 info->print_insn = print_insn_riscv32; 312 #elif defined(TARGET_RISCV64) 313 info->print_insn = print_insn_riscv64; 314 #endif 315 } 316 317 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 318 { 319 CPUState *cs = CPU(dev); 320 RISCVCPU *cpu = RISCV_CPU(dev); 321 CPURISCVState *env = &cpu->env; 322 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 323 int priv_version = PRIV_VERSION_1_11_0; 324 target_ulong target_misa = 0; 325 Error *local_err = NULL; 326 327 cpu_exec_realizefn(cs, &local_err); 328 if (local_err != NULL) { 329 error_propagate(errp, local_err); 330 return; 331 } 332 333 if (cpu->cfg.priv_spec) { 334 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 335 priv_version = PRIV_VERSION_1_11_0; 336 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 337 priv_version = PRIV_VERSION_1_10_0; 338 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) { 339 priv_version = PRIV_VERSION_1_09_1; 340 } else { 341 error_setg(errp, 342 "Unsupported privilege spec version '%s'", 343 cpu->cfg.priv_spec); 344 return; 345 } 346 } 347 348 set_priv_version(env, priv_version); 349 set_resetvec(env, DEFAULT_RSTVEC); 350 351 if (cpu->cfg.mmu) { 352 set_feature(env, RISCV_FEATURE_MMU); 353 } 354 355 if (cpu->cfg.pmp) { 356 set_feature(env, RISCV_FEATURE_PMP); 357 } 358 359 /* If misa isn't set (rv32 and rv64 machines) set it here */ 360 if (!env->misa) { 361 /* Do some ISA extension error checking */ 362 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 363 error_setg(errp, 364 "I and E extensions are incompatible"); 365 return; 366 } 367 368 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 369 error_setg(errp, 370 "Either I or E extension must be set"); 371 return; 372 } 373 374 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 375 cpu->cfg.ext_a & cpu->cfg.ext_f & 376 cpu->cfg.ext_d)) { 377 warn_report("Setting G will also set IMAFD"); 378 cpu->cfg.ext_i = true; 379 cpu->cfg.ext_m = true; 380 cpu->cfg.ext_a = true; 381 cpu->cfg.ext_f = true; 382 cpu->cfg.ext_d = true; 383 } 384 385 /* Set the ISA extensions, checks should have happened above */ 386 if (cpu->cfg.ext_i) { 387 target_misa |= RVI; 388 } 389 if (cpu->cfg.ext_e) { 390 target_misa |= RVE; 391 } 392 if (cpu->cfg.ext_m) { 393 target_misa |= RVM; 394 } 395 if (cpu->cfg.ext_a) { 396 target_misa |= RVA; 397 } 398 if (cpu->cfg.ext_f) { 399 target_misa |= RVF; 400 } 401 if (cpu->cfg.ext_d) { 402 target_misa |= RVD; 403 } 404 if (cpu->cfg.ext_c) { 405 target_misa |= RVC; 406 } 407 if (cpu->cfg.ext_s) { 408 target_misa |= RVS; 409 } 410 if (cpu->cfg.ext_u) { 411 target_misa |= RVU; 412 } 413 414 set_misa(env, RVXLEN | target_misa); 415 } 416 417 riscv_cpu_register_gdb_regs_for_features(cs); 418 419 qemu_init_vcpu(cs); 420 cpu_reset(cs); 421 422 mcc->parent_realize(dev, errp); 423 } 424 425 static void riscv_cpu_init(Object *obj) 426 { 427 RISCVCPU *cpu = RISCV_CPU(obj); 428 429 cpu_set_cpustate_pointers(cpu); 430 } 431 432 static const VMStateDescription vmstate_riscv_cpu = { 433 .name = "cpu", 434 .unmigratable = 1, 435 }; 436 437 static Property riscv_cpu_properties[] = { 438 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 439 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 440 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 441 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 442 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 443 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 444 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 445 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 446 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 447 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 448 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 449 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 450 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 451 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 452 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 453 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 454 DEFINE_PROP_END_OF_LIST(), 455 }; 456 457 static void riscv_cpu_class_init(ObjectClass *c, void *data) 458 { 459 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 460 CPUClass *cc = CPU_CLASS(c); 461 DeviceClass *dc = DEVICE_CLASS(c); 462 463 device_class_set_parent_realize(dc, riscv_cpu_realize, 464 &mcc->parent_realize); 465 466 mcc->parent_reset = cc->reset; 467 cc->reset = riscv_cpu_reset; 468 469 cc->class_by_name = riscv_cpu_class_by_name; 470 cc->has_work = riscv_cpu_has_work; 471 cc->do_interrupt = riscv_cpu_do_interrupt; 472 cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt; 473 cc->dump_state = riscv_cpu_dump_state; 474 cc->set_pc = riscv_cpu_set_pc; 475 cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb; 476 cc->gdb_read_register = riscv_cpu_gdb_read_register; 477 cc->gdb_write_register = riscv_cpu_gdb_write_register; 478 cc->gdb_num_core_regs = 33; 479 #if defined(TARGET_RISCV32) 480 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 481 #elif defined(TARGET_RISCV64) 482 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 483 #endif 484 cc->gdb_stop_before_watchpoint = true; 485 cc->disas_set_info = riscv_cpu_disas_set_info; 486 #ifndef CONFIG_USER_ONLY 487 cc->do_unassigned_access = riscv_cpu_unassigned_access; 488 cc->do_unaligned_access = riscv_cpu_do_unaligned_access; 489 cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; 490 #endif 491 #ifdef CONFIG_TCG 492 cc->tcg_initialize = riscv_translate_init; 493 cc->tlb_fill = riscv_cpu_tlb_fill; 494 #endif 495 /* For now, mark unmigratable: */ 496 cc->vmsd = &vmstate_riscv_cpu; 497 dc->props = riscv_cpu_properties; 498 } 499 500 char *riscv_isa_string(RISCVCPU *cpu) 501 { 502 int i; 503 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 504 char *isa_str = g_new(char, maxlen); 505 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 506 for (i = 0; i < sizeof(riscv_exts); i++) { 507 if (cpu->env.misa & RV(riscv_exts[i])) { 508 *p++ = qemu_tolower(riscv_exts[i]); 509 } 510 } 511 *p = '\0'; 512 return isa_str; 513 } 514 515 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 516 { 517 ObjectClass *class_a = (ObjectClass *)a; 518 ObjectClass *class_b = (ObjectClass *)b; 519 const char *name_a, *name_b; 520 521 name_a = object_class_get_name(class_a); 522 name_b = object_class_get_name(class_b); 523 return strcmp(name_a, name_b); 524 } 525 526 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 527 { 528 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 529 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 530 531 qemu_printf("%.*s\n", len, typename); 532 } 533 534 void riscv_cpu_list(void) 535 { 536 GSList *list; 537 538 list = object_class_get_list(TYPE_RISCV_CPU, false); 539 list = g_slist_sort(list, riscv_cpu_list_compare); 540 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 541 g_slist_free(list); 542 } 543 544 #define DEFINE_CPU(type_name, initfn) \ 545 { \ 546 .name = type_name, \ 547 .parent = TYPE_RISCV_CPU, \ 548 .instance_init = initfn \ 549 } 550 551 static const TypeInfo riscv_cpu_type_infos[] = { 552 { 553 .name = TYPE_RISCV_CPU, 554 .parent = TYPE_CPU, 555 .instance_size = sizeof(RISCVCPU), 556 .instance_init = riscv_cpu_init, 557 .abstract = true, 558 .class_size = sizeof(RISCVCPUClass), 559 .class_init = riscv_cpu_class_init, 560 }, 561 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 562 #if defined(TARGET_RISCV32) 563 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), 564 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), 565 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init), 566 /* Depreacted */ 567 DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), 568 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init), 569 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init) 570 #elif defined(TARGET_RISCV64) 571 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), 572 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), 573 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init), 574 /* Deprecated */ 575 DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), 576 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init), 577 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init) 578 #endif 579 }; 580 581 DEFINE_TYPES(riscv_cpu_type_infos) 582