1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "exec/exec-all.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "fpu/softfloat-helpers.h" 32 33 /* RISC-V CPU definitions */ 34 35 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 36 37 const char * const riscv_int_regnames[] = { 38 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 39 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 40 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 41 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 42 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 43 }; 44 45 const char * const riscv_fpr_regnames[] = { 46 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 47 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 48 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 49 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 50 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 51 "f30/ft10", "f31/ft11" 52 }; 53 54 const char * const riscv_excp_names[] = { 55 "misaligned_fetch", 56 "fault_fetch", 57 "illegal_instruction", 58 "breakpoint", 59 "misaligned_load", 60 "fault_load", 61 "misaligned_store", 62 "fault_store", 63 "user_ecall", 64 "supervisor_ecall", 65 "hypervisor_ecall", 66 "machine_ecall", 67 "exec_page_fault", 68 "load_page_fault", 69 "reserved", 70 "store_page_fault", 71 "reserved", 72 "reserved", 73 "reserved", 74 "reserved", 75 "guest_exec_page_fault", 76 "guest_load_page_fault", 77 "reserved", 78 "guest_store_page_fault", 79 }; 80 81 const char * const riscv_intr_names[] = { 82 "u_software", 83 "s_software", 84 "vs_software", 85 "m_software", 86 "u_timer", 87 "s_timer", 88 "vs_timer", 89 "m_timer", 90 "u_external", 91 "s_external", 92 "vs_external", 93 "m_external", 94 "reserved", 95 "reserved", 96 "reserved", 97 "reserved" 98 }; 99 100 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 101 { 102 if (async) { 103 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 104 riscv_intr_names[cause] : "(unknown)"; 105 } else { 106 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 107 riscv_excp_names[cause] : "(unknown)"; 108 } 109 } 110 111 bool riscv_cpu_is_32bit(CPURISCVState *env) 112 { 113 if (env->misa & RV64) { 114 return false; 115 } 116 117 return true; 118 } 119 120 static void set_misa(CPURISCVState *env, target_ulong misa) 121 { 122 env->misa_mask = env->misa = misa; 123 } 124 125 static void set_priv_version(CPURISCVState *env, int priv_ver) 126 { 127 env->priv_ver = priv_ver; 128 } 129 130 static void set_vext_version(CPURISCVState *env, int vext_ver) 131 { 132 env->vext_ver = vext_ver; 133 } 134 135 static void set_feature(CPURISCVState *env, int feature) 136 { 137 env->features |= (1ULL << feature); 138 } 139 140 static void set_resetvec(CPURISCVState *env, target_ulong resetvec) 141 { 142 #ifndef CONFIG_USER_ONLY 143 env->resetvec = resetvec; 144 #endif 145 } 146 147 static void riscv_any_cpu_init(Object *obj) 148 { 149 CPURISCVState *env = &RISCV_CPU(obj)->env; 150 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); 151 set_priv_version(env, PRIV_VERSION_1_11_0); 152 } 153 154 #if defined(TARGET_RISCV64) 155 static void rv64_base_cpu_init(Object *obj) 156 { 157 CPURISCVState *env = &RISCV_CPU(obj)->env; 158 /* We set this in the realise function */ 159 set_misa(env, RV64); 160 } 161 162 static void rv64_sifive_u_cpu_init(Object *obj) 163 { 164 CPURISCVState *env = &RISCV_CPU(obj)->env; 165 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 166 set_priv_version(env, PRIV_VERSION_1_10_0); 167 } 168 169 static void rv64_sifive_e_cpu_init(Object *obj) 170 { 171 CPURISCVState *env = &RISCV_CPU(obj)->env; 172 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); 173 set_priv_version(env, PRIV_VERSION_1_10_0); 174 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 175 } 176 #else 177 static void rv32_base_cpu_init(Object *obj) 178 { 179 CPURISCVState *env = &RISCV_CPU(obj)->env; 180 /* We set this in the realise function */ 181 set_misa(env, RV32); 182 } 183 184 static void rv32_sifive_u_cpu_init(Object *obj) 185 { 186 CPURISCVState *env = &RISCV_CPU(obj)->env; 187 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 188 set_priv_version(env, PRIV_VERSION_1_10_0); 189 } 190 191 static void rv32_sifive_e_cpu_init(Object *obj) 192 { 193 CPURISCVState *env = &RISCV_CPU(obj)->env; 194 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); 195 set_priv_version(env, PRIV_VERSION_1_10_0); 196 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 197 } 198 199 static void rv32_ibex_cpu_init(Object *obj) 200 { 201 CPURISCVState *env = &RISCV_CPU(obj)->env; 202 set_misa(env, RV32 | RVI | RVM | RVC | RVU); 203 set_priv_version(env, PRIV_VERSION_1_10_0); 204 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 205 qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); 206 } 207 208 static void rv32_imafcu_nommu_cpu_init(Object *obj) 209 { 210 CPURISCVState *env = &RISCV_CPU(obj)->env; 211 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); 212 set_priv_version(env, PRIV_VERSION_1_10_0); 213 set_resetvec(env, DEFAULT_RSTVEC); 214 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 215 } 216 #endif 217 218 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 219 { 220 ObjectClass *oc; 221 char *typename; 222 char **cpuname; 223 224 cpuname = g_strsplit(cpu_model, ",", 1); 225 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 226 oc = object_class_by_name(typename); 227 g_strfreev(cpuname); 228 g_free(typename); 229 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 230 object_class_is_abstract(oc)) { 231 return NULL; 232 } 233 return oc; 234 } 235 236 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 237 { 238 RISCVCPU *cpu = RISCV_CPU(cs); 239 CPURISCVState *env = &cpu->env; 240 int i; 241 242 #if !defined(CONFIG_USER_ONLY) 243 if (riscv_has_ext(env, RVH)) { 244 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 245 } 246 #endif 247 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 248 #ifndef CONFIG_USER_ONLY 249 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); 250 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); 251 if (riscv_cpu_is_32bit(env)) { 252 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", 253 (target_ulong)(env->mstatus >> 32)); 254 } 255 if (riscv_has_ext(env, RVH)) { 256 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); 257 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", 258 (target_ulong)env->vsstatus); 259 } 260 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); 261 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); 262 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); 263 if (riscv_has_ext(env, RVH)) { 264 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); 265 } 266 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); 267 if (riscv_has_ext(env, RVH)) { 268 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); 269 } 270 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); 271 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); 272 if (riscv_has_ext(env, RVH)) { 273 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); 274 } 275 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); 276 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); 277 if (riscv_has_ext(env, RVH)) { 278 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); 279 } 280 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); 281 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); 282 if (riscv_has_ext(env, RVH)) { 283 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); 284 } 285 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); 286 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); 287 if (riscv_has_ext(env, RVH)) { 288 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); 289 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); 290 } 291 #endif 292 293 for (i = 0; i < 32; i++) { 294 qemu_fprintf(f, " %s " TARGET_FMT_lx, 295 riscv_int_regnames[i], env->gpr[i]); 296 if ((i & 3) == 3) { 297 qemu_fprintf(f, "\n"); 298 } 299 } 300 if (flags & CPU_DUMP_FPU) { 301 for (i = 0; i < 32; i++) { 302 qemu_fprintf(f, " %s %016" PRIx64, 303 riscv_fpr_regnames[i], env->fpr[i]); 304 if ((i & 3) == 3) { 305 qemu_fprintf(f, "\n"); 306 } 307 } 308 } 309 } 310 311 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 312 { 313 RISCVCPU *cpu = RISCV_CPU(cs); 314 CPURISCVState *env = &cpu->env; 315 env->pc = value; 316 } 317 318 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 319 const TranslationBlock *tb) 320 { 321 RISCVCPU *cpu = RISCV_CPU(cs); 322 CPURISCVState *env = &cpu->env; 323 env->pc = tb->pc; 324 } 325 326 static bool riscv_cpu_has_work(CPUState *cs) 327 { 328 #ifndef CONFIG_USER_ONLY 329 RISCVCPU *cpu = RISCV_CPU(cs); 330 CPURISCVState *env = &cpu->env; 331 /* 332 * Definition of the WFI instruction requires it to ignore the privilege 333 * mode and delegation registers, but respect individual enables 334 */ 335 return (env->mip & env->mie) != 0; 336 #else 337 return true; 338 #endif 339 } 340 341 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 342 target_ulong *data) 343 { 344 env->pc = data[0]; 345 } 346 347 static void riscv_cpu_reset(DeviceState *dev) 348 { 349 CPUState *cs = CPU(dev); 350 RISCVCPU *cpu = RISCV_CPU(cs); 351 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 352 CPURISCVState *env = &cpu->env; 353 354 mcc->parent_reset(dev); 355 #ifndef CONFIG_USER_ONLY 356 env->priv = PRV_M; 357 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 358 env->mcause = 0; 359 env->pc = env->resetvec; 360 env->two_stage_lookup = false; 361 #endif 362 cs->exception_index = RISCV_EXCP_NONE; 363 env->load_res = -1; 364 set_default_nan_mode(1, &env->fp_status); 365 } 366 367 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 368 { 369 RISCVCPU *cpu = RISCV_CPU(s); 370 if (riscv_cpu_is_32bit(&cpu->env)) { 371 info->print_insn = print_insn_riscv32; 372 } else { 373 info->print_insn = print_insn_riscv64; 374 } 375 } 376 377 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 378 { 379 CPUState *cs = CPU(dev); 380 RISCVCPU *cpu = RISCV_CPU(dev); 381 CPURISCVState *env = &cpu->env; 382 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 383 int priv_version = PRIV_VERSION_1_11_0; 384 int vext_version = VEXT_VERSION_0_07_1; 385 target_ulong target_misa = env->misa; 386 Error *local_err = NULL; 387 388 cpu_exec_realizefn(cs, &local_err); 389 if (local_err != NULL) { 390 error_propagate(errp, local_err); 391 return; 392 } 393 394 if (cpu->cfg.priv_spec) { 395 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 396 priv_version = PRIV_VERSION_1_11_0; 397 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 398 priv_version = PRIV_VERSION_1_10_0; 399 } else { 400 error_setg(errp, 401 "Unsupported privilege spec version '%s'", 402 cpu->cfg.priv_spec); 403 return; 404 } 405 } 406 407 set_priv_version(env, priv_version); 408 set_vext_version(env, vext_version); 409 410 if (cpu->cfg.mmu) { 411 set_feature(env, RISCV_FEATURE_MMU); 412 } 413 414 if (cpu->cfg.pmp) { 415 set_feature(env, RISCV_FEATURE_PMP); 416 417 /* 418 * Enhanced PMP should only be available 419 * on harts with PMP support 420 */ 421 if (cpu->cfg.epmp) { 422 set_feature(env, RISCV_FEATURE_EPMP); 423 } 424 } 425 426 set_resetvec(env, cpu->cfg.resetvec); 427 428 /* If only XLEN is set for misa, then set misa from properties */ 429 if (env->misa == RV32 || env->misa == RV64) { 430 /* Do some ISA extension error checking */ 431 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 432 error_setg(errp, 433 "I and E extensions are incompatible"); 434 return; 435 } 436 437 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 438 error_setg(errp, 439 "Either I or E extension must be set"); 440 return; 441 } 442 443 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 444 cpu->cfg.ext_a & cpu->cfg.ext_f & 445 cpu->cfg.ext_d)) { 446 warn_report("Setting G will also set IMAFD"); 447 cpu->cfg.ext_i = true; 448 cpu->cfg.ext_m = true; 449 cpu->cfg.ext_a = true; 450 cpu->cfg.ext_f = true; 451 cpu->cfg.ext_d = true; 452 } 453 454 /* Set the ISA extensions, checks should have happened above */ 455 if (cpu->cfg.ext_i) { 456 target_misa |= RVI; 457 } 458 if (cpu->cfg.ext_e) { 459 target_misa |= RVE; 460 } 461 if (cpu->cfg.ext_m) { 462 target_misa |= RVM; 463 } 464 if (cpu->cfg.ext_a) { 465 target_misa |= RVA; 466 } 467 if (cpu->cfg.ext_f) { 468 target_misa |= RVF; 469 } 470 if (cpu->cfg.ext_d) { 471 target_misa |= RVD; 472 } 473 if (cpu->cfg.ext_c) { 474 target_misa |= RVC; 475 } 476 if (cpu->cfg.ext_s) { 477 target_misa |= RVS; 478 } 479 if (cpu->cfg.ext_u) { 480 target_misa |= RVU; 481 } 482 if (cpu->cfg.ext_h) { 483 target_misa |= RVH; 484 } 485 if (cpu->cfg.ext_v) { 486 target_misa |= RVV; 487 if (!is_power_of_2(cpu->cfg.vlen)) { 488 error_setg(errp, 489 "Vector extension VLEN must be power of 2"); 490 return; 491 } 492 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 493 error_setg(errp, 494 "Vector extension implementation only supports VLEN " 495 "in the range [128, %d]", RV_VLEN_MAX); 496 return; 497 } 498 if (!is_power_of_2(cpu->cfg.elen)) { 499 error_setg(errp, 500 "Vector extension ELEN must be power of 2"); 501 return; 502 } 503 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 504 error_setg(errp, 505 "Vector extension implementation only supports ELEN " 506 "in the range [8, 64]"); 507 return; 508 } 509 if (cpu->cfg.vext_spec) { 510 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { 511 vext_version = VEXT_VERSION_0_07_1; 512 } else { 513 error_setg(errp, 514 "Unsupported vector spec version '%s'", 515 cpu->cfg.vext_spec); 516 return; 517 } 518 } else { 519 qemu_log("vector version is not specified, " 520 "use the default value v0.7.1\n"); 521 } 522 set_vext_version(env, vext_version); 523 } 524 525 set_misa(env, target_misa); 526 } 527 528 riscv_cpu_register_gdb_regs_for_features(cs); 529 530 qemu_init_vcpu(cs); 531 cpu_reset(cs); 532 533 mcc->parent_realize(dev, errp); 534 } 535 536 static void riscv_cpu_init(Object *obj) 537 { 538 RISCVCPU *cpu = RISCV_CPU(obj); 539 540 cpu_set_cpustate_pointers(cpu); 541 } 542 543 static Property riscv_cpu_properties[] = { 544 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 545 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 546 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 547 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 548 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 549 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 550 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 551 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 552 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 553 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 554 /* This is experimental so mark with 'x-' */ 555 DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), 556 DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), 557 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 558 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 559 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 560 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 561 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 562 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 563 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 564 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 565 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 566 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 567 568 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 569 DEFINE_PROP_END_OF_LIST(), 570 }; 571 572 static gchar *riscv_gdb_arch_name(CPUState *cs) 573 { 574 RISCVCPU *cpu = RISCV_CPU(cs); 575 CPURISCVState *env = &cpu->env; 576 577 if (riscv_cpu_is_32bit(env)) { 578 return g_strdup("riscv:rv32"); 579 } else { 580 return g_strdup("riscv:rv64"); 581 } 582 } 583 584 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 585 { 586 RISCVCPU *cpu = RISCV_CPU(cs); 587 588 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 589 return cpu->dyn_csr_xml; 590 } 591 592 return NULL; 593 } 594 595 #include "hw/core/tcg-cpu-ops.h" 596 597 static struct TCGCPUOps riscv_tcg_ops = { 598 .initialize = riscv_translate_init, 599 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 600 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 601 .tlb_fill = riscv_cpu_tlb_fill, 602 603 #ifndef CONFIG_USER_ONLY 604 .do_interrupt = riscv_cpu_do_interrupt, 605 .do_transaction_failed = riscv_cpu_do_transaction_failed, 606 .do_unaligned_access = riscv_cpu_do_unaligned_access, 607 #endif /* !CONFIG_USER_ONLY */ 608 }; 609 610 static void riscv_cpu_class_init(ObjectClass *c, void *data) 611 { 612 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 613 CPUClass *cc = CPU_CLASS(c); 614 DeviceClass *dc = DEVICE_CLASS(c); 615 616 device_class_set_parent_realize(dc, riscv_cpu_realize, 617 &mcc->parent_realize); 618 619 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 620 621 cc->class_by_name = riscv_cpu_class_by_name; 622 cc->has_work = riscv_cpu_has_work; 623 cc->dump_state = riscv_cpu_dump_state; 624 cc->set_pc = riscv_cpu_set_pc; 625 cc->gdb_read_register = riscv_cpu_gdb_read_register; 626 cc->gdb_write_register = riscv_cpu_gdb_write_register; 627 cc->gdb_num_core_regs = 33; 628 #if defined(TARGET_RISCV32) 629 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 630 #elif defined(TARGET_RISCV64) 631 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 632 #endif 633 cc->gdb_stop_before_watchpoint = true; 634 cc->disas_set_info = riscv_cpu_disas_set_info; 635 #ifndef CONFIG_USER_ONLY 636 cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; 637 /* For now, mark unmigratable: */ 638 cc->vmsd = &vmstate_riscv_cpu; 639 cc->write_elf64_note = riscv_cpu_write_elf64_note; 640 cc->write_elf32_note = riscv_cpu_write_elf32_note; 641 #endif 642 cc->gdb_arch_name = riscv_gdb_arch_name; 643 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 644 cc->tcg_ops = &riscv_tcg_ops; 645 646 device_class_set_props(dc, riscv_cpu_properties); 647 } 648 649 char *riscv_isa_string(RISCVCPU *cpu) 650 { 651 int i; 652 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 653 char *isa_str = g_new(char, maxlen); 654 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 655 for (i = 0; i < sizeof(riscv_exts); i++) { 656 if (cpu->env.misa & RV(riscv_exts[i])) { 657 *p++ = qemu_tolower(riscv_exts[i]); 658 } 659 } 660 *p = '\0'; 661 return isa_str; 662 } 663 664 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 665 { 666 ObjectClass *class_a = (ObjectClass *)a; 667 ObjectClass *class_b = (ObjectClass *)b; 668 const char *name_a, *name_b; 669 670 name_a = object_class_get_name(class_a); 671 name_b = object_class_get_name(class_b); 672 return strcmp(name_a, name_b); 673 } 674 675 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 676 { 677 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 678 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 679 680 qemu_printf("%.*s\n", len, typename); 681 } 682 683 void riscv_cpu_list(void) 684 { 685 GSList *list; 686 687 list = object_class_get_list(TYPE_RISCV_CPU, false); 688 list = g_slist_sort(list, riscv_cpu_list_compare); 689 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 690 g_slist_free(list); 691 } 692 693 #define DEFINE_CPU(type_name, initfn) \ 694 { \ 695 .name = type_name, \ 696 .parent = TYPE_RISCV_CPU, \ 697 .instance_init = initfn \ 698 } 699 700 static const TypeInfo riscv_cpu_type_infos[] = { 701 { 702 .name = TYPE_RISCV_CPU, 703 .parent = TYPE_CPU, 704 .instance_size = sizeof(RISCVCPU), 705 .instance_align = __alignof__(RISCVCPU), 706 .instance_init = riscv_cpu_init, 707 .abstract = true, 708 .class_size = sizeof(RISCVCPUClass), 709 .class_init = riscv_cpu_class_init, 710 }, 711 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 712 #if defined(TARGET_RISCV32) 713 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 714 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 715 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 716 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 717 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 718 #elif defined(TARGET_RISCV64) 719 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 720 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 721 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 722 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 723 #endif 724 }; 725 726 DEFINE_TYPES(riscv_cpu_type_infos) 727