1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "qemu/error-report.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "fpu/softfloat-helpers.h" 36 #include "sysemu/kvm.h" 37 #include "kvm_riscv.h" 38 #include "tcg/tcg.h" 39 40 /* RISC-V CPU definitions */ 41 42 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 43 (QEMU_VERSION_MINOR << 8) | \ 44 (QEMU_VERSION_MICRO)) 45 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 46 47 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 48 49 struct isa_ext_data { 50 const char *name; 51 int min_version; 52 int ext_enable_offset; 53 }; 54 55 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ 56 {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 57 58 /* 59 * Here are the ordering rules of extension naming defined by RISC-V 60 * specification : 61 * 1. All extensions should be separated from other multi-letter extensions 62 * by an underscore. 63 * 2. The first letter following the 'Z' conventionally indicates the most 64 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 65 * If multiple 'Z' extensions are named, they should be ordered first 66 * by category, then alphabetically within a category. 67 * 3. Standard supervisor-level extensions (starts with 'S') should be 68 * listed after standard unprivileged extensions. If multiple 69 * supervisor-level extensions are listed, they should be ordered 70 * alphabetically. 71 * 4. Non-standard extensions (starts with 'X') must be listed after all 72 * standard extensions. They must be separated from other multi-letter 73 * extensions by an underscore. 74 * 75 * Single letter extensions are checked in riscv_cpu_validate_misa_priv() 76 * instead. 77 */ 78 static const struct isa_ext_data isa_edata_arr[] = { 79 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), 80 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), 81 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), 82 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), 83 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), 84 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), 85 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), 86 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), 87 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), 88 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), 89 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), 90 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), 91 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), 92 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), 93 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), 94 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), 95 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), 96 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), 97 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), 98 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), 99 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), 100 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), 101 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), 102 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), 103 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), 104 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), 105 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), 106 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), 107 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), 108 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), 109 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), 110 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), 111 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), 112 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), 113 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), 114 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), 115 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), 116 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), 117 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), 118 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), 119 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), 120 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), 121 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), 122 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), 123 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), 124 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), 125 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), 126 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), 127 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), 128 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), 129 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), 130 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), 131 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), 132 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), 133 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 134 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 135 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), 136 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), 137 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 138 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), 139 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), 140 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 141 }; 142 143 static bool isa_ext_is_enabled(RISCVCPU *cpu, 144 const struct isa_ext_data *edata) 145 { 146 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 147 148 return *ext_enabled; 149 } 150 151 static void isa_ext_update_enabled(RISCVCPU *cpu, 152 const struct isa_ext_data *edata, bool en) 153 { 154 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 155 156 *ext_enabled = en; 157 } 158 159 const char * const riscv_int_regnames[] = { 160 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 161 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 162 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 163 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 164 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 165 }; 166 167 const char * const riscv_int_regnamesh[] = { 168 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 169 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 170 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 171 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 172 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 173 "x30h/t5h", "x31h/t6h" 174 }; 175 176 const char * const riscv_fpr_regnames[] = { 177 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 178 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 179 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 180 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 181 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 182 "f30/ft10", "f31/ft11" 183 }; 184 185 static const char * const riscv_excp_names[] = { 186 "misaligned_fetch", 187 "fault_fetch", 188 "illegal_instruction", 189 "breakpoint", 190 "misaligned_load", 191 "fault_load", 192 "misaligned_store", 193 "fault_store", 194 "user_ecall", 195 "supervisor_ecall", 196 "hypervisor_ecall", 197 "machine_ecall", 198 "exec_page_fault", 199 "load_page_fault", 200 "reserved", 201 "store_page_fault", 202 "reserved", 203 "reserved", 204 "reserved", 205 "reserved", 206 "guest_exec_page_fault", 207 "guest_load_page_fault", 208 "reserved", 209 "guest_store_page_fault", 210 }; 211 212 static const char * const riscv_intr_names[] = { 213 "u_software", 214 "s_software", 215 "vs_software", 216 "m_software", 217 "u_timer", 218 "s_timer", 219 "vs_timer", 220 "m_timer", 221 "u_external", 222 "s_external", 223 "vs_external", 224 "m_external", 225 "reserved", 226 "reserved", 227 "reserved", 228 "reserved" 229 }; 230 231 static void riscv_cpu_add_user_properties(Object *obj); 232 233 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 234 { 235 if (async) { 236 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 237 riscv_intr_names[cause] : "(unknown)"; 238 } else { 239 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 240 riscv_excp_names[cause] : "(unknown)"; 241 } 242 } 243 244 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 245 { 246 env->misa_mxl_max = env->misa_mxl = mxl; 247 env->misa_ext_mask = env->misa_ext = ext; 248 } 249 250 static void set_priv_version(CPURISCVState *env, int priv_ver) 251 { 252 env->priv_ver = priv_ver; 253 } 254 255 static void set_vext_version(CPURISCVState *env, int vext_ver) 256 { 257 env->vext_ver = vext_ver; 258 } 259 260 #ifndef CONFIG_USER_ONLY 261 static uint8_t satp_mode_from_str(const char *satp_mode_str) 262 { 263 if (!strncmp(satp_mode_str, "mbare", 5)) { 264 return VM_1_10_MBARE; 265 } 266 267 if (!strncmp(satp_mode_str, "sv32", 4)) { 268 return VM_1_10_SV32; 269 } 270 271 if (!strncmp(satp_mode_str, "sv39", 4)) { 272 return VM_1_10_SV39; 273 } 274 275 if (!strncmp(satp_mode_str, "sv48", 4)) { 276 return VM_1_10_SV48; 277 } 278 279 if (!strncmp(satp_mode_str, "sv57", 4)) { 280 return VM_1_10_SV57; 281 } 282 283 if (!strncmp(satp_mode_str, "sv64", 4)) { 284 return VM_1_10_SV64; 285 } 286 287 g_assert_not_reached(); 288 } 289 290 uint8_t satp_mode_max_from_map(uint32_t map) 291 { 292 /* map here has at least one bit set, so no problem with clz */ 293 return 31 - __builtin_clz(map); 294 } 295 296 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) 297 { 298 if (is_32_bit) { 299 switch (satp_mode) { 300 case VM_1_10_SV32: 301 return "sv32"; 302 case VM_1_10_MBARE: 303 return "none"; 304 } 305 } else { 306 switch (satp_mode) { 307 case VM_1_10_SV64: 308 return "sv64"; 309 case VM_1_10_SV57: 310 return "sv57"; 311 case VM_1_10_SV48: 312 return "sv48"; 313 case VM_1_10_SV39: 314 return "sv39"; 315 case VM_1_10_MBARE: 316 return "none"; 317 } 318 } 319 320 g_assert_not_reached(); 321 } 322 323 static void set_satp_mode_max_supported(RISCVCPU *cpu, 324 uint8_t satp_mode) 325 { 326 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 327 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; 328 329 for (int i = 0; i <= satp_mode; ++i) { 330 if (valid_vm[i]) { 331 cpu->cfg.satp_mode.supported |= (1 << i); 332 } 333 } 334 } 335 336 /* Set the satp mode to the max supported */ 337 static void set_satp_mode_default_map(RISCVCPU *cpu) 338 { 339 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; 340 } 341 #endif 342 343 static void riscv_any_cpu_init(Object *obj) 344 { 345 CPURISCVState *env = &RISCV_CPU(obj)->env; 346 #if defined(TARGET_RISCV32) 347 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 348 #elif defined(TARGET_RISCV64) 349 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 350 #endif 351 352 #ifndef CONFIG_USER_ONLY 353 set_satp_mode_max_supported(RISCV_CPU(obj), 354 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? 355 VM_1_10_SV32 : VM_1_10_SV57); 356 #endif 357 358 set_priv_version(env, PRIV_VERSION_1_12_0); 359 } 360 361 #if defined(TARGET_RISCV64) 362 static void rv64_base_cpu_init(Object *obj) 363 { 364 CPURISCVState *env = &RISCV_CPU(obj)->env; 365 /* We set this in the realise function */ 366 set_misa(env, MXL_RV64, 0); 367 riscv_cpu_add_user_properties(obj); 368 /* Set latest version of privileged specification */ 369 set_priv_version(env, PRIV_VERSION_1_12_0); 370 #ifndef CONFIG_USER_ONLY 371 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 372 #endif 373 } 374 375 static void rv64_sifive_u_cpu_init(Object *obj) 376 { 377 CPURISCVState *env = &RISCV_CPU(obj)->env; 378 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 379 set_priv_version(env, PRIV_VERSION_1_10_0); 380 #ifndef CONFIG_USER_ONLY 381 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); 382 #endif 383 } 384 385 static void rv64_sifive_e_cpu_init(Object *obj) 386 { 387 CPURISCVState *env = &RISCV_CPU(obj)->env; 388 RISCVCPU *cpu = RISCV_CPU(obj); 389 390 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 391 set_priv_version(env, PRIV_VERSION_1_10_0); 392 cpu->cfg.mmu = false; 393 #ifndef CONFIG_USER_ONLY 394 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 395 #endif 396 } 397 398 static void rv64_thead_c906_cpu_init(Object *obj) 399 { 400 CPURISCVState *env = &RISCV_CPU(obj)->env; 401 RISCVCPU *cpu = RISCV_CPU(obj); 402 403 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); 404 set_priv_version(env, PRIV_VERSION_1_11_0); 405 406 cpu->cfg.ext_zfh = true; 407 cpu->cfg.mmu = true; 408 cpu->cfg.ext_xtheadba = true; 409 cpu->cfg.ext_xtheadbb = true; 410 cpu->cfg.ext_xtheadbs = true; 411 cpu->cfg.ext_xtheadcmo = true; 412 cpu->cfg.ext_xtheadcondmov = true; 413 cpu->cfg.ext_xtheadfmemidx = true; 414 cpu->cfg.ext_xtheadmac = true; 415 cpu->cfg.ext_xtheadmemidx = true; 416 cpu->cfg.ext_xtheadmempair = true; 417 cpu->cfg.ext_xtheadsync = true; 418 419 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 420 #ifndef CONFIG_USER_ONLY 421 set_satp_mode_max_supported(cpu, VM_1_10_SV39); 422 #endif 423 } 424 425 static void rv64_veyron_v1_cpu_init(Object *obj) 426 { 427 CPURISCVState *env = &RISCV_CPU(obj)->env; 428 RISCVCPU *cpu = RISCV_CPU(obj); 429 430 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); 431 env->priv_ver = PRIV_VERSION_1_12_0; 432 433 /* Enable ISA extensions */ 434 cpu->cfg.mmu = true; 435 cpu->cfg.ext_icbom = true; 436 cpu->cfg.cbom_blocksize = 64; 437 cpu->cfg.cboz_blocksize = 64; 438 cpu->cfg.ext_icboz = true; 439 cpu->cfg.ext_smaia = true; 440 cpu->cfg.ext_ssaia = true; 441 cpu->cfg.ext_sscofpmf = true; 442 cpu->cfg.ext_sstc = true; 443 cpu->cfg.ext_svinval = true; 444 cpu->cfg.ext_svnapot = true; 445 cpu->cfg.ext_svpbmt = true; 446 cpu->cfg.ext_smstateen = true; 447 cpu->cfg.ext_zba = true; 448 cpu->cfg.ext_zbb = true; 449 cpu->cfg.ext_zbc = true; 450 cpu->cfg.ext_zbs = true; 451 cpu->cfg.ext_XVentanaCondOps = true; 452 453 cpu->cfg.mvendorid = VEYRON_V1_MVENDORID; 454 cpu->cfg.marchid = VEYRON_V1_MARCHID; 455 cpu->cfg.mimpid = VEYRON_V1_MIMPID; 456 457 #ifndef CONFIG_USER_ONLY 458 set_satp_mode_max_supported(cpu, VM_1_10_SV48); 459 #endif 460 } 461 462 static void rv128_base_cpu_init(Object *obj) 463 { 464 if (qemu_tcg_mttcg_enabled()) { 465 /* Missing 128-bit aligned atomics */ 466 error_report("128-bit RISC-V currently does not work with Multi " 467 "Threaded TCG. Please use: -accel tcg,thread=single"); 468 exit(EXIT_FAILURE); 469 } 470 CPURISCVState *env = &RISCV_CPU(obj)->env; 471 /* We set this in the realise function */ 472 set_misa(env, MXL_RV128, 0); 473 riscv_cpu_add_user_properties(obj); 474 /* Set latest version of privileged specification */ 475 set_priv_version(env, PRIV_VERSION_1_12_0); 476 #ifndef CONFIG_USER_ONLY 477 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 478 #endif 479 } 480 #else 481 static void rv32_base_cpu_init(Object *obj) 482 { 483 CPURISCVState *env = &RISCV_CPU(obj)->env; 484 /* We set this in the realise function */ 485 set_misa(env, MXL_RV32, 0); 486 riscv_cpu_add_user_properties(obj); 487 /* Set latest version of privileged specification */ 488 set_priv_version(env, PRIV_VERSION_1_12_0); 489 #ifndef CONFIG_USER_ONLY 490 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 491 #endif 492 } 493 494 static void rv32_sifive_u_cpu_init(Object *obj) 495 { 496 CPURISCVState *env = &RISCV_CPU(obj)->env; 497 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 498 set_priv_version(env, PRIV_VERSION_1_10_0); 499 #ifndef CONFIG_USER_ONLY 500 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 501 #endif 502 } 503 504 static void rv32_sifive_e_cpu_init(Object *obj) 505 { 506 CPURISCVState *env = &RISCV_CPU(obj)->env; 507 RISCVCPU *cpu = RISCV_CPU(obj); 508 509 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 510 set_priv_version(env, PRIV_VERSION_1_10_0); 511 cpu->cfg.mmu = false; 512 #ifndef CONFIG_USER_ONLY 513 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 514 #endif 515 } 516 517 static void rv32_ibex_cpu_init(Object *obj) 518 { 519 CPURISCVState *env = &RISCV_CPU(obj)->env; 520 RISCVCPU *cpu = RISCV_CPU(obj); 521 522 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 523 set_priv_version(env, PRIV_VERSION_1_11_0); 524 cpu->cfg.mmu = false; 525 #ifndef CONFIG_USER_ONLY 526 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 527 #endif 528 cpu->cfg.epmp = true; 529 } 530 531 static void rv32_imafcu_nommu_cpu_init(Object *obj) 532 { 533 CPURISCVState *env = &RISCV_CPU(obj)->env; 534 RISCVCPU *cpu = RISCV_CPU(obj); 535 536 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 537 set_priv_version(env, PRIV_VERSION_1_10_0); 538 cpu->cfg.mmu = false; 539 #ifndef CONFIG_USER_ONLY 540 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 541 #endif 542 } 543 #endif 544 545 #if defined(CONFIG_KVM) 546 static void riscv_host_cpu_init(Object *obj) 547 { 548 CPURISCVState *env = &RISCV_CPU(obj)->env; 549 #if defined(TARGET_RISCV32) 550 set_misa(env, MXL_RV32, 0); 551 #elif defined(TARGET_RISCV64) 552 set_misa(env, MXL_RV64, 0); 553 #endif 554 riscv_cpu_add_user_properties(obj); 555 } 556 #endif 557 558 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 559 { 560 ObjectClass *oc; 561 char *typename; 562 char **cpuname; 563 564 cpuname = g_strsplit(cpu_model, ",", 1); 565 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 566 oc = object_class_by_name(typename); 567 g_strfreev(cpuname); 568 g_free(typename); 569 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 570 object_class_is_abstract(oc)) { 571 return NULL; 572 } 573 return oc; 574 } 575 576 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 577 { 578 RISCVCPU *cpu = RISCV_CPU(cs); 579 CPURISCVState *env = &cpu->env; 580 int i; 581 582 #if !defined(CONFIG_USER_ONLY) 583 if (riscv_has_ext(env, RVH)) { 584 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); 585 } 586 #endif 587 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 588 #ifndef CONFIG_USER_ONLY 589 { 590 static const int dump_csrs[] = { 591 CSR_MHARTID, 592 CSR_MSTATUS, 593 CSR_MSTATUSH, 594 /* 595 * CSR_SSTATUS is intentionally omitted here as its value 596 * can be figured out by looking at CSR_MSTATUS 597 */ 598 CSR_HSTATUS, 599 CSR_VSSTATUS, 600 CSR_MIP, 601 CSR_MIE, 602 CSR_MIDELEG, 603 CSR_HIDELEG, 604 CSR_MEDELEG, 605 CSR_HEDELEG, 606 CSR_MTVEC, 607 CSR_STVEC, 608 CSR_VSTVEC, 609 CSR_MEPC, 610 CSR_SEPC, 611 CSR_VSEPC, 612 CSR_MCAUSE, 613 CSR_SCAUSE, 614 CSR_VSCAUSE, 615 CSR_MTVAL, 616 CSR_STVAL, 617 CSR_HTVAL, 618 CSR_MTVAL2, 619 CSR_MSCRATCH, 620 CSR_SSCRATCH, 621 CSR_SATP, 622 CSR_MMTE, 623 CSR_UPMBASE, 624 CSR_UPMMASK, 625 CSR_SPMBASE, 626 CSR_SPMMASK, 627 CSR_MPMBASE, 628 CSR_MPMMASK, 629 }; 630 631 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 632 int csrno = dump_csrs[i]; 633 target_ulong val = 0; 634 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 635 636 /* 637 * Rely on the smode, hmode, etc, predicates within csr.c 638 * to do the filtering of the registers that are present. 639 */ 640 if (res == RISCV_EXCP_NONE) { 641 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 642 csr_ops[csrno].name, val); 643 } 644 } 645 } 646 #endif 647 648 for (i = 0; i < 32; i++) { 649 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 650 riscv_int_regnames[i], env->gpr[i]); 651 if ((i & 3) == 3) { 652 qemu_fprintf(f, "\n"); 653 } 654 } 655 if (flags & CPU_DUMP_FPU) { 656 for (i = 0; i < 32; i++) { 657 qemu_fprintf(f, " %-8s %016" PRIx64, 658 riscv_fpr_regnames[i], env->fpr[i]); 659 if ((i & 3) == 3) { 660 qemu_fprintf(f, "\n"); 661 } 662 } 663 } 664 } 665 666 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 667 { 668 RISCVCPU *cpu = RISCV_CPU(cs); 669 CPURISCVState *env = &cpu->env; 670 671 if (env->xl == MXL_RV32) { 672 env->pc = (int32_t)value; 673 } else { 674 env->pc = value; 675 } 676 } 677 678 static vaddr riscv_cpu_get_pc(CPUState *cs) 679 { 680 RISCVCPU *cpu = RISCV_CPU(cs); 681 CPURISCVState *env = &cpu->env; 682 683 /* Match cpu_get_tb_cpu_state. */ 684 if (env->xl == MXL_RV32) { 685 return env->pc & UINT32_MAX; 686 } 687 return env->pc; 688 } 689 690 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 691 const TranslationBlock *tb) 692 { 693 RISCVCPU *cpu = RISCV_CPU(cs); 694 CPURISCVState *env = &cpu->env; 695 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 696 697 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 698 699 if (xl == MXL_RV32) { 700 env->pc = (int32_t) tb->pc; 701 } else { 702 env->pc = tb->pc; 703 } 704 } 705 706 static bool riscv_cpu_has_work(CPUState *cs) 707 { 708 #ifndef CONFIG_USER_ONLY 709 RISCVCPU *cpu = RISCV_CPU(cs); 710 CPURISCVState *env = &cpu->env; 711 /* 712 * Definition of the WFI instruction requires it to ignore the privilege 713 * mode and delegation registers, but respect individual enables 714 */ 715 return riscv_cpu_all_pending(env) != 0; 716 #else 717 return true; 718 #endif 719 } 720 721 static void riscv_restore_state_to_opc(CPUState *cs, 722 const TranslationBlock *tb, 723 const uint64_t *data) 724 { 725 RISCVCPU *cpu = RISCV_CPU(cs); 726 CPURISCVState *env = &cpu->env; 727 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 728 729 if (xl == MXL_RV32) { 730 env->pc = (int32_t)data[0]; 731 } else { 732 env->pc = data[0]; 733 } 734 env->bins = data[1]; 735 } 736 737 static void riscv_cpu_reset_hold(Object *obj) 738 { 739 #ifndef CONFIG_USER_ONLY 740 uint8_t iprio; 741 int i, irq, rdzero; 742 #endif 743 CPUState *cs = CPU(obj); 744 RISCVCPU *cpu = RISCV_CPU(cs); 745 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 746 CPURISCVState *env = &cpu->env; 747 748 if (mcc->parent_phases.hold) { 749 mcc->parent_phases.hold(obj); 750 } 751 #ifndef CONFIG_USER_ONLY 752 env->misa_mxl = env->misa_mxl_max; 753 env->priv = PRV_M; 754 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 755 if (env->misa_mxl > MXL_RV32) { 756 /* 757 * The reset status of SXL/UXL is undefined, but mstatus is WARL 758 * and we must ensure that the value after init is valid for read. 759 */ 760 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 761 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 762 if (riscv_has_ext(env, RVH)) { 763 env->vsstatus = set_field(env->vsstatus, 764 MSTATUS64_SXL, env->misa_mxl); 765 env->vsstatus = set_field(env->vsstatus, 766 MSTATUS64_UXL, env->misa_mxl); 767 env->mstatus_hs = set_field(env->mstatus_hs, 768 MSTATUS64_SXL, env->misa_mxl); 769 env->mstatus_hs = set_field(env->mstatus_hs, 770 MSTATUS64_UXL, env->misa_mxl); 771 } 772 } 773 env->mcause = 0; 774 env->miclaim = MIP_SGEIP; 775 env->pc = env->resetvec; 776 env->bins = 0; 777 env->two_stage_lookup = false; 778 779 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | 780 (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); 781 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | 782 (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); 783 784 /* Initialized default priorities of local interrupts. */ 785 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 786 iprio = riscv_cpu_default_priority(i); 787 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 788 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 789 env->hviprio[i] = 0; 790 } 791 i = 0; 792 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 793 if (!rdzero) { 794 env->hviprio[irq] = env->miprio[irq]; 795 } 796 i++; 797 } 798 /* mmte is supposed to have pm.current hardwired to 1 */ 799 env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); 800 #endif 801 env->xl = riscv_cpu_mxl(env); 802 riscv_cpu_update_mask(env); 803 cs->exception_index = RISCV_EXCP_NONE; 804 env->load_res = -1; 805 set_default_nan_mode(1, &env->fp_status); 806 807 #ifndef CONFIG_USER_ONLY 808 if (cpu->cfg.debug) { 809 riscv_trigger_init(env); 810 } 811 812 if (kvm_enabled()) { 813 kvm_riscv_reset_vcpu(cpu); 814 } 815 #endif 816 } 817 818 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 819 { 820 RISCVCPU *cpu = RISCV_CPU(s); 821 822 switch (riscv_cpu_mxl(&cpu->env)) { 823 case MXL_RV32: 824 info->print_insn = print_insn_riscv32; 825 break; 826 case MXL_RV64: 827 info->print_insn = print_insn_riscv64; 828 break; 829 case MXL_RV128: 830 info->print_insn = print_insn_riscv128; 831 break; 832 default: 833 g_assert_not_reached(); 834 } 835 } 836 837 /* 838 * Check consistency between chosen extensions while setting 839 * cpu->cfg accordingly. 840 */ 841 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 842 { 843 CPURISCVState *env = &cpu->env; 844 845 /* Do some ISA extension error checking */ 846 if (riscv_has_ext(env, RVG) && 847 !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && 848 riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && 849 riscv_has_ext(env, RVD) && 850 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 851 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 852 cpu->cfg.ext_icsr = true; 853 cpu->cfg.ext_ifencei = true; 854 855 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; 856 env->misa_ext_mask = env->misa_ext; 857 } 858 859 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 860 error_setg(errp, 861 "I and E extensions are incompatible"); 862 return; 863 } 864 865 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 866 error_setg(errp, 867 "Either I or E extension must be set"); 868 return; 869 } 870 871 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 872 error_setg(errp, 873 "Setting S extension without U extension is illegal"); 874 return; 875 } 876 877 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 878 error_setg(errp, 879 "H depends on an I base integer ISA with 32 x registers"); 880 return; 881 } 882 883 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 884 error_setg(errp, "H extension implicitly requires S-mode"); 885 return; 886 } 887 888 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { 889 error_setg(errp, "F extension requires Zicsr"); 890 return; 891 } 892 893 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 894 error_setg(errp, "Zawrs extension requires A extension"); 895 return; 896 } 897 898 if (cpu->cfg.ext_zfh) { 899 cpu->cfg.ext_zfhmin = true; 900 } 901 902 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 903 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 904 return; 905 } 906 907 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 908 error_setg(errp, "D extension requires F extension"); 909 return; 910 } 911 912 /* The V vector extension depends on the Zve64d extension */ 913 if (riscv_has_ext(env, RVV)) { 914 cpu->cfg.ext_zve64d = true; 915 } 916 917 /* The Zve64d extension depends on the Zve64f extension */ 918 if (cpu->cfg.ext_zve64d) { 919 cpu->cfg.ext_zve64f = true; 920 } 921 922 /* The Zve64f extension depends on the Zve32f extension */ 923 if (cpu->cfg.ext_zve64f) { 924 cpu->cfg.ext_zve32f = true; 925 } 926 927 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 928 error_setg(errp, "Zve64d/V extensions require D extension"); 929 return; 930 } 931 932 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 933 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 934 return; 935 } 936 937 if (cpu->cfg.ext_zvfh) { 938 cpu->cfg.ext_zvfhmin = true; 939 } 940 941 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 942 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 943 return; 944 } 945 946 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 947 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 948 return; 949 } 950 951 /* Set the ISA extensions, checks should have happened above */ 952 if (cpu->cfg.ext_zhinx) { 953 cpu->cfg.ext_zhinxmin = true; 954 } 955 956 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 957 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 958 return; 959 } 960 961 if (cpu->cfg.ext_zfinx) { 962 if (!cpu->cfg.ext_icsr) { 963 error_setg(errp, "Zfinx extension requires Zicsr"); 964 return; 965 } 966 if (riscv_has_ext(env, RVF)) { 967 error_setg(errp, 968 "Zfinx cannot be supported together with F extension"); 969 return; 970 } 971 } 972 973 if (cpu->cfg.ext_zce) { 974 cpu->cfg.ext_zca = true; 975 cpu->cfg.ext_zcb = true; 976 cpu->cfg.ext_zcmp = true; 977 cpu->cfg.ext_zcmt = true; 978 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 979 cpu->cfg.ext_zcf = true; 980 } 981 } 982 983 if (riscv_has_ext(env, RVC)) { 984 cpu->cfg.ext_zca = true; 985 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 986 cpu->cfg.ext_zcf = true; 987 } 988 if (riscv_has_ext(env, RVD)) { 989 cpu->cfg.ext_zcd = true; 990 } 991 } 992 993 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 994 error_setg(errp, "Zcf extension is only relevant to RV32"); 995 return; 996 } 997 998 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 999 error_setg(errp, "Zcf extension requires F extension"); 1000 return; 1001 } 1002 1003 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 1004 error_setg(errp, "Zcd extension requires D extension"); 1005 return; 1006 } 1007 1008 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 1009 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 1010 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 1011 "extension"); 1012 return; 1013 } 1014 1015 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 1016 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 1017 "Zcd extension"); 1018 return; 1019 } 1020 1021 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { 1022 error_setg(errp, "Zcmt extension requires Zicsr extension"); 1023 return; 1024 } 1025 1026 if (cpu->cfg.ext_zk) { 1027 cpu->cfg.ext_zkn = true; 1028 cpu->cfg.ext_zkr = true; 1029 cpu->cfg.ext_zkt = true; 1030 } 1031 1032 if (cpu->cfg.ext_zkn) { 1033 cpu->cfg.ext_zbkb = true; 1034 cpu->cfg.ext_zbkc = true; 1035 cpu->cfg.ext_zbkx = true; 1036 cpu->cfg.ext_zkne = true; 1037 cpu->cfg.ext_zknd = true; 1038 cpu->cfg.ext_zknh = true; 1039 } 1040 1041 if (cpu->cfg.ext_zks) { 1042 cpu->cfg.ext_zbkb = true; 1043 cpu->cfg.ext_zbkc = true; 1044 cpu->cfg.ext_zbkx = true; 1045 cpu->cfg.ext_zksed = true; 1046 cpu->cfg.ext_zksh = true; 1047 } 1048 1049 if (riscv_has_ext(env, RVV)) { 1050 int vext_version = VEXT_VERSION_1_00_0; 1051 if (!is_power_of_2(cpu->cfg.vlen)) { 1052 error_setg(errp, 1053 "Vector extension VLEN must be power of 2"); 1054 return; 1055 } 1056 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 1057 error_setg(errp, 1058 "Vector extension implementation only supports VLEN " 1059 "in the range [128, %d]", RV_VLEN_MAX); 1060 return; 1061 } 1062 if (!is_power_of_2(cpu->cfg.elen)) { 1063 error_setg(errp, 1064 "Vector extension ELEN must be power of 2"); 1065 return; 1066 } 1067 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 1068 error_setg(errp, 1069 "Vector extension implementation only supports ELEN " 1070 "in the range [8, 64]"); 1071 return; 1072 } 1073 if (cpu->cfg.vext_spec) { 1074 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 1075 vext_version = VEXT_VERSION_1_00_0; 1076 } else { 1077 error_setg(errp, 1078 "Unsupported vector spec version '%s'", 1079 cpu->cfg.vext_spec); 1080 return; 1081 } 1082 } else { 1083 qemu_log("vector version is not specified, " 1084 "use the default value v1.0\n"); 1085 } 1086 set_vext_version(env, vext_version); 1087 } 1088 } 1089 1090 #ifndef CONFIG_USER_ONLY 1091 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) 1092 { 1093 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 1094 uint8_t satp_mode_map_max; 1095 uint8_t satp_mode_supported_max = 1096 satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 1097 1098 if (cpu->cfg.satp_mode.map == 0) { 1099 if (cpu->cfg.satp_mode.init == 0) { 1100 /* If unset by the user, we fallback to the default satp mode. */ 1101 set_satp_mode_default_map(cpu); 1102 } else { 1103 /* 1104 * Find the lowest level that was disabled and then enable the 1105 * first valid level below which can be found in 1106 * valid_vm_1_10_32/64. 1107 */ 1108 for (int i = 1; i < 16; ++i) { 1109 if ((cpu->cfg.satp_mode.init & (1 << i)) && 1110 (cpu->cfg.satp_mode.supported & (1 << i))) { 1111 for (int j = i - 1; j >= 0; --j) { 1112 if (cpu->cfg.satp_mode.supported & (1 << j)) { 1113 cpu->cfg.satp_mode.map |= (1 << j); 1114 break; 1115 } 1116 } 1117 break; 1118 } 1119 } 1120 } 1121 } 1122 1123 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 1124 1125 /* Make sure the user asked for a supported configuration (HW and qemu) */ 1126 if (satp_mode_map_max > satp_mode_supported_max) { 1127 error_setg(errp, "satp_mode %s is higher than hw max capability %s", 1128 satp_mode_str(satp_mode_map_max, rv32), 1129 satp_mode_str(satp_mode_supported_max, rv32)); 1130 return; 1131 } 1132 1133 /* 1134 * Make sure the user did not ask for an invalid configuration as per 1135 * the specification. 1136 */ 1137 if (!rv32) { 1138 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1139 if (!(cpu->cfg.satp_mode.map & (1 << i)) && 1140 (cpu->cfg.satp_mode.init & (1 << i)) && 1141 (cpu->cfg.satp_mode.supported & (1 << i))) { 1142 error_setg(errp, "cannot disable %s satp mode if %s " 1143 "is enabled", satp_mode_str(i, false), 1144 satp_mode_str(satp_mode_map_max, false)); 1145 return; 1146 } 1147 } 1148 } 1149 1150 /* Finally expand the map so that all valid modes are set */ 1151 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1152 if (cpu->cfg.satp_mode.supported & (1 << i)) { 1153 cpu->cfg.satp_mode.map |= (1 << i); 1154 } 1155 } 1156 } 1157 #endif 1158 1159 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1160 { 1161 #ifndef CONFIG_USER_ONLY 1162 Error *local_err = NULL; 1163 1164 riscv_cpu_satp_mode_finalize(cpu, &local_err); 1165 if (local_err != NULL) { 1166 error_propagate(errp, local_err); 1167 return; 1168 } 1169 #endif 1170 } 1171 1172 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 1173 { 1174 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 1175 error_setg(errp, "H extension requires priv spec 1.12.0"); 1176 return; 1177 } 1178 } 1179 1180 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 1181 { 1182 CPUState *cs = CPU(dev); 1183 RISCVCPU *cpu = RISCV_CPU(dev); 1184 CPURISCVState *env = &cpu->env; 1185 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 1186 CPUClass *cc = CPU_CLASS(mcc); 1187 int i, priv_version = -1; 1188 Error *local_err = NULL; 1189 1190 cpu_exec_realizefn(cs, &local_err); 1191 if (local_err != NULL) { 1192 error_propagate(errp, local_err); 1193 return; 1194 } 1195 1196 if (cpu->cfg.priv_spec) { 1197 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 1198 priv_version = PRIV_VERSION_1_12_0; 1199 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 1200 priv_version = PRIV_VERSION_1_11_0; 1201 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 1202 priv_version = PRIV_VERSION_1_10_0; 1203 } else { 1204 error_setg(errp, 1205 "Unsupported privilege spec version '%s'", 1206 cpu->cfg.priv_spec); 1207 return; 1208 } 1209 } 1210 1211 if (priv_version >= PRIV_VERSION_1_10_0) { 1212 set_priv_version(env, priv_version); 1213 } 1214 1215 riscv_cpu_validate_misa_priv(env, &local_err); 1216 if (local_err != NULL) { 1217 error_propagate(errp, local_err); 1218 return; 1219 } 1220 1221 /* Force disable extensions if priv spec version does not match */ 1222 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1223 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 1224 (env->priv_ver < isa_edata_arr[i].min_version)) { 1225 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 1226 #ifndef CONFIG_USER_ONLY 1227 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 1228 " because privilege spec version does not match", 1229 isa_edata_arr[i].name, env->mhartid); 1230 #else 1231 warn_report("disabling %s extension because " 1232 "privilege spec version does not match", 1233 isa_edata_arr[i].name); 1234 #endif 1235 } 1236 } 1237 1238 if (cpu->cfg.epmp && !cpu->cfg.pmp) { 1239 /* 1240 * Enhanced PMP should only be available 1241 * on harts with PMP support 1242 */ 1243 error_setg(errp, "Invalid configuration: EPMP requires PMP support"); 1244 return; 1245 } 1246 1247 1248 #ifndef CONFIG_USER_ONLY 1249 if (cpu->cfg.ext_sstc) { 1250 riscv_timer_init(cpu); 1251 } 1252 #endif /* CONFIG_USER_ONLY */ 1253 1254 /* Validate that MISA_MXL is set properly. */ 1255 switch (env->misa_mxl_max) { 1256 #ifdef TARGET_RISCV64 1257 case MXL_RV64: 1258 case MXL_RV128: 1259 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 1260 break; 1261 #endif 1262 case MXL_RV32: 1263 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 1264 break; 1265 default: 1266 g_assert_not_reached(); 1267 } 1268 assert(env->misa_mxl_max == env->misa_mxl); 1269 1270 riscv_cpu_validate_set_extensions(cpu, &local_err); 1271 if (local_err != NULL) { 1272 error_propagate(errp, local_err); 1273 return; 1274 } 1275 1276 #ifndef CONFIG_USER_ONLY 1277 if (cpu->cfg.pmu_num) { 1278 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 1279 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1280 riscv_pmu_timer_cb, cpu); 1281 } 1282 } 1283 #endif 1284 1285 riscv_cpu_finalize_features(cpu, &local_err); 1286 if (local_err != NULL) { 1287 error_propagate(errp, local_err); 1288 return; 1289 } 1290 1291 riscv_cpu_register_gdb_regs_for_features(cs); 1292 1293 qemu_init_vcpu(cs); 1294 cpu_reset(cs); 1295 1296 mcc->parent_realize(dev, errp); 1297 } 1298 1299 #ifndef CONFIG_USER_ONLY 1300 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, 1301 void *opaque, Error **errp) 1302 { 1303 RISCVSATPMap *satp_map = opaque; 1304 uint8_t satp = satp_mode_from_str(name); 1305 bool value; 1306 1307 value = satp_map->map & (1 << satp); 1308 1309 visit_type_bool(v, name, &value, errp); 1310 } 1311 1312 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, 1313 void *opaque, Error **errp) 1314 { 1315 RISCVSATPMap *satp_map = opaque; 1316 uint8_t satp = satp_mode_from_str(name); 1317 bool value; 1318 1319 if (!visit_type_bool(v, name, &value, errp)) { 1320 return; 1321 } 1322 1323 satp_map->map = deposit32(satp_map->map, satp, 1, value); 1324 satp_map->init |= 1 << satp; 1325 } 1326 1327 static void riscv_add_satp_mode_properties(Object *obj) 1328 { 1329 RISCVCPU *cpu = RISCV_CPU(obj); 1330 1331 if (cpu->env.misa_mxl == MXL_RV32) { 1332 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, 1333 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1334 } else { 1335 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, 1336 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1337 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, 1338 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1339 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, 1340 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1341 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, 1342 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1343 } 1344 } 1345 1346 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1347 { 1348 RISCVCPU *cpu = RISCV_CPU(opaque); 1349 CPURISCVState *env = &cpu->env; 1350 1351 if (irq < IRQ_LOCAL_MAX) { 1352 switch (irq) { 1353 case IRQ_U_SOFT: 1354 case IRQ_S_SOFT: 1355 case IRQ_VS_SOFT: 1356 case IRQ_M_SOFT: 1357 case IRQ_U_TIMER: 1358 case IRQ_S_TIMER: 1359 case IRQ_VS_TIMER: 1360 case IRQ_M_TIMER: 1361 case IRQ_U_EXT: 1362 case IRQ_VS_EXT: 1363 case IRQ_M_EXT: 1364 if (kvm_enabled()) { 1365 kvm_riscv_set_irq(cpu, irq, level); 1366 } else { 1367 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); 1368 } 1369 break; 1370 case IRQ_S_EXT: 1371 if (kvm_enabled()) { 1372 kvm_riscv_set_irq(cpu, irq, level); 1373 } else { 1374 env->external_seip = level; 1375 riscv_cpu_update_mip(env, 1 << irq, 1376 BOOL_TO_MASK(level | env->software_seip)); 1377 } 1378 break; 1379 default: 1380 g_assert_not_reached(); 1381 } 1382 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1383 /* Require H-extension for handling guest local interrupts */ 1384 if (!riscv_has_ext(env, RVH)) { 1385 g_assert_not_reached(); 1386 } 1387 1388 /* Compute bit position in HGEIP CSR */ 1389 irq = irq - IRQ_LOCAL_MAX + 1; 1390 if (env->geilen < irq) { 1391 g_assert_not_reached(); 1392 } 1393 1394 /* Update HGEIP CSR */ 1395 env->hgeip &= ~((target_ulong)1 << irq); 1396 if (level) { 1397 env->hgeip |= (target_ulong)1 << irq; 1398 } 1399 1400 /* Update mip.SGEIP bit */ 1401 riscv_cpu_update_mip(env, MIP_SGEIP, 1402 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1403 } else { 1404 g_assert_not_reached(); 1405 } 1406 } 1407 #endif /* CONFIG_USER_ONLY */ 1408 1409 static void riscv_cpu_init(Object *obj) 1410 { 1411 RISCVCPU *cpu = RISCV_CPU(obj); 1412 1413 cpu->cfg.ext_ifencei = true; 1414 cpu->cfg.ext_icsr = true; 1415 cpu->cfg.mmu = true; 1416 cpu->cfg.pmp = true; 1417 1418 cpu_set_cpustate_pointers(cpu); 1419 1420 #ifndef CONFIG_USER_ONLY 1421 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1422 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1423 #endif /* CONFIG_USER_ONLY */ 1424 } 1425 1426 typedef struct RISCVCPUMisaExtConfig { 1427 const char *name; 1428 const char *description; 1429 target_ulong misa_bit; 1430 bool enabled; 1431 } RISCVCPUMisaExtConfig; 1432 1433 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1434 void *opaque, Error **errp) 1435 { 1436 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1437 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1438 RISCVCPU *cpu = RISCV_CPU(obj); 1439 CPURISCVState *env = &cpu->env; 1440 bool value; 1441 1442 if (!visit_type_bool(v, name, &value, errp)) { 1443 return; 1444 } 1445 1446 if (value) { 1447 env->misa_ext |= misa_bit; 1448 env->misa_ext_mask |= misa_bit; 1449 } else { 1450 env->misa_ext &= ~misa_bit; 1451 env->misa_ext_mask &= ~misa_bit; 1452 } 1453 } 1454 1455 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1456 void *opaque, Error **errp) 1457 { 1458 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1459 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1460 RISCVCPU *cpu = RISCV_CPU(obj); 1461 CPURISCVState *env = &cpu->env; 1462 bool value; 1463 1464 value = env->misa_ext & misa_bit; 1465 1466 visit_type_bool(v, name, &value, errp); 1467 } 1468 1469 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1470 {.name = "a", .description = "Atomic instructions", 1471 .misa_bit = RVA, .enabled = true}, 1472 {.name = "c", .description = "Compressed instructions", 1473 .misa_bit = RVC, .enabled = true}, 1474 {.name = "d", .description = "Double-precision float point", 1475 .misa_bit = RVD, .enabled = true}, 1476 {.name = "f", .description = "Single-precision float point", 1477 .misa_bit = RVF, .enabled = true}, 1478 {.name = "i", .description = "Base integer instruction set", 1479 .misa_bit = RVI, .enabled = true}, 1480 {.name = "e", .description = "Base integer instruction set (embedded)", 1481 .misa_bit = RVE, .enabled = false}, 1482 {.name = "m", .description = "Integer multiplication and division", 1483 .misa_bit = RVM, .enabled = true}, 1484 {.name = "s", .description = "Supervisor-level instructions", 1485 .misa_bit = RVS, .enabled = true}, 1486 {.name = "u", .description = "User-level instructions", 1487 .misa_bit = RVU, .enabled = true}, 1488 {.name = "h", .description = "Hypervisor", 1489 .misa_bit = RVH, .enabled = true}, 1490 {.name = "x-j", .description = "Dynamic translated languages", 1491 .misa_bit = RVJ, .enabled = false}, 1492 {.name = "v", .description = "Vector operations", 1493 .misa_bit = RVV, .enabled = false}, 1494 {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)", 1495 .misa_bit = RVG, .enabled = false}, 1496 }; 1497 1498 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1499 { 1500 int i; 1501 1502 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1503 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1504 1505 object_property_add(cpu_obj, misa_cfg->name, "bool", 1506 cpu_get_misa_ext_cfg, 1507 cpu_set_misa_ext_cfg, 1508 NULL, (void *)misa_cfg); 1509 object_property_set_description(cpu_obj, misa_cfg->name, 1510 misa_cfg->description); 1511 object_property_set_bool(cpu_obj, misa_cfg->name, 1512 misa_cfg->enabled, NULL); 1513 } 1514 } 1515 1516 static Property riscv_cpu_extensions[] = { 1517 /* Defaults for standard extensions */ 1518 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1519 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1520 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1521 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1522 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1523 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1524 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1525 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1526 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1527 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1528 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), 1529 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1530 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1531 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1532 1533 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1534 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1535 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1536 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1537 1538 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), 1539 1540 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1541 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1542 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1543 1544 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1545 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1546 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1547 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1548 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1549 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1550 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1551 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1552 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1553 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1554 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1555 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1556 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1557 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1558 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1559 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1560 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1561 1562 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1563 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1564 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1565 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1566 1567 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), 1568 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), 1569 DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), 1570 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), 1571 1572 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1573 1574 DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false), 1575 DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false), 1576 DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false), 1577 DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false), 1578 DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), 1579 DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), 1580 DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), 1581 1582 /* Vendor-specific custom extensions */ 1583 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1584 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1585 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1586 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1587 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1588 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1589 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1590 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1591 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1592 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1593 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1594 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1595 1596 /* These are experimental so mark with 'x-' */ 1597 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), 1598 1599 /* ePMP 0.9.3 */ 1600 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1601 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1602 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1603 1604 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), 1605 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), 1606 1607 DEFINE_PROP_END_OF_LIST(), 1608 }; 1609 1610 /* 1611 * Add CPU properties with user-facing flags. 1612 * 1613 * This will overwrite existing env->misa_ext values with the 1614 * defaults set via riscv_cpu_add_misa_properties(). 1615 */ 1616 static void riscv_cpu_add_user_properties(Object *obj) 1617 { 1618 Property *prop; 1619 DeviceState *dev = DEVICE(obj); 1620 1621 riscv_cpu_add_misa_properties(obj); 1622 1623 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1624 qdev_property_add_static(dev, prop); 1625 } 1626 1627 #ifndef CONFIG_USER_ONLY 1628 riscv_add_satp_mode_properties(obj); 1629 #endif 1630 } 1631 1632 static Property riscv_cpu_properties[] = { 1633 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1634 1635 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1636 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1637 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1638 1639 #ifndef CONFIG_USER_ONLY 1640 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1641 #endif 1642 1643 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1644 1645 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1646 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1647 1648 /* 1649 * write_misa() is marked as experimental for now so mark 1650 * it with -x and default to 'false'. 1651 */ 1652 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1653 DEFINE_PROP_END_OF_LIST(), 1654 }; 1655 1656 static gchar *riscv_gdb_arch_name(CPUState *cs) 1657 { 1658 RISCVCPU *cpu = RISCV_CPU(cs); 1659 CPURISCVState *env = &cpu->env; 1660 1661 switch (riscv_cpu_mxl(env)) { 1662 case MXL_RV32: 1663 return g_strdup("riscv:rv32"); 1664 case MXL_RV64: 1665 case MXL_RV128: 1666 return g_strdup("riscv:rv64"); 1667 default: 1668 g_assert_not_reached(); 1669 } 1670 } 1671 1672 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1673 { 1674 RISCVCPU *cpu = RISCV_CPU(cs); 1675 1676 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1677 return cpu->dyn_csr_xml; 1678 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1679 return cpu->dyn_vreg_xml; 1680 } 1681 1682 return NULL; 1683 } 1684 1685 #ifndef CONFIG_USER_ONLY 1686 static int64_t riscv_get_arch_id(CPUState *cs) 1687 { 1688 RISCVCPU *cpu = RISCV_CPU(cs); 1689 1690 return cpu->env.mhartid; 1691 } 1692 1693 #include "hw/core/sysemu-cpu-ops.h" 1694 1695 static const struct SysemuCPUOps riscv_sysemu_ops = { 1696 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1697 .write_elf64_note = riscv_cpu_write_elf64_note, 1698 .write_elf32_note = riscv_cpu_write_elf32_note, 1699 .legacy_vmsd = &vmstate_riscv_cpu, 1700 }; 1701 #endif 1702 1703 #include "hw/core/tcg-cpu-ops.h" 1704 1705 static const struct TCGCPUOps riscv_tcg_ops = { 1706 .initialize = riscv_translate_init, 1707 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1708 .restore_state_to_opc = riscv_restore_state_to_opc, 1709 1710 #ifndef CONFIG_USER_ONLY 1711 .tlb_fill = riscv_cpu_tlb_fill, 1712 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1713 .do_interrupt = riscv_cpu_do_interrupt, 1714 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1715 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1716 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1717 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1718 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1719 #endif /* !CONFIG_USER_ONLY */ 1720 }; 1721 1722 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1723 { 1724 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1725 CPUClass *cc = CPU_CLASS(c); 1726 DeviceClass *dc = DEVICE_CLASS(c); 1727 ResettableClass *rc = RESETTABLE_CLASS(c); 1728 1729 device_class_set_parent_realize(dc, riscv_cpu_realize, 1730 &mcc->parent_realize); 1731 1732 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1733 &mcc->parent_phases); 1734 1735 cc->class_by_name = riscv_cpu_class_by_name; 1736 cc->has_work = riscv_cpu_has_work; 1737 cc->dump_state = riscv_cpu_dump_state; 1738 cc->set_pc = riscv_cpu_set_pc; 1739 cc->get_pc = riscv_cpu_get_pc; 1740 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1741 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1742 cc->gdb_num_core_regs = 33; 1743 cc->gdb_stop_before_watchpoint = true; 1744 cc->disas_set_info = riscv_cpu_disas_set_info; 1745 #ifndef CONFIG_USER_ONLY 1746 cc->sysemu_ops = &riscv_sysemu_ops; 1747 cc->get_arch_id = riscv_get_arch_id; 1748 #endif 1749 cc->gdb_arch_name = riscv_gdb_arch_name; 1750 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1751 cc->tcg_ops = &riscv_tcg_ops; 1752 1753 device_class_set_props(dc, riscv_cpu_properties); 1754 } 1755 1756 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, 1757 int max_str_len) 1758 { 1759 char *old = *isa_str; 1760 char *new = *isa_str; 1761 int i; 1762 1763 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1764 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1765 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1766 g_free(old); 1767 old = new; 1768 } 1769 } 1770 1771 *isa_str = new; 1772 } 1773 1774 char *riscv_isa_string(RISCVCPU *cpu) 1775 { 1776 int i; 1777 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1778 char *isa_str = g_new(char, maxlen); 1779 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1780 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1781 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1782 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1783 } 1784 } 1785 *p = '\0'; 1786 if (!cpu->cfg.short_isa_string) { 1787 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1788 } 1789 return isa_str; 1790 } 1791 1792 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1793 { 1794 ObjectClass *class_a = (ObjectClass *)a; 1795 ObjectClass *class_b = (ObjectClass *)b; 1796 const char *name_a, *name_b; 1797 1798 name_a = object_class_get_name(class_a); 1799 name_b = object_class_get_name(class_b); 1800 return strcmp(name_a, name_b); 1801 } 1802 1803 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1804 { 1805 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1806 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1807 1808 qemu_printf("%.*s\n", len, typename); 1809 } 1810 1811 void riscv_cpu_list(void) 1812 { 1813 GSList *list; 1814 1815 list = object_class_get_list(TYPE_RISCV_CPU, false); 1816 list = g_slist_sort(list, riscv_cpu_list_compare); 1817 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1818 g_slist_free(list); 1819 } 1820 1821 #define DEFINE_CPU(type_name, initfn) \ 1822 { \ 1823 .name = type_name, \ 1824 .parent = TYPE_RISCV_CPU, \ 1825 .instance_init = initfn \ 1826 } 1827 1828 #define DEFINE_DYNAMIC_CPU(type_name, initfn) \ 1829 { \ 1830 .name = type_name, \ 1831 .parent = TYPE_RISCV_DYNAMIC_CPU, \ 1832 .instance_init = initfn \ 1833 } 1834 1835 static const TypeInfo riscv_cpu_type_infos[] = { 1836 { 1837 .name = TYPE_RISCV_CPU, 1838 .parent = TYPE_CPU, 1839 .instance_size = sizeof(RISCVCPU), 1840 .instance_align = __alignof__(RISCVCPU), 1841 .instance_init = riscv_cpu_init, 1842 .abstract = true, 1843 .class_size = sizeof(RISCVCPUClass), 1844 .class_init = riscv_cpu_class_init, 1845 }, 1846 { 1847 .name = TYPE_RISCV_DYNAMIC_CPU, 1848 .parent = TYPE_RISCV_CPU, 1849 .abstract = true, 1850 }, 1851 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1852 #if defined(CONFIG_KVM) 1853 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1854 #endif 1855 #if defined(TARGET_RISCV32) 1856 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1857 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1858 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1859 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1860 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1861 #elif defined(TARGET_RISCV64) 1862 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1863 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1864 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1865 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1866 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1867 DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), 1868 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1869 #endif 1870 }; 1871 1872 DEFINE_TYPES(riscv_cpu_type_infos) 1873