1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "qemu/error-report.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "fpu/softfloat-helpers.h" 36 #include "sysemu/kvm.h" 37 #include "kvm_riscv.h" 38 #include "tcg/tcg.h" 39 40 /* RISC-V CPU definitions */ 41 42 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 43 (QEMU_VERSION_MINOR << 8) | \ 44 (QEMU_VERSION_MICRO)) 45 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 46 47 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 48 49 struct isa_ext_data { 50 const char *name; 51 bool multi_letter; 52 int min_version; 53 int ext_enable_offset; 54 }; 55 56 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ 57 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 58 59 /* 60 * Here are the ordering rules of extension naming defined by RISC-V 61 * specification : 62 * 1. All extensions should be separated from other multi-letter extensions 63 * by an underscore. 64 * 2. The first letter following the 'Z' conventionally indicates the most 65 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 66 * If multiple 'Z' extensions are named, they should be ordered first 67 * by category, then alphabetically within a category. 68 * 3. Standard supervisor-level extensions (starts with 'S') should be 69 * listed after standard unprivileged extensions. If multiple 70 * supervisor-level extensions are listed, they should be ordered 71 * alphabetically. 72 * 4. Non-standard extensions (starts with 'X') must be listed after all 73 * standard extensions. They must be separated from other multi-letter 74 * extensions by an underscore. 75 * 76 * Single letter extensions are checked in riscv_cpu_validate_misa_priv() 77 * instead. 78 */ 79 static const struct isa_ext_data isa_edata_arr[] = { 80 ISA_EXT_DATA_ENTRY(zicbom, true, PRIV_VERSION_1_12_0, ext_icbom), 81 ISA_EXT_DATA_ENTRY(zicboz, true, PRIV_VERSION_1_12_0, ext_icboz), 82 ISA_EXT_DATA_ENTRY(zicond, true, PRIV_VERSION_1_12_0, ext_zicond), 83 ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), 84 ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), 85 ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), 86 ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), 87 ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), 88 ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_11_0, ext_zfhmin), 89 ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), 90 ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), 91 ISA_EXT_DATA_ENTRY(zca, true, PRIV_VERSION_1_12_0, ext_zca), 92 ISA_EXT_DATA_ENTRY(zcb, true, PRIV_VERSION_1_12_0, ext_zcb), 93 ISA_EXT_DATA_ENTRY(zcf, true, PRIV_VERSION_1_12_0, ext_zcf), 94 ISA_EXT_DATA_ENTRY(zcd, true, PRIV_VERSION_1_12_0, ext_zcd), 95 ISA_EXT_DATA_ENTRY(zce, true, PRIV_VERSION_1_12_0, ext_zce), 96 ISA_EXT_DATA_ENTRY(zcmp, true, PRIV_VERSION_1_12_0, ext_zcmp), 97 ISA_EXT_DATA_ENTRY(zcmt, true, PRIV_VERSION_1_12_0, ext_zcmt), 98 ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), 99 ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), 100 ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), 101 ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), 102 ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), 103 ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), 104 ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), 105 ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), 106 ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), 107 ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), 108 ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), 109 ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), 110 ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), 111 ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), 112 ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), 113 ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), 114 ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), 115 ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_10_0, ext_zve32f), 116 ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_10_0, ext_zve64f), 117 ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_10_0, ext_zve64d), 118 ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh), 119 ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin), 120 ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), 121 ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), 122 ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), 123 ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), 124 ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), 125 ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), 126 ISA_EXT_DATA_ENTRY(svadu, true, PRIV_VERSION_1_12_0, ext_svadu), 127 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), 128 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), 129 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), 130 ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), 131 ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), 132 ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), 133 ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), 134 ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 135 ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 136 ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), 137 ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), 138 ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 139 ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), 140 ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), 141 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 142 }; 143 144 static bool isa_ext_is_enabled(RISCVCPU *cpu, 145 const struct isa_ext_data *edata) 146 { 147 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 148 149 return *ext_enabled; 150 } 151 152 static void isa_ext_update_enabled(RISCVCPU *cpu, 153 const struct isa_ext_data *edata, bool en) 154 { 155 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 156 157 *ext_enabled = en; 158 } 159 160 const char * const riscv_int_regnames[] = { 161 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 162 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 163 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 164 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 165 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 166 }; 167 168 const char * const riscv_int_regnamesh[] = { 169 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 170 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 171 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 172 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 173 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 174 "x30h/t5h", "x31h/t6h" 175 }; 176 177 const char * const riscv_fpr_regnames[] = { 178 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 179 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 180 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 181 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 182 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 183 "f30/ft10", "f31/ft11" 184 }; 185 186 static const char * const riscv_excp_names[] = { 187 "misaligned_fetch", 188 "fault_fetch", 189 "illegal_instruction", 190 "breakpoint", 191 "misaligned_load", 192 "fault_load", 193 "misaligned_store", 194 "fault_store", 195 "user_ecall", 196 "supervisor_ecall", 197 "hypervisor_ecall", 198 "machine_ecall", 199 "exec_page_fault", 200 "load_page_fault", 201 "reserved", 202 "store_page_fault", 203 "reserved", 204 "reserved", 205 "reserved", 206 "reserved", 207 "guest_exec_page_fault", 208 "guest_load_page_fault", 209 "reserved", 210 "guest_store_page_fault", 211 }; 212 213 static const char * const riscv_intr_names[] = { 214 "u_software", 215 "s_software", 216 "vs_software", 217 "m_software", 218 "u_timer", 219 "s_timer", 220 "vs_timer", 221 "m_timer", 222 "u_external", 223 "s_external", 224 "vs_external", 225 "m_external", 226 "reserved", 227 "reserved", 228 "reserved", 229 "reserved" 230 }; 231 232 static void register_cpu_props(Object *obj); 233 234 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 235 { 236 if (async) { 237 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 238 riscv_intr_names[cause] : "(unknown)"; 239 } else { 240 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 241 riscv_excp_names[cause] : "(unknown)"; 242 } 243 } 244 245 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 246 { 247 env->misa_mxl_max = env->misa_mxl = mxl; 248 env->misa_ext_mask = env->misa_ext = ext; 249 } 250 251 static void set_priv_version(CPURISCVState *env, int priv_ver) 252 { 253 env->priv_ver = priv_ver; 254 } 255 256 static void set_vext_version(CPURISCVState *env, int vext_ver) 257 { 258 env->vext_ver = vext_ver; 259 } 260 261 #ifndef CONFIG_USER_ONLY 262 static uint8_t satp_mode_from_str(const char *satp_mode_str) 263 { 264 if (!strncmp(satp_mode_str, "mbare", 5)) { 265 return VM_1_10_MBARE; 266 } 267 268 if (!strncmp(satp_mode_str, "sv32", 4)) { 269 return VM_1_10_SV32; 270 } 271 272 if (!strncmp(satp_mode_str, "sv39", 4)) { 273 return VM_1_10_SV39; 274 } 275 276 if (!strncmp(satp_mode_str, "sv48", 4)) { 277 return VM_1_10_SV48; 278 } 279 280 if (!strncmp(satp_mode_str, "sv57", 4)) { 281 return VM_1_10_SV57; 282 } 283 284 if (!strncmp(satp_mode_str, "sv64", 4)) { 285 return VM_1_10_SV64; 286 } 287 288 g_assert_not_reached(); 289 } 290 291 uint8_t satp_mode_max_from_map(uint32_t map) 292 { 293 /* map here has at least one bit set, so no problem with clz */ 294 return 31 - __builtin_clz(map); 295 } 296 297 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) 298 { 299 if (is_32_bit) { 300 switch (satp_mode) { 301 case VM_1_10_SV32: 302 return "sv32"; 303 case VM_1_10_MBARE: 304 return "none"; 305 } 306 } else { 307 switch (satp_mode) { 308 case VM_1_10_SV64: 309 return "sv64"; 310 case VM_1_10_SV57: 311 return "sv57"; 312 case VM_1_10_SV48: 313 return "sv48"; 314 case VM_1_10_SV39: 315 return "sv39"; 316 case VM_1_10_MBARE: 317 return "none"; 318 } 319 } 320 321 g_assert_not_reached(); 322 } 323 324 static void set_satp_mode_max_supported(RISCVCPU *cpu, 325 uint8_t satp_mode) 326 { 327 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 328 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; 329 330 for (int i = 0; i <= satp_mode; ++i) { 331 if (valid_vm[i]) { 332 cpu->cfg.satp_mode.supported |= (1 << i); 333 } 334 } 335 } 336 337 /* Set the satp mode to the max supported */ 338 static void set_satp_mode_default_map(RISCVCPU *cpu) 339 { 340 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; 341 } 342 #endif 343 344 static void riscv_any_cpu_init(Object *obj) 345 { 346 CPURISCVState *env = &RISCV_CPU(obj)->env; 347 #if defined(TARGET_RISCV32) 348 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 349 #elif defined(TARGET_RISCV64) 350 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 351 #endif 352 353 #ifndef CONFIG_USER_ONLY 354 set_satp_mode_max_supported(RISCV_CPU(obj), 355 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? 356 VM_1_10_SV32 : VM_1_10_SV57); 357 #endif 358 359 set_priv_version(env, PRIV_VERSION_1_12_0); 360 register_cpu_props(obj); 361 } 362 363 #if defined(TARGET_RISCV64) 364 static void rv64_base_cpu_init(Object *obj) 365 { 366 CPURISCVState *env = &RISCV_CPU(obj)->env; 367 /* We set this in the realise function */ 368 set_misa(env, MXL_RV64, 0); 369 register_cpu_props(obj); 370 /* Set latest version of privileged specification */ 371 set_priv_version(env, PRIV_VERSION_1_12_0); 372 #ifndef CONFIG_USER_ONLY 373 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 374 #endif 375 } 376 377 static void rv64_sifive_u_cpu_init(Object *obj) 378 { 379 CPURISCVState *env = &RISCV_CPU(obj)->env; 380 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 381 register_cpu_props(obj); 382 set_priv_version(env, PRIV_VERSION_1_10_0); 383 #ifndef CONFIG_USER_ONLY 384 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); 385 #endif 386 } 387 388 static void rv64_sifive_e_cpu_init(Object *obj) 389 { 390 CPURISCVState *env = &RISCV_CPU(obj)->env; 391 RISCVCPU *cpu = RISCV_CPU(obj); 392 393 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 394 register_cpu_props(obj); 395 set_priv_version(env, PRIV_VERSION_1_10_0); 396 cpu->cfg.mmu = false; 397 #ifndef CONFIG_USER_ONLY 398 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 399 #endif 400 } 401 402 static void rv64_thead_c906_cpu_init(Object *obj) 403 { 404 CPURISCVState *env = &RISCV_CPU(obj)->env; 405 RISCVCPU *cpu = RISCV_CPU(obj); 406 407 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 408 set_priv_version(env, PRIV_VERSION_1_11_0); 409 410 cpu->cfg.ext_g = true; 411 cpu->cfg.ext_c = true; 412 cpu->cfg.ext_u = true; 413 cpu->cfg.ext_s = true; 414 cpu->cfg.ext_icsr = true; 415 cpu->cfg.ext_zfh = true; 416 cpu->cfg.mmu = true; 417 cpu->cfg.ext_xtheadba = true; 418 cpu->cfg.ext_xtheadbb = true; 419 cpu->cfg.ext_xtheadbs = true; 420 cpu->cfg.ext_xtheadcmo = true; 421 cpu->cfg.ext_xtheadcondmov = true; 422 cpu->cfg.ext_xtheadfmemidx = true; 423 cpu->cfg.ext_xtheadmac = true; 424 cpu->cfg.ext_xtheadmemidx = true; 425 cpu->cfg.ext_xtheadmempair = true; 426 cpu->cfg.ext_xtheadsync = true; 427 428 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 429 #ifndef CONFIG_USER_ONLY 430 set_satp_mode_max_supported(cpu, VM_1_10_SV39); 431 #endif 432 } 433 434 static void rv128_base_cpu_init(Object *obj) 435 { 436 if (qemu_tcg_mttcg_enabled()) { 437 /* Missing 128-bit aligned atomics */ 438 error_report("128-bit RISC-V currently does not work with Multi " 439 "Threaded TCG. Please use: -accel tcg,thread=single"); 440 exit(EXIT_FAILURE); 441 } 442 CPURISCVState *env = &RISCV_CPU(obj)->env; 443 /* We set this in the realise function */ 444 set_misa(env, MXL_RV128, 0); 445 register_cpu_props(obj); 446 /* Set latest version of privileged specification */ 447 set_priv_version(env, PRIV_VERSION_1_12_0); 448 #ifndef CONFIG_USER_ONLY 449 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 450 #endif 451 } 452 #else 453 static void rv32_base_cpu_init(Object *obj) 454 { 455 CPURISCVState *env = &RISCV_CPU(obj)->env; 456 /* We set this in the realise function */ 457 set_misa(env, MXL_RV32, 0); 458 register_cpu_props(obj); 459 /* Set latest version of privileged specification */ 460 set_priv_version(env, PRIV_VERSION_1_12_0); 461 #ifndef CONFIG_USER_ONLY 462 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 463 #endif 464 } 465 466 static void rv32_sifive_u_cpu_init(Object *obj) 467 { 468 CPURISCVState *env = &RISCV_CPU(obj)->env; 469 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 470 register_cpu_props(obj); 471 set_priv_version(env, PRIV_VERSION_1_10_0); 472 #ifndef CONFIG_USER_ONLY 473 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 474 #endif 475 } 476 477 static void rv32_sifive_e_cpu_init(Object *obj) 478 { 479 CPURISCVState *env = &RISCV_CPU(obj)->env; 480 RISCVCPU *cpu = RISCV_CPU(obj); 481 482 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 483 register_cpu_props(obj); 484 set_priv_version(env, PRIV_VERSION_1_10_0); 485 cpu->cfg.mmu = false; 486 #ifndef CONFIG_USER_ONLY 487 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 488 #endif 489 } 490 491 static void rv32_ibex_cpu_init(Object *obj) 492 { 493 CPURISCVState *env = &RISCV_CPU(obj)->env; 494 RISCVCPU *cpu = RISCV_CPU(obj); 495 496 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 497 register_cpu_props(obj); 498 set_priv_version(env, PRIV_VERSION_1_11_0); 499 cpu->cfg.mmu = false; 500 #ifndef CONFIG_USER_ONLY 501 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 502 #endif 503 cpu->cfg.epmp = true; 504 } 505 506 static void rv32_imafcu_nommu_cpu_init(Object *obj) 507 { 508 CPURISCVState *env = &RISCV_CPU(obj)->env; 509 RISCVCPU *cpu = RISCV_CPU(obj); 510 511 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 512 register_cpu_props(obj); 513 set_priv_version(env, PRIV_VERSION_1_10_0); 514 cpu->cfg.mmu = false; 515 #ifndef CONFIG_USER_ONLY 516 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 517 #endif 518 } 519 #endif 520 521 #if defined(CONFIG_KVM) 522 static void riscv_host_cpu_init(Object *obj) 523 { 524 CPURISCVState *env = &RISCV_CPU(obj)->env; 525 #if defined(TARGET_RISCV32) 526 set_misa(env, MXL_RV32, 0); 527 #elif defined(TARGET_RISCV64) 528 set_misa(env, MXL_RV64, 0); 529 #endif 530 register_cpu_props(obj); 531 } 532 #endif 533 534 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 535 { 536 ObjectClass *oc; 537 char *typename; 538 char **cpuname; 539 540 cpuname = g_strsplit(cpu_model, ",", 1); 541 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 542 oc = object_class_by_name(typename); 543 g_strfreev(cpuname); 544 g_free(typename); 545 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 546 object_class_is_abstract(oc)) { 547 return NULL; 548 } 549 return oc; 550 } 551 552 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 553 { 554 RISCVCPU *cpu = RISCV_CPU(cs); 555 CPURISCVState *env = &cpu->env; 556 int i; 557 558 #if !defined(CONFIG_USER_ONLY) 559 if (riscv_has_ext(env, RVH)) { 560 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); 561 } 562 #endif 563 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 564 #ifndef CONFIG_USER_ONLY 565 { 566 static const int dump_csrs[] = { 567 CSR_MHARTID, 568 CSR_MSTATUS, 569 CSR_MSTATUSH, 570 /* 571 * CSR_SSTATUS is intentionally omitted here as its value 572 * can be figured out by looking at CSR_MSTATUS 573 */ 574 CSR_HSTATUS, 575 CSR_VSSTATUS, 576 CSR_MIP, 577 CSR_MIE, 578 CSR_MIDELEG, 579 CSR_HIDELEG, 580 CSR_MEDELEG, 581 CSR_HEDELEG, 582 CSR_MTVEC, 583 CSR_STVEC, 584 CSR_VSTVEC, 585 CSR_MEPC, 586 CSR_SEPC, 587 CSR_VSEPC, 588 CSR_MCAUSE, 589 CSR_SCAUSE, 590 CSR_VSCAUSE, 591 CSR_MTVAL, 592 CSR_STVAL, 593 CSR_HTVAL, 594 CSR_MTVAL2, 595 CSR_MSCRATCH, 596 CSR_SSCRATCH, 597 CSR_SATP, 598 CSR_MMTE, 599 CSR_UPMBASE, 600 CSR_UPMMASK, 601 CSR_SPMBASE, 602 CSR_SPMMASK, 603 CSR_MPMBASE, 604 CSR_MPMMASK, 605 }; 606 607 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 608 int csrno = dump_csrs[i]; 609 target_ulong val = 0; 610 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 611 612 /* 613 * Rely on the smode, hmode, etc, predicates within csr.c 614 * to do the filtering of the registers that are present. 615 */ 616 if (res == RISCV_EXCP_NONE) { 617 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 618 csr_ops[csrno].name, val); 619 } 620 } 621 } 622 #endif 623 624 for (i = 0; i < 32; i++) { 625 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 626 riscv_int_regnames[i], env->gpr[i]); 627 if ((i & 3) == 3) { 628 qemu_fprintf(f, "\n"); 629 } 630 } 631 if (flags & CPU_DUMP_FPU) { 632 for (i = 0; i < 32; i++) { 633 qemu_fprintf(f, " %-8s %016" PRIx64, 634 riscv_fpr_regnames[i], env->fpr[i]); 635 if ((i & 3) == 3) { 636 qemu_fprintf(f, "\n"); 637 } 638 } 639 } 640 } 641 642 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 643 { 644 RISCVCPU *cpu = RISCV_CPU(cs); 645 CPURISCVState *env = &cpu->env; 646 647 if (env->xl == MXL_RV32) { 648 env->pc = (int32_t)value; 649 } else { 650 env->pc = value; 651 } 652 } 653 654 static vaddr riscv_cpu_get_pc(CPUState *cs) 655 { 656 RISCVCPU *cpu = RISCV_CPU(cs); 657 CPURISCVState *env = &cpu->env; 658 659 /* Match cpu_get_tb_cpu_state. */ 660 if (env->xl == MXL_RV32) { 661 return env->pc & UINT32_MAX; 662 } 663 return env->pc; 664 } 665 666 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 667 const TranslationBlock *tb) 668 { 669 RISCVCPU *cpu = RISCV_CPU(cs); 670 CPURISCVState *env = &cpu->env; 671 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 672 673 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 674 675 if (xl == MXL_RV32) { 676 env->pc = (int32_t) tb->pc; 677 } else { 678 env->pc = tb->pc; 679 } 680 } 681 682 static bool riscv_cpu_has_work(CPUState *cs) 683 { 684 #ifndef CONFIG_USER_ONLY 685 RISCVCPU *cpu = RISCV_CPU(cs); 686 CPURISCVState *env = &cpu->env; 687 /* 688 * Definition of the WFI instruction requires it to ignore the privilege 689 * mode and delegation registers, but respect individual enables 690 */ 691 return riscv_cpu_all_pending(env) != 0; 692 #else 693 return true; 694 #endif 695 } 696 697 static void riscv_restore_state_to_opc(CPUState *cs, 698 const TranslationBlock *tb, 699 const uint64_t *data) 700 { 701 RISCVCPU *cpu = RISCV_CPU(cs); 702 CPURISCVState *env = &cpu->env; 703 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 704 705 if (xl == MXL_RV32) { 706 env->pc = (int32_t)data[0]; 707 } else { 708 env->pc = data[0]; 709 } 710 env->bins = data[1]; 711 } 712 713 static void riscv_cpu_reset_hold(Object *obj) 714 { 715 #ifndef CONFIG_USER_ONLY 716 uint8_t iprio; 717 int i, irq, rdzero; 718 #endif 719 CPUState *cs = CPU(obj); 720 RISCVCPU *cpu = RISCV_CPU(cs); 721 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 722 CPURISCVState *env = &cpu->env; 723 724 if (mcc->parent_phases.hold) { 725 mcc->parent_phases.hold(obj); 726 } 727 #ifndef CONFIG_USER_ONLY 728 env->misa_mxl = env->misa_mxl_max; 729 env->priv = PRV_M; 730 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 731 if (env->misa_mxl > MXL_RV32) { 732 /* 733 * The reset status of SXL/UXL is undefined, but mstatus is WARL 734 * and we must ensure that the value after init is valid for read. 735 */ 736 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 737 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 738 if (riscv_has_ext(env, RVH)) { 739 env->vsstatus = set_field(env->vsstatus, 740 MSTATUS64_SXL, env->misa_mxl); 741 env->vsstatus = set_field(env->vsstatus, 742 MSTATUS64_UXL, env->misa_mxl); 743 env->mstatus_hs = set_field(env->mstatus_hs, 744 MSTATUS64_SXL, env->misa_mxl); 745 env->mstatus_hs = set_field(env->mstatus_hs, 746 MSTATUS64_UXL, env->misa_mxl); 747 } 748 } 749 env->mcause = 0; 750 env->miclaim = MIP_SGEIP; 751 env->pc = env->resetvec; 752 env->bins = 0; 753 env->two_stage_lookup = false; 754 755 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | 756 (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); 757 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | 758 (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); 759 760 /* Initialized default priorities of local interrupts. */ 761 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 762 iprio = riscv_cpu_default_priority(i); 763 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 764 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 765 env->hviprio[i] = 0; 766 } 767 i = 0; 768 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 769 if (!rdzero) { 770 env->hviprio[irq] = env->miprio[irq]; 771 } 772 i++; 773 } 774 /* mmte is supposed to have pm.current hardwired to 1 */ 775 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 776 #endif 777 env->xl = riscv_cpu_mxl(env); 778 riscv_cpu_update_mask(env); 779 cs->exception_index = RISCV_EXCP_NONE; 780 env->load_res = -1; 781 set_default_nan_mode(1, &env->fp_status); 782 783 #ifndef CONFIG_USER_ONLY 784 if (cpu->cfg.debug) { 785 riscv_trigger_init(env); 786 } 787 788 if (kvm_enabled()) { 789 kvm_riscv_reset_vcpu(cpu); 790 } 791 #endif 792 } 793 794 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 795 { 796 RISCVCPU *cpu = RISCV_CPU(s); 797 798 switch (riscv_cpu_mxl(&cpu->env)) { 799 case MXL_RV32: 800 info->print_insn = print_insn_riscv32; 801 break; 802 case MXL_RV64: 803 info->print_insn = print_insn_riscv64; 804 break; 805 case MXL_RV128: 806 info->print_insn = print_insn_riscv128; 807 break; 808 default: 809 g_assert_not_reached(); 810 } 811 } 812 813 /* 814 * Check consistency between chosen extensions while setting 815 * cpu->cfg accordingly. 816 */ 817 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 818 { 819 CPURISCVState *env = &cpu->env; 820 821 /* Do some ISA extension error checking */ 822 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 823 cpu->cfg.ext_a && cpu->cfg.ext_f && 824 cpu->cfg.ext_d && 825 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 826 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 827 cpu->cfg.ext_i = true; 828 cpu->cfg.ext_m = true; 829 cpu->cfg.ext_a = true; 830 cpu->cfg.ext_f = true; 831 cpu->cfg.ext_d = true; 832 cpu->cfg.ext_icsr = true; 833 cpu->cfg.ext_ifencei = true; 834 835 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; 836 env->misa_ext_mask = env->misa_ext; 837 } 838 839 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 840 error_setg(errp, 841 "I and E extensions are incompatible"); 842 return; 843 } 844 845 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 846 error_setg(errp, 847 "Either I or E extension must be set"); 848 return; 849 } 850 851 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 852 error_setg(errp, 853 "Setting S extension without U extension is illegal"); 854 return; 855 } 856 857 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { 858 error_setg(errp, 859 "H depends on an I base integer ISA with 32 x registers"); 860 return; 861 } 862 863 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 864 error_setg(errp, "H extension implicitly requires S-mode"); 865 return; 866 } 867 868 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 869 error_setg(errp, "F extension requires Zicsr"); 870 return; 871 } 872 873 if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { 874 error_setg(errp, "Zawrs extension requires A extension"); 875 return; 876 } 877 878 if (cpu->cfg.ext_zfh) { 879 cpu->cfg.ext_zfhmin = true; 880 } 881 882 if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { 883 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 884 return; 885 } 886 887 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 888 error_setg(errp, "D extension requires F extension"); 889 return; 890 } 891 892 /* The V vector extension depends on the Zve64d extension */ 893 if (cpu->cfg.ext_v) { 894 cpu->cfg.ext_zve64d = true; 895 } 896 897 /* The Zve64d extension depends on the Zve64f extension */ 898 if (cpu->cfg.ext_zve64d) { 899 cpu->cfg.ext_zve64f = true; 900 } 901 902 /* The Zve64f extension depends on the Zve32f extension */ 903 if (cpu->cfg.ext_zve64f) { 904 cpu->cfg.ext_zve32f = true; 905 } 906 907 if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { 908 error_setg(errp, "Zve64d/V extensions require D extension"); 909 return; 910 } 911 912 if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { 913 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 914 return; 915 } 916 917 if (cpu->cfg.ext_zvfh) { 918 cpu->cfg.ext_zvfhmin = true; 919 } 920 921 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 922 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 923 return; 924 } 925 926 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 927 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 928 return; 929 } 930 931 /* Set the ISA extensions, checks should have happened above */ 932 if (cpu->cfg.ext_zhinx) { 933 cpu->cfg.ext_zhinxmin = true; 934 } 935 936 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { 937 cpu->cfg.ext_zfinx = true; 938 } 939 940 if (cpu->cfg.ext_zfinx) { 941 if (!cpu->cfg.ext_icsr) { 942 error_setg(errp, "Zfinx extension requires Zicsr"); 943 return; 944 } 945 if (cpu->cfg.ext_f) { 946 error_setg(errp, 947 "Zfinx cannot be supported together with F extension"); 948 return; 949 } 950 } 951 952 if (cpu->cfg.ext_zce) { 953 cpu->cfg.ext_zca = true; 954 cpu->cfg.ext_zcb = true; 955 cpu->cfg.ext_zcmp = true; 956 cpu->cfg.ext_zcmt = true; 957 if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { 958 cpu->cfg.ext_zcf = true; 959 } 960 } 961 962 if (cpu->cfg.ext_c) { 963 cpu->cfg.ext_zca = true; 964 if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { 965 cpu->cfg.ext_zcf = true; 966 } 967 if (cpu->cfg.ext_d) { 968 cpu->cfg.ext_zcd = true; 969 } 970 } 971 972 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 973 error_setg(errp, "Zcf extension is only relevant to RV32"); 974 return; 975 } 976 977 if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { 978 error_setg(errp, "Zcf extension requires F extension"); 979 return; 980 } 981 982 if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { 983 error_setg(errp, "Zcd extension requires D extension"); 984 return; 985 } 986 987 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 988 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 989 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 990 "extension"); 991 return; 992 } 993 994 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 995 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 996 "Zcd extension"); 997 return; 998 } 999 1000 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { 1001 error_setg(errp, "Zcmt extension requires Zicsr extension"); 1002 return; 1003 } 1004 1005 if (cpu->cfg.ext_zk) { 1006 cpu->cfg.ext_zkn = true; 1007 cpu->cfg.ext_zkr = true; 1008 cpu->cfg.ext_zkt = true; 1009 } 1010 1011 if (cpu->cfg.ext_zkn) { 1012 cpu->cfg.ext_zbkb = true; 1013 cpu->cfg.ext_zbkc = true; 1014 cpu->cfg.ext_zbkx = true; 1015 cpu->cfg.ext_zkne = true; 1016 cpu->cfg.ext_zknd = true; 1017 cpu->cfg.ext_zknh = true; 1018 } 1019 1020 if (cpu->cfg.ext_zks) { 1021 cpu->cfg.ext_zbkb = true; 1022 cpu->cfg.ext_zbkc = true; 1023 cpu->cfg.ext_zbkx = true; 1024 cpu->cfg.ext_zksed = true; 1025 cpu->cfg.ext_zksh = true; 1026 } 1027 1028 if (cpu->cfg.ext_v) { 1029 int vext_version = VEXT_VERSION_1_00_0; 1030 if (!is_power_of_2(cpu->cfg.vlen)) { 1031 error_setg(errp, 1032 "Vector extension VLEN must be power of 2"); 1033 return; 1034 } 1035 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 1036 error_setg(errp, 1037 "Vector extension implementation only supports VLEN " 1038 "in the range [128, %d]", RV_VLEN_MAX); 1039 return; 1040 } 1041 if (!is_power_of_2(cpu->cfg.elen)) { 1042 error_setg(errp, 1043 "Vector extension ELEN must be power of 2"); 1044 return; 1045 } 1046 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 1047 error_setg(errp, 1048 "Vector extension implementation only supports ELEN " 1049 "in the range [8, 64]"); 1050 return; 1051 } 1052 if (cpu->cfg.vext_spec) { 1053 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 1054 vext_version = VEXT_VERSION_1_00_0; 1055 } else { 1056 error_setg(errp, 1057 "Unsupported vector spec version '%s'", 1058 cpu->cfg.vext_spec); 1059 return; 1060 } 1061 } else { 1062 qemu_log("vector version is not specified, " 1063 "use the default value v1.0\n"); 1064 } 1065 set_vext_version(env, vext_version); 1066 } 1067 } 1068 1069 #ifndef CONFIG_USER_ONLY 1070 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) 1071 { 1072 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 1073 uint8_t satp_mode_map_max; 1074 uint8_t satp_mode_supported_max = 1075 satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 1076 1077 if (cpu->cfg.satp_mode.map == 0) { 1078 if (cpu->cfg.satp_mode.init == 0) { 1079 /* If unset by the user, we fallback to the default satp mode. */ 1080 set_satp_mode_default_map(cpu); 1081 } else { 1082 /* 1083 * Find the lowest level that was disabled and then enable the 1084 * first valid level below which can be found in 1085 * valid_vm_1_10_32/64. 1086 */ 1087 for (int i = 1; i < 16; ++i) { 1088 if ((cpu->cfg.satp_mode.init & (1 << i)) && 1089 (cpu->cfg.satp_mode.supported & (1 << i))) { 1090 for (int j = i - 1; j >= 0; --j) { 1091 if (cpu->cfg.satp_mode.supported & (1 << j)) { 1092 cpu->cfg.satp_mode.map |= (1 << j); 1093 break; 1094 } 1095 } 1096 break; 1097 } 1098 } 1099 } 1100 } 1101 1102 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 1103 1104 /* Make sure the user asked for a supported configuration (HW and qemu) */ 1105 if (satp_mode_map_max > satp_mode_supported_max) { 1106 error_setg(errp, "satp_mode %s is higher than hw max capability %s", 1107 satp_mode_str(satp_mode_map_max, rv32), 1108 satp_mode_str(satp_mode_supported_max, rv32)); 1109 return; 1110 } 1111 1112 /* 1113 * Make sure the user did not ask for an invalid configuration as per 1114 * the specification. 1115 */ 1116 if (!rv32) { 1117 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1118 if (!(cpu->cfg.satp_mode.map & (1 << i)) && 1119 (cpu->cfg.satp_mode.init & (1 << i)) && 1120 (cpu->cfg.satp_mode.supported & (1 << i))) { 1121 error_setg(errp, "cannot disable %s satp mode if %s " 1122 "is enabled", satp_mode_str(i, false), 1123 satp_mode_str(satp_mode_map_max, false)); 1124 return; 1125 } 1126 } 1127 } 1128 1129 /* Finally expand the map so that all valid modes are set */ 1130 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1131 if (cpu->cfg.satp_mode.supported & (1 << i)) { 1132 cpu->cfg.satp_mode.map |= (1 << i); 1133 } 1134 } 1135 } 1136 #endif 1137 1138 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1139 { 1140 #ifndef CONFIG_USER_ONLY 1141 Error *local_err = NULL; 1142 1143 riscv_cpu_satp_mode_finalize(cpu, &local_err); 1144 if (local_err != NULL) { 1145 error_propagate(errp, local_err); 1146 return; 1147 } 1148 #endif 1149 } 1150 1151 static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) 1152 { 1153 uint32_t ext = 0; 1154 1155 if (riscv_cpu_cfg(env)->ext_i) { 1156 ext |= RVI; 1157 } 1158 if (riscv_cpu_cfg(env)->ext_e) { 1159 ext |= RVE; 1160 } 1161 if (riscv_cpu_cfg(env)->ext_m) { 1162 ext |= RVM; 1163 } 1164 if (riscv_cpu_cfg(env)->ext_a) { 1165 ext |= RVA; 1166 } 1167 if (riscv_cpu_cfg(env)->ext_f) { 1168 ext |= RVF; 1169 } 1170 if (riscv_cpu_cfg(env)->ext_d) { 1171 ext |= RVD; 1172 } 1173 if (riscv_cpu_cfg(env)->ext_c) { 1174 ext |= RVC; 1175 } 1176 if (riscv_cpu_cfg(env)->ext_s) { 1177 ext |= RVS; 1178 } 1179 if (riscv_cpu_cfg(env)->ext_u) { 1180 ext |= RVU; 1181 } 1182 if (riscv_cpu_cfg(env)->ext_h) { 1183 ext |= RVH; 1184 } 1185 if (riscv_cpu_cfg(env)->ext_v) { 1186 ext |= RVV; 1187 } 1188 if (riscv_cpu_cfg(env)->ext_j) { 1189 ext |= RVJ; 1190 } 1191 1192 env->misa_ext = env->misa_ext_mask = ext; 1193 } 1194 1195 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 1196 { 1197 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 1198 error_setg(errp, "H extension requires priv spec 1.12.0"); 1199 return; 1200 } 1201 } 1202 1203 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 1204 { 1205 CPUState *cs = CPU(dev); 1206 RISCVCPU *cpu = RISCV_CPU(dev); 1207 CPURISCVState *env = &cpu->env; 1208 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 1209 CPUClass *cc = CPU_CLASS(mcc); 1210 int i, priv_version = -1; 1211 Error *local_err = NULL; 1212 1213 cpu_exec_realizefn(cs, &local_err); 1214 if (local_err != NULL) { 1215 error_propagate(errp, local_err); 1216 return; 1217 } 1218 1219 if (cpu->cfg.priv_spec) { 1220 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 1221 priv_version = PRIV_VERSION_1_12_0; 1222 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 1223 priv_version = PRIV_VERSION_1_11_0; 1224 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 1225 priv_version = PRIV_VERSION_1_10_0; 1226 } else { 1227 error_setg(errp, 1228 "Unsupported privilege spec version '%s'", 1229 cpu->cfg.priv_spec); 1230 return; 1231 } 1232 } 1233 1234 if (priv_version >= PRIV_VERSION_1_10_0) { 1235 set_priv_version(env, priv_version); 1236 } 1237 1238 /* 1239 * We can't be sure of whether we set defaults during cpu_init() 1240 * or whether the user enabled/disabled some bits via cpu->cfg 1241 * flags. Sync env->misa_ext with cpu->cfg now to allow us to 1242 * use just env->misa_ext later. 1243 */ 1244 riscv_cpu_sync_misa_cfg(env); 1245 1246 riscv_cpu_validate_misa_priv(env, &local_err); 1247 if (local_err != NULL) { 1248 error_propagate(errp, local_err); 1249 return; 1250 } 1251 1252 /* Force disable extensions if priv spec version does not match */ 1253 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1254 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 1255 (env->priv_ver < isa_edata_arr[i].min_version)) { 1256 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 1257 #ifndef CONFIG_USER_ONLY 1258 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 1259 " because privilege spec version does not match", 1260 isa_edata_arr[i].name, env->mhartid); 1261 #else 1262 warn_report("disabling %s extension because " 1263 "privilege spec version does not match", 1264 isa_edata_arr[i].name); 1265 #endif 1266 } 1267 } 1268 1269 if (cpu->cfg.epmp && !cpu->cfg.pmp) { 1270 /* 1271 * Enhanced PMP should only be available 1272 * on harts with PMP support 1273 */ 1274 error_setg(errp, "Invalid configuration: EPMP requires PMP support"); 1275 return; 1276 } 1277 1278 1279 #ifndef CONFIG_USER_ONLY 1280 if (cpu->cfg.ext_sstc) { 1281 riscv_timer_init(cpu); 1282 } 1283 #endif /* CONFIG_USER_ONLY */ 1284 1285 /* Validate that MISA_MXL is set properly. */ 1286 switch (env->misa_mxl_max) { 1287 #ifdef TARGET_RISCV64 1288 case MXL_RV64: 1289 case MXL_RV128: 1290 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 1291 break; 1292 #endif 1293 case MXL_RV32: 1294 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 1295 break; 1296 default: 1297 g_assert_not_reached(); 1298 } 1299 assert(env->misa_mxl_max == env->misa_mxl); 1300 1301 riscv_cpu_validate_set_extensions(cpu, &local_err); 1302 if (local_err != NULL) { 1303 error_propagate(errp, local_err); 1304 return; 1305 } 1306 1307 #ifndef CONFIG_USER_ONLY 1308 if (cpu->cfg.pmu_num) { 1309 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 1310 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1311 riscv_pmu_timer_cb, cpu); 1312 } 1313 } 1314 #endif 1315 1316 riscv_cpu_finalize_features(cpu, &local_err); 1317 if (local_err != NULL) { 1318 error_propagate(errp, local_err); 1319 return; 1320 } 1321 1322 riscv_cpu_register_gdb_regs_for_features(cs); 1323 1324 qemu_init_vcpu(cs); 1325 cpu_reset(cs); 1326 1327 mcc->parent_realize(dev, errp); 1328 } 1329 1330 #ifndef CONFIG_USER_ONLY 1331 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, 1332 void *opaque, Error **errp) 1333 { 1334 RISCVSATPMap *satp_map = opaque; 1335 uint8_t satp = satp_mode_from_str(name); 1336 bool value; 1337 1338 value = satp_map->map & (1 << satp); 1339 1340 visit_type_bool(v, name, &value, errp); 1341 } 1342 1343 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, 1344 void *opaque, Error **errp) 1345 { 1346 RISCVSATPMap *satp_map = opaque; 1347 uint8_t satp = satp_mode_from_str(name); 1348 bool value; 1349 1350 if (!visit_type_bool(v, name, &value, errp)) { 1351 return; 1352 } 1353 1354 satp_map->map = deposit32(satp_map->map, satp, 1, value); 1355 satp_map->init |= 1 << satp; 1356 } 1357 1358 static void riscv_add_satp_mode_properties(Object *obj) 1359 { 1360 RISCVCPU *cpu = RISCV_CPU(obj); 1361 1362 if (cpu->env.misa_mxl == MXL_RV32) { 1363 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, 1364 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1365 } else { 1366 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, 1367 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1368 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, 1369 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1370 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, 1371 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1372 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, 1373 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1374 } 1375 } 1376 1377 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1378 { 1379 RISCVCPU *cpu = RISCV_CPU(opaque); 1380 CPURISCVState *env = &cpu->env; 1381 1382 if (irq < IRQ_LOCAL_MAX) { 1383 switch (irq) { 1384 case IRQ_U_SOFT: 1385 case IRQ_S_SOFT: 1386 case IRQ_VS_SOFT: 1387 case IRQ_M_SOFT: 1388 case IRQ_U_TIMER: 1389 case IRQ_S_TIMER: 1390 case IRQ_VS_TIMER: 1391 case IRQ_M_TIMER: 1392 case IRQ_U_EXT: 1393 case IRQ_VS_EXT: 1394 case IRQ_M_EXT: 1395 if (kvm_enabled()) { 1396 kvm_riscv_set_irq(cpu, irq, level); 1397 } else { 1398 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); 1399 } 1400 break; 1401 case IRQ_S_EXT: 1402 if (kvm_enabled()) { 1403 kvm_riscv_set_irq(cpu, irq, level); 1404 } else { 1405 env->external_seip = level; 1406 riscv_cpu_update_mip(env, 1 << irq, 1407 BOOL_TO_MASK(level | env->software_seip)); 1408 } 1409 break; 1410 default: 1411 g_assert_not_reached(); 1412 } 1413 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1414 /* Require H-extension for handling guest local interrupts */ 1415 if (!riscv_has_ext(env, RVH)) { 1416 g_assert_not_reached(); 1417 } 1418 1419 /* Compute bit position in HGEIP CSR */ 1420 irq = irq - IRQ_LOCAL_MAX + 1; 1421 if (env->geilen < irq) { 1422 g_assert_not_reached(); 1423 } 1424 1425 /* Update HGEIP CSR */ 1426 env->hgeip &= ~((target_ulong)1 << irq); 1427 if (level) { 1428 env->hgeip |= (target_ulong)1 << irq; 1429 } 1430 1431 /* Update mip.SGEIP bit */ 1432 riscv_cpu_update_mip(env, MIP_SGEIP, 1433 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1434 } else { 1435 g_assert_not_reached(); 1436 } 1437 } 1438 #endif /* CONFIG_USER_ONLY */ 1439 1440 static void riscv_cpu_init(Object *obj) 1441 { 1442 RISCVCPU *cpu = RISCV_CPU(obj); 1443 1444 cpu->cfg.ext_ifencei = true; 1445 cpu->cfg.ext_icsr = true; 1446 cpu->cfg.mmu = true; 1447 cpu->cfg.pmp = true; 1448 1449 cpu_set_cpustate_pointers(cpu); 1450 1451 #ifndef CONFIG_USER_ONLY 1452 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1453 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1454 #endif /* CONFIG_USER_ONLY */ 1455 } 1456 1457 static Property riscv_cpu_extensions[] = { 1458 /* Defaults for standard extensions */ 1459 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 1460 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 1461 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1462 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 1463 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 1464 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 1465 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 1466 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 1467 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 1468 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1469 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1470 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1471 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1472 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1473 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1474 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1475 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1476 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1477 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1478 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1479 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1480 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1481 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), 1482 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1483 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1484 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1485 1486 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1487 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1488 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1489 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1490 1491 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), 1492 1493 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1494 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1495 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1496 1497 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1498 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1499 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1500 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1501 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1502 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1503 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1504 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1505 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1506 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1507 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1508 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1509 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1510 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1511 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1512 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1513 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1514 1515 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1516 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1517 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1518 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1519 1520 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), 1521 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), 1522 DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), 1523 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), 1524 1525 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1526 1527 /* Vendor-specific custom extensions */ 1528 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1529 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1530 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1531 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1532 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1533 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1534 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1535 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1536 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1537 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1538 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1539 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1540 1541 /* These are experimental so mark with 'x-' */ 1542 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), 1543 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1544 1545 DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), 1546 DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), 1547 DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), 1548 DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), 1549 DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), 1550 DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), 1551 DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), 1552 1553 /* ePMP 0.9.3 */ 1554 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1555 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1556 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1557 1558 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), 1559 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), 1560 1561 DEFINE_PROP_END_OF_LIST(), 1562 }; 1563 1564 /* 1565 * Register CPU props based on env.misa_ext. If a non-zero 1566 * value was set, register only the required cpu->cfg.ext_* 1567 * properties and leave. env.misa_ext = 0 means that we want 1568 * all the default properties to be registered. 1569 */ 1570 static void register_cpu_props(Object *obj) 1571 { 1572 RISCVCPU *cpu = RISCV_CPU(obj); 1573 uint32_t misa_ext = cpu->env.misa_ext; 1574 Property *prop; 1575 DeviceState *dev = DEVICE(obj); 1576 1577 /* 1578 * If misa_ext is not zero, set cfg properties now to 1579 * allow them to be read during riscv_cpu_realize() 1580 * later on. 1581 */ 1582 if (cpu->env.misa_ext != 0) { 1583 cpu->cfg.ext_i = misa_ext & RVI; 1584 cpu->cfg.ext_e = misa_ext & RVE; 1585 cpu->cfg.ext_m = misa_ext & RVM; 1586 cpu->cfg.ext_a = misa_ext & RVA; 1587 cpu->cfg.ext_f = misa_ext & RVF; 1588 cpu->cfg.ext_d = misa_ext & RVD; 1589 cpu->cfg.ext_v = misa_ext & RVV; 1590 cpu->cfg.ext_c = misa_ext & RVC; 1591 cpu->cfg.ext_s = misa_ext & RVS; 1592 cpu->cfg.ext_u = misa_ext & RVU; 1593 cpu->cfg.ext_h = misa_ext & RVH; 1594 cpu->cfg.ext_j = misa_ext & RVJ; 1595 1596 /* 1597 * We don't want to set the default riscv_cpu_extensions 1598 * in this case. 1599 */ 1600 return; 1601 } 1602 1603 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1604 qdev_property_add_static(dev, prop); 1605 } 1606 1607 #ifndef CONFIG_USER_ONLY 1608 riscv_add_satp_mode_properties(obj); 1609 #endif 1610 } 1611 1612 static Property riscv_cpu_properties[] = { 1613 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1614 1615 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1616 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1617 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1618 1619 #ifndef CONFIG_USER_ONLY 1620 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1621 #endif 1622 1623 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1624 1625 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1626 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1627 1628 /* 1629 * write_misa() is marked as experimental for now so mark 1630 * it with -x and default to 'false'. 1631 */ 1632 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1633 DEFINE_PROP_END_OF_LIST(), 1634 }; 1635 1636 static gchar *riscv_gdb_arch_name(CPUState *cs) 1637 { 1638 RISCVCPU *cpu = RISCV_CPU(cs); 1639 CPURISCVState *env = &cpu->env; 1640 1641 switch (riscv_cpu_mxl(env)) { 1642 case MXL_RV32: 1643 return g_strdup("riscv:rv32"); 1644 case MXL_RV64: 1645 case MXL_RV128: 1646 return g_strdup("riscv:rv64"); 1647 default: 1648 g_assert_not_reached(); 1649 } 1650 } 1651 1652 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1653 { 1654 RISCVCPU *cpu = RISCV_CPU(cs); 1655 1656 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1657 return cpu->dyn_csr_xml; 1658 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1659 return cpu->dyn_vreg_xml; 1660 } 1661 1662 return NULL; 1663 } 1664 1665 #ifndef CONFIG_USER_ONLY 1666 static int64_t riscv_get_arch_id(CPUState *cs) 1667 { 1668 RISCVCPU *cpu = RISCV_CPU(cs); 1669 1670 return cpu->env.mhartid; 1671 } 1672 1673 #include "hw/core/sysemu-cpu-ops.h" 1674 1675 static const struct SysemuCPUOps riscv_sysemu_ops = { 1676 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1677 .write_elf64_note = riscv_cpu_write_elf64_note, 1678 .write_elf32_note = riscv_cpu_write_elf32_note, 1679 .legacy_vmsd = &vmstate_riscv_cpu, 1680 }; 1681 #endif 1682 1683 #include "hw/core/tcg-cpu-ops.h" 1684 1685 static const struct TCGCPUOps riscv_tcg_ops = { 1686 .initialize = riscv_translate_init, 1687 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1688 .restore_state_to_opc = riscv_restore_state_to_opc, 1689 1690 #ifndef CONFIG_USER_ONLY 1691 .tlb_fill = riscv_cpu_tlb_fill, 1692 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1693 .do_interrupt = riscv_cpu_do_interrupt, 1694 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1695 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1696 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1697 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1698 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1699 #endif /* !CONFIG_USER_ONLY */ 1700 }; 1701 1702 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1703 { 1704 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1705 CPUClass *cc = CPU_CLASS(c); 1706 DeviceClass *dc = DEVICE_CLASS(c); 1707 ResettableClass *rc = RESETTABLE_CLASS(c); 1708 1709 device_class_set_parent_realize(dc, riscv_cpu_realize, 1710 &mcc->parent_realize); 1711 1712 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1713 &mcc->parent_phases); 1714 1715 cc->class_by_name = riscv_cpu_class_by_name; 1716 cc->has_work = riscv_cpu_has_work; 1717 cc->dump_state = riscv_cpu_dump_state; 1718 cc->set_pc = riscv_cpu_set_pc; 1719 cc->get_pc = riscv_cpu_get_pc; 1720 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1721 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1722 cc->gdb_num_core_regs = 33; 1723 cc->gdb_stop_before_watchpoint = true; 1724 cc->disas_set_info = riscv_cpu_disas_set_info; 1725 #ifndef CONFIG_USER_ONLY 1726 cc->sysemu_ops = &riscv_sysemu_ops; 1727 cc->get_arch_id = riscv_get_arch_id; 1728 #endif 1729 cc->gdb_arch_name = riscv_gdb_arch_name; 1730 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1731 cc->tcg_ops = &riscv_tcg_ops; 1732 1733 device_class_set_props(dc, riscv_cpu_properties); 1734 } 1735 1736 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, 1737 int max_str_len) 1738 { 1739 char *old = *isa_str; 1740 char *new = *isa_str; 1741 int i; 1742 1743 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1744 if (isa_edata_arr[i].multi_letter && 1745 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1746 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1747 g_free(old); 1748 old = new; 1749 } 1750 } 1751 1752 *isa_str = new; 1753 } 1754 1755 char *riscv_isa_string(RISCVCPU *cpu) 1756 { 1757 int i; 1758 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1759 char *isa_str = g_new(char, maxlen); 1760 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1761 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1762 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1763 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1764 } 1765 } 1766 *p = '\0'; 1767 if (!cpu->cfg.short_isa_string) { 1768 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1769 } 1770 return isa_str; 1771 } 1772 1773 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1774 { 1775 ObjectClass *class_a = (ObjectClass *)a; 1776 ObjectClass *class_b = (ObjectClass *)b; 1777 const char *name_a, *name_b; 1778 1779 name_a = object_class_get_name(class_a); 1780 name_b = object_class_get_name(class_b); 1781 return strcmp(name_a, name_b); 1782 } 1783 1784 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1785 { 1786 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1787 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1788 1789 qemu_printf("%.*s\n", len, typename); 1790 } 1791 1792 void riscv_cpu_list(void) 1793 { 1794 GSList *list; 1795 1796 list = object_class_get_list(TYPE_RISCV_CPU, false); 1797 list = g_slist_sort(list, riscv_cpu_list_compare); 1798 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1799 g_slist_free(list); 1800 } 1801 1802 #define DEFINE_CPU(type_name, initfn) \ 1803 { \ 1804 .name = type_name, \ 1805 .parent = TYPE_RISCV_CPU, \ 1806 .instance_init = initfn \ 1807 } 1808 1809 static const TypeInfo riscv_cpu_type_infos[] = { 1810 { 1811 .name = TYPE_RISCV_CPU, 1812 .parent = TYPE_CPU, 1813 .instance_size = sizeof(RISCVCPU), 1814 .instance_align = __alignof__(RISCVCPU), 1815 .instance_init = riscv_cpu_init, 1816 .abstract = true, 1817 .class_size = sizeof(RISCVCPUClass), 1818 .class_init = riscv_cpu_class_init, 1819 }, 1820 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1821 #if defined(CONFIG_KVM) 1822 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1823 #endif 1824 #if defined(TARGET_RISCV32) 1825 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1826 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1827 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1828 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1829 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1830 #elif defined(TARGET_RISCV64) 1831 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1832 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1833 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1834 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1835 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1836 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1837 #endif 1838 }; 1839 1840 DEFINE_TYPES(riscv_cpu_type_infos) 1841