1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "pmu.h" 26 #include "internals.h" 27 #include "time_helper.h" 28 #include "exec/exec-all.h" 29 #include "qapi/error.h" 30 #include "qemu/error-report.h" 31 #include "hw/qdev-properties.h" 32 #include "migration/vmstate.h" 33 #include "fpu/softfloat-helpers.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_riscv.h" 36 37 /* RISC-V CPU definitions */ 38 39 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 40 (QEMU_VERSION_MINOR << 8) | \ 41 (QEMU_VERSION_MICRO)) 42 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 43 44 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 45 46 struct isa_ext_data { 47 const char *name; 48 bool multi_letter; 49 int min_version; 50 int ext_enable_offset; 51 }; 52 53 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ 54 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 55 56 /** 57 * Here are the ordering rules of extension naming defined by RISC-V 58 * specification : 59 * 1. All extensions should be separated from other multi-letter extensions 60 * by an underscore. 61 * 2. The first letter following the 'Z' conventionally indicates the most 62 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 63 * If multiple 'Z' extensions are named, they should be ordered first 64 * by category, then alphabetically within a category. 65 * 3. Standard supervisor-level extensions (starts with 'S') should be 66 * listed after standard unprivileged extensions. If multiple 67 * supervisor-level extensions are listed, they should be ordered 68 * alphabetically. 69 * 4. Non-standard extensions (starts with 'X') must be listed after all 70 * standard extensions. They must be separated from other multi-letter 71 * extensions by an underscore. 72 */ 73 static const struct isa_ext_data isa_edata_arr[] = { 74 ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), 75 ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), 76 ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), 77 ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), 78 ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), 79 ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), 80 ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), 81 ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), 82 ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), 83 ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), 84 ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), 85 ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), 86 ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), 87 ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), 88 ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), 89 ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), 90 ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), 91 ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), 92 ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), 93 ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), 94 ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), 95 ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), 96 ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), 97 ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), 98 ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), 99 ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), 100 ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), 101 ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), 102 ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), 103 ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), 104 ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), 105 ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), 106 ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), 107 ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), 108 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), 109 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), 110 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), 111 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 112 }; 113 114 static bool isa_ext_is_enabled(RISCVCPU *cpu, 115 const struct isa_ext_data *edata) 116 { 117 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 118 119 return *ext_enabled; 120 } 121 122 static void isa_ext_update_enabled(RISCVCPU *cpu, 123 const struct isa_ext_data *edata, bool en) 124 { 125 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 126 127 *ext_enabled = en; 128 } 129 130 const char * const riscv_int_regnames[] = { 131 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 132 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 133 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 134 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 135 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 136 }; 137 138 const char * const riscv_int_regnamesh[] = { 139 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 140 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 141 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 142 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 143 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 144 "x30h/t5h", "x31h/t6h" 145 }; 146 147 const char * const riscv_fpr_regnames[] = { 148 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 149 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 150 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 151 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 152 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 153 "f30/ft10", "f31/ft11" 154 }; 155 156 static const char * const riscv_excp_names[] = { 157 "misaligned_fetch", 158 "fault_fetch", 159 "illegal_instruction", 160 "breakpoint", 161 "misaligned_load", 162 "fault_load", 163 "misaligned_store", 164 "fault_store", 165 "user_ecall", 166 "supervisor_ecall", 167 "hypervisor_ecall", 168 "machine_ecall", 169 "exec_page_fault", 170 "load_page_fault", 171 "reserved", 172 "store_page_fault", 173 "reserved", 174 "reserved", 175 "reserved", 176 "reserved", 177 "guest_exec_page_fault", 178 "guest_load_page_fault", 179 "reserved", 180 "guest_store_page_fault", 181 }; 182 183 static const char * const riscv_intr_names[] = { 184 "u_software", 185 "s_software", 186 "vs_software", 187 "m_software", 188 "u_timer", 189 "s_timer", 190 "vs_timer", 191 "m_timer", 192 "u_external", 193 "s_external", 194 "vs_external", 195 "m_external", 196 "reserved", 197 "reserved", 198 "reserved", 199 "reserved" 200 }; 201 202 static void register_cpu_props(DeviceState *dev); 203 204 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 205 { 206 if (async) { 207 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 208 riscv_intr_names[cause] : "(unknown)"; 209 } else { 210 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 211 riscv_excp_names[cause] : "(unknown)"; 212 } 213 } 214 215 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 216 { 217 env->misa_mxl_max = env->misa_mxl = mxl; 218 env->misa_ext_mask = env->misa_ext = ext; 219 } 220 221 static void set_priv_version(CPURISCVState *env, int priv_ver) 222 { 223 env->priv_ver = priv_ver; 224 } 225 226 static void set_vext_version(CPURISCVState *env, int vext_ver) 227 { 228 env->vext_ver = vext_ver; 229 } 230 231 static void set_resetvec(CPURISCVState *env, target_ulong resetvec) 232 { 233 #ifndef CONFIG_USER_ONLY 234 env->resetvec = resetvec; 235 #endif 236 } 237 238 static void riscv_any_cpu_init(Object *obj) 239 { 240 CPURISCVState *env = &RISCV_CPU(obj)->env; 241 #if defined(TARGET_RISCV32) 242 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 243 #elif defined(TARGET_RISCV64) 244 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 245 #endif 246 set_priv_version(env, PRIV_VERSION_1_12_0); 247 register_cpu_props(DEVICE(obj)); 248 } 249 250 #if defined(TARGET_RISCV64) 251 static void rv64_base_cpu_init(Object *obj) 252 { 253 CPURISCVState *env = &RISCV_CPU(obj)->env; 254 /* We set this in the realise function */ 255 set_misa(env, MXL_RV64, 0); 256 register_cpu_props(DEVICE(obj)); 257 /* Set latest version of privileged specification */ 258 set_priv_version(env, PRIV_VERSION_1_12_0); 259 } 260 261 static void rv64_sifive_u_cpu_init(Object *obj) 262 { 263 CPURISCVState *env = &RISCV_CPU(obj)->env; 264 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 265 set_priv_version(env, PRIV_VERSION_1_10_0); 266 } 267 268 static void rv64_sifive_e_cpu_init(Object *obj) 269 { 270 CPURISCVState *env = &RISCV_CPU(obj)->env; 271 RISCVCPU *cpu = RISCV_CPU(obj); 272 273 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 274 set_priv_version(env, PRIV_VERSION_1_10_0); 275 cpu->cfg.mmu = false; 276 } 277 278 static void rv128_base_cpu_init(Object *obj) 279 { 280 if (qemu_tcg_mttcg_enabled()) { 281 /* Missing 128-bit aligned atomics */ 282 error_report("128-bit RISC-V currently does not work with Multi " 283 "Threaded TCG. Please use: -accel tcg,thread=single"); 284 exit(EXIT_FAILURE); 285 } 286 CPURISCVState *env = &RISCV_CPU(obj)->env; 287 /* We set this in the realise function */ 288 set_misa(env, MXL_RV128, 0); 289 register_cpu_props(DEVICE(obj)); 290 /* Set latest version of privileged specification */ 291 set_priv_version(env, PRIV_VERSION_1_12_0); 292 } 293 #else 294 static void rv32_base_cpu_init(Object *obj) 295 { 296 CPURISCVState *env = &RISCV_CPU(obj)->env; 297 /* We set this in the realise function */ 298 set_misa(env, MXL_RV32, 0); 299 register_cpu_props(DEVICE(obj)); 300 /* Set latest version of privileged specification */ 301 set_priv_version(env, PRIV_VERSION_1_12_0); 302 } 303 304 static void rv32_sifive_u_cpu_init(Object *obj) 305 { 306 CPURISCVState *env = &RISCV_CPU(obj)->env; 307 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 308 set_priv_version(env, PRIV_VERSION_1_10_0); 309 } 310 311 static void rv32_sifive_e_cpu_init(Object *obj) 312 { 313 CPURISCVState *env = &RISCV_CPU(obj)->env; 314 RISCVCPU *cpu = RISCV_CPU(obj); 315 316 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 317 set_priv_version(env, PRIV_VERSION_1_10_0); 318 cpu->cfg.mmu = false; 319 } 320 321 static void rv32_ibex_cpu_init(Object *obj) 322 { 323 CPURISCVState *env = &RISCV_CPU(obj)->env; 324 RISCVCPU *cpu = RISCV_CPU(obj); 325 326 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 327 set_priv_version(env, PRIV_VERSION_1_11_0); 328 cpu->cfg.mmu = false; 329 cpu->cfg.epmp = true; 330 } 331 332 static void rv32_imafcu_nommu_cpu_init(Object *obj) 333 { 334 CPURISCVState *env = &RISCV_CPU(obj)->env; 335 RISCVCPU *cpu = RISCV_CPU(obj); 336 337 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 338 set_priv_version(env, PRIV_VERSION_1_10_0); 339 set_resetvec(env, DEFAULT_RSTVEC); 340 cpu->cfg.mmu = false; 341 } 342 #endif 343 344 #if defined(CONFIG_KVM) 345 static void riscv_host_cpu_init(Object *obj) 346 { 347 CPURISCVState *env = &RISCV_CPU(obj)->env; 348 #if defined(TARGET_RISCV32) 349 set_misa(env, MXL_RV32, 0); 350 #elif defined(TARGET_RISCV64) 351 set_misa(env, MXL_RV64, 0); 352 #endif 353 register_cpu_props(DEVICE(obj)); 354 } 355 #endif 356 357 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 358 { 359 ObjectClass *oc; 360 char *typename; 361 char **cpuname; 362 363 cpuname = g_strsplit(cpu_model, ",", 1); 364 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 365 oc = object_class_by_name(typename); 366 g_strfreev(cpuname); 367 g_free(typename); 368 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 369 object_class_is_abstract(oc)) { 370 return NULL; 371 } 372 return oc; 373 } 374 375 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 376 { 377 RISCVCPU *cpu = RISCV_CPU(cs); 378 CPURISCVState *env = &cpu->env; 379 int i; 380 381 #if !defined(CONFIG_USER_ONLY) 382 if (riscv_has_ext(env, RVH)) { 383 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 384 } 385 #endif 386 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 387 #ifndef CONFIG_USER_ONLY 388 { 389 static const int dump_csrs[] = { 390 CSR_MHARTID, 391 CSR_MSTATUS, 392 CSR_MSTATUSH, 393 CSR_HSTATUS, 394 CSR_VSSTATUS, 395 CSR_MIP, 396 CSR_MIE, 397 CSR_MIDELEG, 398 CSR_HIDELEG, 399 CSR_MEDELEG, 400 CSR_HEDELEG, 401 CSR_MTVEC, 402 CSR_STVEC, 403 CSR_VSTVEC, 404 CSR_MEPC, 405 CSR_SEPC, 406 CSR_VSEPC, 407 CSR_MCAUSE, 408 CSR_SCAUSE, 409 CSR_VSCAUSE, 410 CSR_MTVAL, 411 CSR_STVAL, 412 CSR_HTVAL, 413 CSR_MTVAL2, 414 CSR_MSCRATCH, 415 CSR_SSCRATCH, 416 CSR_SATP, 417 CSR_MMTE, 418 CSR_UPMBASE, 419 CSR_UPMMASK, 420 CSR_SPMBASE, 421 CSR_SPMMASK, 422 CSR_MPMBASE, 423 CSR_MPMMASK, 424 }; 425 426 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 427 int csrno = dump_csrs[i]; 428 target_ulong val = 0; 429 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 430 431 /* 432 * Rely on the smode, hmode, etc, predicates within csr.c 433 * to do the filtering of the registers that are present. 434 */ 435 if (res == RISCV_EXCP_NONE) { 436 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 437 csr_ops[csrno].name, val); 438 } 439 } 440 } 441 #endif 442 443 for (i = 0; i < 32; i++) { 444 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 445 riscv_int_regnames[i], env->gpr[i]); 446 if ((i & 3) == 3) { 447 qemu_fprintf(f, "\n"); 448 } 449 } 450 if (flags & CPU_DUMP_FPU) { 451 for (i = 0; i < 32; i++) { 452 qemu_fprintf(f, " %-8s %016" PRIx64, 453 riscv_fpr_regnames[i], env->fpr[i]); 454 if ((i & 3) == 3) { 455 qemu_fprintf(f, "\n"); 456 } 457 } 458 } 459 } 460 461 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 462 { 463 RISCVCPU *cpu = RISCV_CPU(cs); 464 CPURISCVState *env = &cpu->env; 465 466 if (env->xl == MXL_RV32) { 467 env->pc = (int32_t)value; 468 } else { 469 env->pc = value; 470 } 471 } 472 473 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 474 const TranslationBlock *tb) 475 { 476 RISCVCPU *cpu = RISCV_CPU(cs); 477 CPURISCVState *env = &cpu->env; 478 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 479 480 if (xl == MXL_RV32) { 481 env->pc = (int32_t)tb->pc; 482 } else { 483 env->pc = tb->pc; 484 } 485 } 486 487 static bool riscv_cpu_has_work(CPUState *cs) 488 { 489 #ifndef CONFIG_USER_ONLY 490 RISCVCPU *cpu = RISCV_CPU(cs); 491 CPURISCVState *env = &cpu->env; 492 /* 493 * Definition of the WFI instruction requires it to ignore the privilege 494 * mode and delegation registers, but respect individual enables 495 */ 496 return riscv_cpu_all_pending(env) != 0; 497 #else 498 return true; 499 #endif 500 } 501 502 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 503 target_ulong *data) 504 { 505 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 506 if (xl == MXL_RV32) { 507 env->pc = (int32_t)data[0]; 508 } else { 509 env->pc = data[0]; 510 } 511 env->bins = data[1]; 512 } 513 514 static void riscv_cpu_reset(DeviceState *dev) 515 { 516 #ifndef CONFIG_USER_ONLY 517 uint8_t iprio; 518 int i, irq, rdzero; 519 #endif 520 CPUState *cs = CPU(dev); 521 RISCVCPU *cpu = RISCV_CPU(cs); 522 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 523 CPURISCVState *env = &cpu->env; 524 525 mcc->parent_reset(dev); 526 #ifndef CONFIG_USER_ONLY 527 env->misa_mxl = env->misa_mxl_max; 528 env->priv = PRV_M; 529 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 530 if (env->misa_mxl > MXL_RV32) { 531 /* 532 * The reset status of SXL/UXL is undefined, but mstatus is WARL 533 * and we must ensure that the value after init is valid for read. 534 */ 535 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 536 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 537 if (riscv_has_ext(env, RVH)) { 538 env->vsstatus = set_field(env->vsstatus, 539 MSTATUS64_SXL, env->misa_mxl); 540 env->vsstatus = set_field(env->vsstatus, 541 MSTATUS64_UXL, env->misa_mxl); 542 env->mstatus_hs = set_field(env->mstatus_hs, 543 MSTATUS64_SXL, env->misa_mxl); 544 env->mstatus_hs = set_field(env->mstatus_hs, 545 MSTATUS64_UXL, env->misa_mxl); 546 } 547 } 548 env->mcause = 0; 549 env->miclaim = MIP_SGEIP; 550 env->pc = env->resetvec; 551 env->bins = 0; 552 env->two_stage_lookup = false; 553 554 /* Initialized default priorities of local interrupts. */ 555 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 556 iprio = riscv_cpu_default_priority(i); 557 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 558 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 559 env->hviprio[i] = 0; 560 } 561 i = 0; 562 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 563 if (!rdzero) { 564 env->hviprio[irq] = env->miprio[irq]; 565 } 566 i++; 567 } 568 /* mmte is supposed to have pm.current hardwired to 1 */ 569 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 570 #endif 571 env->xl = riscv_cpu_mxl(env); 572 riscv_cpu_update_mask(env); 573 cs->exception_index = RISCV_EXCP_NONE; 574 env->load_res = -1; 575 set_default_nan_mode(1, &env->fp_status); 576 577 #ifndef CONFIG_USER_ONLY 578 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 579 riscv_trigger_init(env); 580 } 581 582 if (kvm_enabled()) { 583 kvm_riscv_reset_vcpu(cpu); 584 } 585 #endif 586 } 587 588 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 589 { 590 RISCVCPU *cpu = RISCV_CPU(s); 591 592 switch (riscv_cpu_mxl(&cpu->env)) { 593 case MXL_RV32: 594 info->print_insn = print_insn_riscv32; 595 break; 596 case MXL_RV64: 597 info->print_insn = print_insn_riscv64; 598 break; 599 case MXL_RV128: 600 info->print_insn = print_insn_riscv128; 601 break; 602 default: 603 g_assert_not_reached(); 604 } 605 } 606 607 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 608 { 609 CPUState *cs = CPU(dev); 610 RISCVCPU *cpu = RISCV_CPU(dev); 611 CPURISCVState *env = &cpu->env; 612 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 613 CPUClass *cc = CPU_CLASS(mcc); 614 int i, priv_version = -1; 615 Error *local_err = NULL; 616 617 cpu_exec_realizefn(cs, &local_err); 618 if (local_err != NULL) { 619 error_propagate(errp, local_err); 620 return; 621 } 622 623 if (cpu->cfg.priv_spec) { 624 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 625 priv_version = PRIV_VERSION_1_12_0; 626 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 627 priv_version = PRIV_VERSION_1_11_0; 628 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 629 priv_version = PRIV_VERSION_1_10_0; 630 } else { 631 error_setg(errp, 632 "Unsupported privilege spec version '%s'", 633 cpu->cfg.priv_spec); 634 return; 635 } 636 } 637 638 if (priv_version >= PRIV_VERSION_1_10_0) { 639 set_priv_version(env, priv_version); 640 } 641 642 /* Force disable extensions if priv spec version does not match */ 643 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 644 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 645 (env->priv_ver < isa_edata_arr[i].min_version)) { 646 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 647 #ifndef CONFIG_USER_ONLY 648 warn_report("disabling %s extension for hart 0x%lx because " 649 "privilege spec version does not match", 650 isa_edata_arr[i].name, (unsigned long)env->mhartid); 651 #else 652 warn_report("disabling %s extension because " 653 "privilege spec version does not match", 654 isa_edata_arr[i].name); 655 #endif 656 } 657 } 658 659 if (cpu->cfg.mmu) { 660 riscv_set_feature(env, RISCV_FEATURE_MMU); 661 } 662 663 if (cpu->cfg.pmp) { 664 riscv_set_feature(env, RISCV_FEATURE_PMP); 665 666 /* 667 * Enhanced PMP should only be available 668 * on harts with PMP support 669 */ 670 if (cpu->cfg.epmp) { 671 riscv_set_feature(env, RISCV_FEATURE_EPMP); 672 } 673 } 674 675 if (cpu->cfg.debug) { 676 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 677 } 678 679 set_resetvec(env, cpu->cfg.resetvec); 680 681 #ifndef CONFIG_USER_ONLY 682 if (cpu->cfg.ext_sstc) { 683 riscv_timer_init(cpu); 684 } 685 #endif /* CONFIG_USER_ONLY */ 686 687 /* Validate that MISA_MXL is set properly. */ 688 switch (env->misa_mxl_max) { 689 #ifdef TARGET_RISCV64 690 case MXL_RV64: 691 case MXL_RV128: 692 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 693 break; 694 #endif 695 case MXL_RV32: 696 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 697 break; 698 default: 699 g_assert_not_reached(); 700 } 701 assert(env->misa_mxl_max == env->misa_mxl); 702 703 /* If only MISA_EXT is unset for misa, then set it from properties */ 704 if (env->misa_ext == 0) { 705 uint32_t ext = 0; 706 707 /* Do some ISA extension error checking */ 708 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 709 cpu->cfg.ext_a && cpu->cfg.ext_f && 710 cpu->cfg.ext_d && 711 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 712 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 713 cpu->cfg.ext_i = true; 714 cpu->cfg.ext_m = true; 715 cpu->cfg.ext_a = true; 716 cpu->cfg.ext_f = true; 717 cpu->cfg.ext_d = true; 718 cpu->cfg.ext_icsr = true; 719 cpu->cfg.ext_ifencei = true; 720 } 721 722 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 723 error_setg(errp, 724 "I and E extensions are incompatible"); 725 return; 726 } 727 728 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 729 error_setg(errp, 730 "Either I or E extension must be set"); 731 return; 732 } 733 734 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 735 error_setg(errp, 736 "Setting S extension without U extension is illegal"); 737 return; 738 } 739 740 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { 741 error_setg(errp, 742 "H depends on an I base integer ISA with 32 x registers"); 743 return; 744 } 745 746 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 747 error_setg(errp, "H extension implicitly requires S-mode"); 748 return; 749 } 750 751 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 752 error_setg(errp, "F extension requires Zicsr"); 753 return; 754 } 755 756 if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { 757 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 758 return; 759 } 760 761 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 762 error_setg(errp, "D extension requires F extension"); 763 return; 764 } 765 766 if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { 767 error_setg(errp, "V extension requires D extension"); 768 return; 769 } 770 771 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 772 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 773 return; 774 } 775 776 /* Set the ISA extensions, checks should have happened above */ 777 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || 778 cpu->cfg.ext_zhinxmin) { 779 cpu->cfg.ext_zfinx = true; 780 } 781 782 if (cpu->cfg.ext_zfinx) { 783 if (!cpu->cfg.ext_icsr) { 784 error_setg(errp, "Zfinx extension requires Zicsr"); 785 return; 786 } 787 if (cpu->cfg.ext_f) { 788 error_setg(errp, 789 "Zfinx cannot be supported together with F extension"); 790 return; 791 } 792 } 793 794 if (cpu->cfg.ext_zk) { 795 cpu->cfg.ext_zkn = true; 796 cpu->cfg.ext_zkr = true; 797 cpu->cfg.ext_zkt = true; 798 } 799 800 if (cpu->cfg.ext_zkn) { 801 cpu->cfg.ext_zbkb = true; 802 cpu->cfg.ext_zbkc = true; 803 cpu->cfg.ext_zbkx = true; 804 cpu->cfg.ext_zkne = true; 805 cpu->cfg.ext_zknd = true; 806 cpu->cfg.ext_zknh = true; 807 } 808 809 if (cpu->cfg.ext_zks) { 810 cpu->cfg.ext_zbkb = true; 811 cpu->cfg.ext_zbkc = true; 812 cpu->cfg.ext_zbkx = true; 813 cpu->cfg.ext_zksed = true; 814 cpu->cfg.ext_zksh = true; 815 } 816 817 if (cpu->cfg.ext_i) { 818 ext |= RVI; 819 } 820 if (cpu->cfg.ext_e) { 821 ext |= RVE; 822 } 823 if (cpu->cfg.ext_m) { 824 ext |= RVM; 825 } 826 if (cpu->cfg.ext_a) { 827 ext |= RVA; 828 } 829 if (cpu->cfg.ext_f) { 830 ext |= RVF; 831 } 832 if (cpu->cfg.ext_d) { 833 ext |= RVD; 834 } 835 if (cpu->cfg.ext_c) { 836 ext |= RVC; 837 } 838 if (cpu->cfg.ext_s) { 839 ext |= RVS; 840 } 841 if (cpu->cfg.ext_u) { 842 ext |= RVU; 843 } 844 if (cpu->cfg.ext_h) { 845 ext |= RVH; 846 } 847 if (cpu->cfg.ext_v) { 848 int vext_version = VEXT_VERSION_1_00_0; 849 ext |= RVV; 850 if (!is_power_of_2(cpu->cfg.vlen)) { 851 error_setg(errp, 852 "Vector extension VLEN must be power of 2"); 853 return; 854 } 855 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 856 error_setg(errp, 857 "Vector extension implementation only supports VLEN " 858 "in the range [128, %d]", RV_VLEN_MAX); 859 return; 860 } 861 if (!is_power_of_2(cpu->cfg.elen)) { 862 error_setg(errp, 863 "Vector extension ELEN must be power of 2"); 864 return; 865 } 866 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 867 error_setg(errp, 868 "Vector extension implementation only supports ELEN " 869 "in the range [8, 64]"); 870 return; 871 } 872 if (cpu->cfg.vext_spec) { 873 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 874 vext_version = VEXT_VERSION_1_00_0; 875 } else { 876 error_setg(errp, 877 "Unsupported vector spec version '%s'", 878 cpu->cfg.vext_spec); 879 return; 880 } 881 } else { 882 qemu_log("vector version is not specified, " 883 "use the default value v1.0\n"); 884 } 885 set_vext_version(env, vext_version); 886 } 887 if (cpu->cfg.ext_j) { 888 ext |= RVJ; 889 } 890 891 set_misa(env, env->misa_mxl, ext); 892 } 893 894 #ifndef CONFIG_USER_ONLY 895 if (cpu->cfg.pmu_num) { 896 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 897 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 898 riscv_pmu_timer_cb, cpu); 899 } 900 } 901 #endif 902 903 riscv_cpu_register_gdb_regs_for_features(cs); 904 905 qemu_init_vcpu(cs); 906 cpu_reset(cs); 907 908 mcc->parent_realize(dev, errp); 909 } 910 911 #ifndef CONFIG_USER_ONLY 912 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 913 { 914 RISCVCPU *cpu = RISCV_CPU(opaque); 915 CPURISCVState *env = &cpu->env; 916 917 if (irq < IRQ_LOCAL_MAX) { 918 switch (irq) { 919 case IRQ_U_SOFT: 920 case IRQ_S_SOFT: 921 case IRQ_VS_SOFT: 922 case IRQ_M_SOFT: 923 case IRQ_U_TIMER: 924 case IRQ_S_TIMER: 925 case IRQ_VS_TIMER: 926 case IRQ_M_TIMER: 927 case IRQ_U_EXT: 928 case IRQ_VS_EXT: 929 case IRQ_M_EXT: 930 if (kvm_enabled()) { 931 kvm_riscv_set_irq(cpu, irq, level); 932 } else { 933 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 934 } 935 break; 936 case IRQ_S_EXT: 937 if (kvm_enabled()) { 938 kvm_riscv_set_irq(cpu, irq, level); 939 } else { 940 env->external_seip = level; 941 riscv_cpu_update_mip(cpu, 1 << irq, 942 BOOL_TO_MASK(level | env->software_seip)); 943 } 944 break; 945 default: 946 g_assert_not_reached(); 947 } 948 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 949 /* Require H-extension for handling guest local interrupts */ 950 if (!riscv_has_ext(env, RVH)) { 951 g_assert_not_reached(); 952 } 953 954 /* Compute bit position in HGEIP CSR */ 955 irq = irq - IRQ_LOCAL_MAX + 1; 956 if (env->geilen < irq) { 957 g_assert_not_reached(); 958 } 959 960 /* Update HGEIP CSR */ 961 env->hgeip &= ~((target_ulong)1 << irq); 962 if (level) { 963 env->hgeip |= (target_ulong)1 << irq; 964 } 965 966 /* Update mip.SGEIP bit */ 967 riscv_cpu_update_mip(cpu, MIP_SGEIP, 968 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 969 } else { 970 g_assert_not_reached(); 971 } 972 } 973 #endif /* CONFIG_USER_ONLY */ 974 975 static void riscv_cpu_init(Object *obj) 976 { 977 RISCVCPU *cpu = RISCV_CPU(obj); 978 979 cpu->cfg.ext_ifencei = true; 980 cpu->cfg.ext_icsr = true; 981 cpu->cfg.mmu = true; 982 cpu->cfg.pmp = true; 983 984 cpu_set_cpustate_pointers(cpu); 985 986 #ifndef CONFIG_USER_ONLY 987 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 988 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 989 #endif /* CONFIG_USER_ONLY */ 990 } 991 992 static Property riscv_cpu_extensions[] = { 993 /* Defaults for standard extensions */ 994 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 995 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 996 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 997 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 998 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 999 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 1000 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 1001 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 1002 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 1003 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1004 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1005 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1006 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1007 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1008 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1009 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1010 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1011 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1012 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1013 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1014 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1015 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1016 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1017 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1018 1019 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1020 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1021 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1022 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1023 1024 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1025 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1026 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1027 1028 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1029 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1030 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1031 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1032 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1033 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1034 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1035 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1036 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1037 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1038 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1039 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1040 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1041 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1042 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1043 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1044 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1045 1046 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1047 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1048 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1049 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1050 1051 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1052 1053 /* Vendor-specific custom extensions */ 1054 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1055 1056 /* These are experimental so mark with 'x-' */ 1057 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1058 /* ePMP 0.9.3 */ 1059 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1060 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1061 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1062 1063 DEFINE_PROP_END_OF_LIST(), 1064 }; 1065 1066 static void register_cpu_props(DeviceState *dev) 1067 { 1068 Property *prop; 1069 1070 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1071 qdev_property_add_static(dev, prop); 1072 } 1073 } 1074 1075 static Property riscv_cpu_properties[] = { 1076 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1077 1078 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1079 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1080 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1081 1082 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 1083 1084 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1085 1086 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1087 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1088 DEFINE_PROP_END_OF_LIST(), 1089 }; 1090 1091 static gchar *riscv_gdb_arch_name(CPUState *cs) 1092 { 1093 RISCVCPU *cpu = RISCV_CPU(cs); 1094 CPURISCVState *env = &cpu->env; 1095 1096 switch (riscv_cpu_mxl(env)) { 1097 case MXL_RV32: 1098 return g_strdup("riscv:rv32"); 1099 case MXL_RV64: 1100 case MXL_RV128: 1101 return g_strdup("riscv:rv64"); 1102 default: 1103 g_assert_not_reached(); 1104 } 1105 } 1106 1107 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1108 { 1109 RISCVCPU *cpu = RISCV_CPU(cs); 1110 1111 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1112 return cpu->dyn_csr_xml; 1113 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1114 return cpu->dyn_vreg_xml; 1115 } 1116 1117 return NULL; 1118 } 1119 1120 #ifndef CONFIG_USER_ONLY 1121 #include "hw/core/sysemu-cpu-ops.h" 1122 1123 static const struct SysemuCPUOps riscv_sysemu_ops = { 1124 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1125 .write_elf64_note = riscv_cpu_write_elf64_note, 1126 .write_elf32_note = riscv_cpu_write_elf32_note, 1127 .legacy_vmsd = &vmstate_riscv_cpu, 1128 }; 1129 #endif 1130 1131 #include "hw/core/tcg-cpu-ops.h" 1132 1133 static const struct TCGCPUOps riscv_tcg_ops = { 1134 .initialize = riscv_translate_init, 1135 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1136 1137 #ifndef CONFIG_USER_ONLY 1138 .tlb_fill = riscv_cpu_tlb_fill, 1139 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1140 .do_interrupt = riscv_cpu_do_interrupt, 1141 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1142 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1143 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1144 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1145 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1146 #endif /* !CONFIG_USER_ONLY */ 1147 }; 1148 1149 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1150 { 1151 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1152 CPUClass *cc = CPU_CLASS(c); 1153 DeviceClass *dc = DEVICE_CLASS(c); 1154 1155 device_class_set_parent_realize(dc, riscv_cpu_realize, 1156 &mcc->parent_realize); 1157 1158 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 1159 1160 cc->class_by_name = riscv_cpu_class_by_name; 1161 cc->has_work = riscv_cpu_has_work; 1162 cc->dump_state = riscv_cpu_dump_state; 1163 cc->set_pc = riscv_cpu_set_pc; 1164 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1165 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1166 cc->gdb_num_core_regs = 33; 1167 cc->gdb_stop_before_watchpoint = true; 1168 cc->disas_set_info = riscv_cpu_disas_set_info; 1169 #ifndef CONFIG_USER_ONLY 1170 cc->sysemu_ops = &riscv_sysemu_ops; 1171 #endif 1172 cc->gdb_arch_name = riscv_gdb_arch_name; 1173 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1174 cc->tcg_ops = &riscv_tcg_ops; 1175 1176 device_class_set_props(dc, riscv_cpu_properties); 1177 } 1178 1179 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1180 { 1181 char *old = *isa_str; 1182 char *new = *isa_str; 1183 int i; 1184 1185 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1186 if (isa_edata_arr[i].multi_letter && 1187 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1188 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1189 g_free(old); 1190 old = new; 1191 } 1192 } 1193 1194 *isa_str = new; 1195 } 1196 1197 char *riscv_isa_string(RISCVCPU *cpu) 1198 { 1199 int i; 1200 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1201 char *isa_str = g_new(char, maxlen); 1202 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1203 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1204 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1205 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1206 } 1207 } 1208 *p = '\0'; 1209 if (!cpu->cfg.short_isa_string) { 1210 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1211 } 1212 return isa_str; 1213 } 1214 1215 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1216 { 1217 ObjectClass *class_a = (ObjectClass *)a; 1218 ObjectClass *class_b = (ObjectClass *)b; 1219 const char *name_a, *name_b; 1220 1221 name_a = object_class_get_name(class_a); 1222 name_b = object_class_get_name(class_b); 1223 return strcmp(name_a, name_b); 1224 } 1225 1226 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1227 { 1228 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1229 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1230 1231 qemu_printf("%.*s\n", len, typename); 1232 } 1233 1234 void riscv_cpu_list(void) 1235 { 1236 GSList *list; 1237 1238 list = object_class_get_list(TYPE_RISCV_CPU, false); 1239 list = g_slist_sort(list, riscv_cpu_list_compare); 1240 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1241 g_slist_free(list); 1242 } 1243 1244 #define DEFINE_CPU(type_name, initfn) \ 1245 { \ 1246 .name = type_name, \ 1247 .parent = TYPE_RISCV_CPU, \ 1248 .instance_init = initfn \ 1249 } 1250 1251 static const TypeInfo riscv_cpu_type_infos[] = { 1252 { 1253 .name = TYPE_RISCV_CPU, 1254 .parent = TYPE_CPU, 1255 .instance_size = sizeof(RISCVCPU), 1256 .instance_align = __alignof__(RISCVCPU), 1257 .instance_init = riscv_cpu_init, 1258 .abstract = true, 1259 .class_size = sizeof(RISCVCPUClass), 1260 .class_init = riscv_cpu_class_init, 1261 }, 1262 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1263 #if defined(CONFIG_KVM) 1264 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1265 #endif 1266 #if defined(TARGET_RISCV32) 1267 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1268 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1269 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1270 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1271 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1272 #elif defined(TARGET_RISCV64) 1273 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1274 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1275 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1276 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1277 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1278 #endif 1279 }; 1280 1281 DEFINE_TYPES(riscv_cpu_type_infos) 1282