xref: /openbmc/qemu/target/riscv/cpu.c (revision 5d326db2)
1 /*
2  * QEMU RISC-V CPU
3  *
4  * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5  * Copyright (c) 2017-2018 SiFive, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify it
8  * under the terms and conditions of the GNU General Public License,
9  * version 2 or later, as published by the Free Software Foundation.
10  *
11  * This program is distributed in the hope it will be useful, but WITHOUT
12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
14  * more details.
15  *
16  * You should have received a copy of the GNU General Public License along with
17  * this program.  If not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/qemu-print.h"
22 #include "qemu/ctype.h"
23 #include "qemu/log.h"
24 #include "cpu.h"
25 #include "cpu_vendorid.h"
26 #include "pmu.h"
27 #include "internals.h"
28 #include "time_helper.h"
29 #include "exec/exec-all.h"
30 #include "qapi/error.h"
31 #include "qapi/visitor.h"
32 #include "qemu/error-report.h"
33 #include "hw/qdev-properties.h"
34 #include "migration/vmstate.h"
35 #include "fpu/softfloat-helpers.h"
36 #include "sysemu/kvm.h"
37 #include "kvm_riscv.h"
38 #include "tcg/tcg.h"
39 
40 /* RISC-V CPU definitions */
41 
42 #define RISCV_CPU_MARCHID   ((QEMU_VERSION_MAJOR << 16) | \
43                              (QEMU_VERSION_MINOR << 8)  | \
44                              (QEMU_VERSION_MICRO))
45 #define RISCV_CPU_MIMPID    RISCV_CPU_MARCHID
46 
47 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH";
48 
49 struct isa_ext_data {
50     const char *name;
51     int min_version;
52     int ext_enable_offset;
53 };
54 
55 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \
56     {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)}
57 
58 /*
59  * Here are the ordering rules of extension naming defined by RISC-V
60  * specification :
61  * 1. All extensions should be separated from other multi-letter extensions
62  *    by an underscore.
63  * 2. The first letter following the 'Z' conventionally indicates the most
64  *    closely related alphabetical extension category, IMAFDQLCBKJTPVH.
65  *    If multiple 'Z' extensions are named, they should be ordered first
66  *    by category, then alphabetically within a category.
67  * 3. Standard supervisor-level extensions (starts with 'S') should be
68  *    listed after standard unprivileged extensions.  If multiple
69  *    supervisor-level extensions are listed, they should be ordered
70  *    alphabetically.
71  * 4. Non-standard extensions (starts with 'X') must be listed after all
72  *    standard extensions. They must be separated from other multi-letter
73  *    extensions by an underscore.
74  *
75  * Single letter extensions are checked in riscv_cpu_validate_misa_priv()
76  * instead.
77  */
78 static const struct isa_ext_data isa_edata_arr[] = {
79     ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom),
80     ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz),
81     ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond),
82     ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr),
83     ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei),
84     ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause),
85     ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs),
86     ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh),
87     ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin),
88     ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx),
89     ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx),
90     ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca),
91     ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb),
92     ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf),
93     ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd),
94     ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce),
95     ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp),
96     ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt),
97     ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba),
98     ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb),
99     ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc),
100     ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb),
101     ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc),
102     ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx),
103     ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs),
104     ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk),
105     ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn),
106     ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd),
107     ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne),
108     ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh),
109     ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr),
110     ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks),
111     ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed),
112     ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh),
113     ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt),
114     ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f),
115     ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f),
116     ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d),
117     ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh),
118     ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin),
119     ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx),
120     ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin),
121     ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia),
122     ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen),
123     ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia),
124     ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf),
125     ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc),
126     ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu),
127     ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval),
128     ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot),
129     ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt),
130     ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba),
131     ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb),
132     ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs),
133     ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo),
134     ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov),
135     ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx),
136     ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv),
137     ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac),
138     ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx),
139     ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair),
140     ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync),
141     ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
142 };
143 
144 static bool isa_ext_is_enabled(RISCVCPU *cpu,
145                                const struct isa_ext_data *edata)
146 {
147     bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
148 
149     return *ext_enabled;
150 }
151 
152 static void isa_ext_update_enabled(RISCVCPU *cpu,
153                                    const struct isa_ext_data *edata, bool en)
154 {
155     bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset;
156 
157     *ext_enabled = en;
158 }
159 
160 const char * const riscv_int_regnames[] = {
161     "x0/zero", "x1/ra",  "x2/sp",  "x3/gp",  "x4/tp",  "x5/t0",   "x6/t1",
162     "x7/t2",   "x8/s0",  "x9/s1",  "x10/a0", "x11/a1", "x12/a2",  "x13/a3",
163     "x14/a4",  "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3",  "x20/s4",
164     "x21/s5",  "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11",
165     "x28/t3",  "x29/t4", "x30/t5", "x31/t6"
166 };
167 
168 const char * const riscv_int_regnamesh[] = {
169     "x0h/zeroh", "x1h/rah",  "x2h/sph",   "x3h/gph",   "x4h/tph",  "x5h/t0h",
170     "x6h/t1h",   "x7h/t2h",  "x8h/s0h",   "x9h/s1h",   "x10h/a0h", "x11h/a1h",
171     "x12h/a2h",  "x13h/a3h", "x14h/a4h",  "x15h/a5h",  "x16h/a6h", "x17h/a7h",
172     "x18h/s2h",  "x19h/s3h", "x20h/s4h",  "x21h/s5h",  "x22h/s6h", "x23h/s7h",
173     "x24h/s8h",  "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h",
174     "x30h/t5h",  "x31h/t6h"
175 };
176 
177 const char * const riscv_fpr_regnames[] = {
178     "f0/ft0",   "f1/ft1",  "f2/ft2",   "f3/ft3",   "f4/ft4",  "f5/ft5",
179     "f6/ft6",   "f7/ft7",  "f8/fs0",   "f9/fs1",   "f10/fa0", "f11/fa1",
180     "f12/fa2",  "f13/fa3", "f14/fa4",  "f15/fa5",  "f16/fa6", "f17/fa7",
181     "f18/fs2",  "f19/fs3", "f20/fs4",  "f21/fs5",  "f22/fs6", "f23/fs7",
182     "f24/fs8",  "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9",
183     "f30/ft10", "f31/ft11"
184 };
185 
186 static const char * const riscv_excp_names[] = {
187     "misaligned_fetch",
188     "fault_fetch",
189     "illegal_instruction",
190     "breakpoint",
191     "misaligned_load",
192     "fault_load",
193     "misaligned_store",
194     "fault_store",
195     "user_ecall",
196     "supervisor_ecall",
197     "hypervisor_ecall",
198     "machine_ecall",
199     "exec_page_fault",
200     "load_page_fault",
201     "reserved",
202     "store_page_fault",
203     "reserved",
204     "reserved",
205     "reserved",
206     "reserved",
207     "guest_exec_page_fault",
208     "guest_load_page_fault",
209     "reserved",
210     "guest_store_page_fault",
211 };
212 
213 static const char * const riscv_intr_names[] = {
214     "u_software",
215     "s_software",
216     "vs_software",
217     "m_software",
218     "u_timer",
219     "s_timer",
220     "vs_timer",
221     "m_timer",
222     "u_external",
223     "s_external",
224     "vs_external",
225     "m_external",
226     "reserved",
227     "reserved",
228     "reserved",
229     "reserved"
230 };
231 
232 static void riscv_cpu_add_user_properties(Object *obj);
233 
234 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async)
235 {
236     if (async) {
237         return (cause < ARRAY_SIZE(riscv_intr_names)) ?
238                riscv_intr_names[cause] : "(unknown)";
239     } else {
240         return (cause < ARRAY_SIZE(riscv_excp_names)) ?
241                riscv_excp_names[cause] : "(unknown)";
242     }
243 }
244 
245 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext)
246 {
247     env->misa_mxl_max = env->misa_mxl = mxl;
248     env->misa_ext_mask = env->misa_ext = ext;
249 }
250 
251 #ifndef CONFIG_USER_ONLY
252 static uint8_t satp_mode_from_str(const char *satp_mode_str)
253 {
254     if (!strncmp(satp_mode_str, "mbare", 5)) {
255         return VM_1_10_MBARE;
256     }
257 
258     if (!strncmp(satp_mode_str, "sv32", 4)) {
259         return VM_1_10_SV32;
260     }
261 
262     if (!strncmp(satp_mode_str, "sv39", 4)) {
263         return VM_1_10_SV39;
264     }
265 
266     if (!strncmp(satp_mode_str, "sv48", 4)) {
267         return VM_1_10_SV48;
268     }
269 
270     if (!strncmp(satp_mode_str, "sv57", 4)) {
271         return VM_1_10_SV57;
272     }
273 
274     if (!strncmp(satp_mode_str, "sv64", 4)) {
275         return VM_1_10_SV64;
276     }
277 
278     g_assert_not_reached();
279 }
280 
281 uint8_t satp_mode_max_from_map(uint32_t map)
282 {
283     /* map here has at least one bit set, so no problem with clz */
284     return 31 - __builtin_clz(map);
285 }
286 
287 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit)
288 {
289     if (is_32_bit) {
290         switch (satp_mode) {
291         case VM_1_10_SV32:
292             return "sv32";
293         case VM_1_10_MBARE:
294             return "none";
295         }
296     } else {
297         switch (satp_mode) {
298         case VM_1_10_SV64:
299             return "sv64";
300         case VM_1_10_SV57:
301             return "sv57";
302         case VM_1_10_SV48:
303             return "sv48";
304         case VM_1_10_SV39:
305             return "sv39";
306         case VM_1_10_MBARE:
307             return "none";
308         }
309     }
310 
311     g_assert_not_reached();
312 }
313 
314 static void set_satp_mode_max_supported(RISCVCPU *cpu,
315                                         uint8_t satp_mode)
316 {
317     bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
318     const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64;
319 
320     for (int i = 0; i <= satp_mode; ++i) {
321         if (valid_vm[i]) {
322             cpu->cfg.satp_mode.supported |= (1 << i);
323         }
324     }
325 }
326 
327 /* Set the satp mode to the max supported */
328 static void set_satp_mode_default_map(RISCVCPU *cpu)
329 {
330     cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported;
331 }
332 #endif
333 
334 static void riscv_any_cpu_init(Object *obj)
335 {
336     RISCVCPU *cpu = RISCV_CPU(obj);
337     CPURISCVState *env = &cpu->env;
338 #if defined(TARGET_RISCV32)
339     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
340 #elif defined(TARGET_RISCV64)
341     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU);
342 #endif
343 
344 #ifndef CONFIG_USER_ONLY
345     set_satp_mode_max_supported(RISCV_CPU(obj),
346         riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ?
347         VM_1_10_SV32 : VM_1_10_SV57);
348 #endif
349 
350     env->priv_ver = PRIV_VERSION_LATEST;
351 
352     /* inherited from parent obj via riscv_cpu_init() */
353     cpu->cfg.ext_ifencei = true;
354     cpu->cfg.ext_icsr = true;
355     cpu->cfg.mmu = true;
356     cpu->cfg.pmp = true;
357 }
358 
359 #if defined(TARGET_RISCV64)
360 static void rv64_base_cpu_init(Object *obj)
361 {
362     CPURISCVState *env = &RISCV_CPU(obj)->env;
363     /* We set this in the realise function */
364     set_misa(env, MXL_RV64, 0);
365     riscv_cpu_add_user_properties(obj);
366     /* Set latest version of privileged specification */
367     env->priv_ver = PRIV_VERSION_LATEST;
368 #ifndef CONFIG_USER_ONLY
369     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
370 #endif
371 }
372 
373 static void rv64_sifive_u_cpu_init(Object *obj)
374 {
375     RISCVCPU *cpu = RISCV_CPU(obj);
376     CPURISCVState *env = &cpu->env;
377     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
378     env->priv_ver = PRIV_VERSION_1_10_0;
379 #ifndef CONFIG_USER_ONLY
380     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39);
381 #endif
382 
383     /* inherited from parent obj via riscv_cpu_init() */
384     cpu->cfg.ext_ifencei = true;
385     cpu->cfg.ext_icsr = true;
386     cpu->cfg.mmu = true;
387     cpu->cfg.pmp = true;
388 }
389 
390 static void rv64_sifive_e_cpu_init(Object *obj)
391 {
392     CPURISCVState *env = &RISCV_CPU(obj)->env;
393     RISCVCPU *cpu = RISCV_CPU(obj);
394 
395     set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU);
396     env->priv_ver = PRIV_VERSION_1_10_0;
397 #ifndef CONFIG_USER_ONLY
398     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
399 #endif
400 
401     /* inherited from parent obj via riscv_cpu_init() */
402     cpu->cfg.ext_ifencei = true;
403     cpu->cfg.ext_icsr = true;
404     cpu->cfg.pmp = true;
405 }
406 
407 static void rv64_thead_c906_cpu_init(Object *obj)
408 {
409     CPURISCVState *env = &RISCV_CPU(obj)->env;
410     RISCVCPU *cpu = RISCV_CPU(obj);
411 
412     set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU);
413     env->priv_ver = PRIV_VERSION_1_11_0;
414 
415     cpu->cfg.ext_zfh = true;
416     cpu->cfg.mmu = true;
417     cpu->cfg.ext_xtheadba = true;
418     cpu->cfg.ext_xtheadbb = true;
419     cpu->cfg.ext_xtheadbs = true;
420     cpu->cfg.ext_xtheadcmo = true;
421     cpu->cfg.ext_xtheadcondmov = true;
422     cpu->cfg.ext_xtheadfmemidx = true;
423     cpu->cfg.ext_xtheadmac = true;
424     cpu->cfg.ext_xtheadmemidx = true;
425     cpu->cfg.ext_xtheadmempair = true;
426     cpu->cfg.ext_xtheadsync = true;
427 
428     cpu->cfg.mvendorid = THEAD_VENDOR_ID;
429 #ifndef CONFIG_USER_ONLY
430     set_satp_mode_max_supported(cpu, VM_1_10_SV39);
431 #endif
432 
433     /* inherited from parent obj via riscv_cpu_init() */
434     cpu->cfg.pmp = true;
435 }
436 
437 static void rv64_veyron_v1_cpu_init(Object *obj)
438 {
439     CPURISCVState *env = &RISCV_CPU(obj)->env;
440     RISCVCPU *cpu = RISCV_CPU(obj);
441 
442     set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH);
443     env->priv_ver = PRIV_VERSION_1_12_0;
444 
445     /* Enable ISA extensions */
446     cpu->cfg.mmu = true;
447     cpu->cfg.ext_icbom = true;
448     cpu->cfg.cbom_blocksize = 64;
449     cpu->cfg.cboz_blocksize = 64;
450     cpu->cfg.ext_icboz = true;
451     cpu->cfg.ext_smaia = true;
452     cpu->cfg.ext_ssaia = true;
453     cpu->cfg.ext_sscofpmf = true;
454     cpu->cfg.ext_sstc = true;
455     cpu->cfg.ext_svinval = true;
456     cpu->cfg.ext_svnapot = true;
457     cpu->cfg.ext_svpbmt = true;
458     cpu->cfg.ext_smstateen = true;
459     cpu->cfg.ext_zba = true;
460     cpu->cfg.ext_zbb = true;
461     cpu->cfg.ext_zbc = true;
462     cpu->cfg.ext_zbs = true;
463     cpu->cfg.ext_XVentanaCondOps = true;
464 
465     cpu->cfg.mvendorid = VEYRON_V1_MVENDORID;
466     cpu->cfg.marchid = VEYRON_V1_MARCHID;
467     cpu->cfg.mimpid = VEYRON_V1_MIMPID;
468 
469 #ifndef CONFIG_USER_ONLY
470     set_satp_mode_max_supported(cpu, VM_1_10_SV48);
471 #endif
472 }
473 
474 static void rv128_base_cpu_init(Object *obj)
475 {
476     if (qemu_tcg_mttcg_enabled()) {
477         /* Missing 128-bit aligned atomics */
478         error_report("128-bit RISC-V currently does not work with Multi "
479                      "Threaded TCG. Please use: -accel tcg,thread=single");
480         exit(EXIT_FAILURE);
481     }
482     CPURISCVState *env = &RISCV_CPU(obj)->env;
483     /* We set this in the realise function */
484     set_misa(env, MXL_RV128, 0);
485     riscv_cpu_add_user_properties(obj);
486     /* Set latest version of privileged specification */
487     env->priv_ver = PRIV_VERSION_LATEST;
488 #ifndef CONFIG_USER_ONLY
489     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57);
490 #endif
491 }
492 #else
493 static void rv32_base_cpu_init(Object *obj)
494 {
495     CPURISCVState *env = &RISCV_CPU(obj)->env;
496     /* We set this in the realise function */
497     set_misa(env, MXL_RV32, 0);
498     riscv_cpu_add_user_properties(obj);
499     /* Set latest version of privileged specification */
500     env->priv_ver = PRIV_VERSION_LATEST;
501 #ifndef CONFIG_USER_ONLY
502     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
503 #endif
504 }
505 
506 static void rv32_sifive_u_cpu_init(Object *obj)
507 {
508     RISCVCPU *cpu = RISCV_CPU(obj);
509     CPURISCVState *env = &cpu->env;
510     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
511     env->priv_ver = PRIV_VERSION_1_10_0;
512 #ifndef CONFIG_USER_ONLY
513     set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32);
514 #endif
515 
516     /* inherited from parent obj via riscv_cpu_init() */
517     cpu->cfg.ext_ifencei = true;
518     cpu->cfg.ext_icsr = true;
519     cpu->cfg.mmu = true;
520     cpu->cfg.pmp = true;
521 }
522 
523 static void rv32_sifive_e_cpu_init(Object *obj)
524 {
525     CPURISCVState *env = &RISCV_CPU(obj)->env;
526     RISCVCPU *cpu = RISCV_CPU(obj);
527 
528     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU);
529     env->priv_ver = PRIV_VERSION_1_10_0;
530 #ifndef CONFIG_USER_ONLY
531     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
532 #endif
533 
534     /* inherited from parent obj via riscv_cpu_init() */
535     cpu->cfg.ext_ifencei = true;
536     cpu->cfg.ext_icsr = true;
537     cpu->cfg.pmp = true;
538 }
539 
540 static void rv32_ibex_cpu_init(Object *obj)
541 {
542     CPURISCVState *env = &RISCV_CPU(obj)->env;
543     RISCVCPU *cpu = RISCV_CPU(obj);
544 
545     set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU);
546     env->priv_ver = PRIV_VERSION_1_11_0;
547 #ifndef CONFIG_USER_ONLY
548     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
549 #endif
550     cpu->cfg.epmp = true;
551 
552     /* inherited from parent obj via riscv_cpu_init() */
553     cpu->cfg.ext_ifencei = true;
554     cpu->cfg.ext_icsr = true;
555     cpu->cfg.pmp = true;
556 }
557 
558 static void rv32_imafcu_nommu_cpu_init(Object *obj)
559 {
560     CPURISCVState *env = &RISCV_CPU(obj)->env;
561     RISCVCPU *cpu = RISCV_CPU(obj);
562 
563     set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU);
564     env->priv_ver = PRIV_VERSION_1_10_0;
565 #ifndef CONFIG_USER_ONLY
566     set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
567 #endif
568 
569     /* inherited from parent obj via riscv_cpu_init() */
570     cpu->cfg.ext_ifencei = true;
571     cpu->cfg.ext_icsr = true;
572     cpu->cfg.pmp = true;
573 }
574 #endif
575 
576 #if defined(CONFIG_KVM)
577 static void riscv_host_cpu_init(Object *obj)
578 {
579     CPURISCVState *env = &RISCV_CPU(obj)->env;
580 #if defined(TARGET_RISCV32)
581     set_misa(env, MXL_RV32, 0);
582 #elif defined(TARGET_RISCV64)
583     set_misa(env, MXL_RV64, 0);
584 #endif
585     riscv_cpu_add_user_properties(obj);
586 }
587 #endif /* CONFIG_KVM */
588 
589 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model)
590 {
591     ObjectClass *oc;
592     char *typename;
593     char **cpuname;
594 
595     cpuname = g_strsplit(cpu_model, ",", 1);
596     typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]);
597     oc = object_class_by_name(typename);
598     g_strfreev(cpuname);
599     g_free(typename);
600     if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) ||
601         object_class_is_abstract(oc)) {
602         return NULL;
603     }
604     return oc;
605 }
606 
607 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags)
608 {
609     RISCVCPU *cpu = RISCV_CPU(cs);
610     CPURISCVState *env = &cpu->env;
611     int i;
612 
613 #if !defined(CONFIG_USER_ONLY)
614     if (riscv_has_ext(env, RVH)) {
615         qemu_fprintf(f, " %s %d\n", "V      =  ", env->virt_enabled);
616     }
617 #endif
618     qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc      ", env->pc);
619 #ifndef CONFIG_USER_ONLY
620     {
621         static const int dump_csrs[] = {
622             CSR_MHARTID,
623             CSR_MSTATUS,
624             CSR_MSTATUSH,
625             /*
626              * CSR_SSTATUS is intentionally omitted here as its value
627              * can be figured out by looking at CSR_MSTATUS
628              */
629             CSR_HSTATUS,
630             CSR_VSSTATUS,
631             CSR_MIP,
632             CSR_MIE,
633             CSR_MIDELEG,
634             CSR_HIDELEG,
635             CSR_MEDELEG,
636             CSR_HEDELEG,
637             CSR_MTVEC,
638             CSR_STVEC,
639             CSR_VSTVEC,
640             CSR_MEPC,
641             CSR_SEPC,
642             CSR_VSEPC,
643             CSR_MCAUSE,
644             CSR_SCAUSE,
645             CSR_VSCAUSE,
646             CSR_MTVAL,
647             CSR_STVAL,
648             CSR_HTVAL,
649             CSR_MTVAL2,
650             CSR_MSCRATCH,
651             CSR_SSCRATCH,
652             CSR_SATP,
653             CSR_MMTE,
654             CSR_UPMBASE,
655             CSR_UPMMASK,
656             CSR_SPMBASE,
657             CSR_SPMMASK,
658             CSR_MPMBASE,
659             CSR_MPMMASK,
660         };
661 
662         for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) {
663             int csrno = dump_csrs[i];
664             target_ulong val = 0;
665             RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0);
666 
667             /*
668              * Rely on the smode, hmode, etc, predicates within csr.c
669              * to do the filtering of the registers that are present.
670              */
671             if (res == RISCV_EXCP_NONE) {
672                 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n",
673                              csr_ops[csrno].name, val);
674             }
675         }
676     }
677 #endif
678 
679     for (i = 0; i < 32; i++) {
680         qemu_fprintf(f, " %-8s " TARGET_FMT_lx,
681                      riscv_int_regnames[i], env->gpr[i]);
682         if ((i & 3) == 3) {
683             qemu_fprintf(f, "\n");
684         }
685     }
686     if (flags & CPU_DUMP_FPU) {
687         for (i = 0; i < 32; i++) {
688             qemu_fprintf(f, " %-8s %016" PRIx64,
689                          riscv_fpr_regnames[i], env->fpr[i]);
690             if ((i & 3) == 3) {
691                 qemu_fprintf(f, "\n");
692             }
693         }
694     }
695 }
696 
697 static void riscv_cpu_set_pc(CPUState *cs, vaddr value)
698 {
699     RISCVCPU *cpu = RISCV_CPU(cs);
700     CPURISCVState *env = &cpu->env;
701 
702     if (env->xl == MXL_RV32) {
703         env->pc = (int32_t)value;
704     } else {
705         env->pc = value;
706     }
707 }
708 
709 static vaddr riscv_cpu_get_pc(CPUState *cs)
710 {
711     RISCVCPU *cpu = RISCV_CPU(cs);
712     CPURISCVState *env = &cpu->env;
713 
714     /* Match cpu_get_tb_cpu_state. */
715     if (env->xl == MXL_RV32) {
716         return env->pc & UINT32_MAX;
717     }
718     return env->pc;
719 }
720 
721 static void riscv_cpu_synchronize_from_tb(CPUState *cs,
722                                           const TranslationBlock *tb)
723 {
724     if (!(tb_cflags(tb) & CF_PCREL)) {
725         RISCVCPU *cpu = RISCV_CPU(cs);
726         CPURISCVState *env = &cpu->env;
727         RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
728 
729         tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL));
730 
731         if (xl == MXL_RV32) {
732             env->pc = (int32_t) tb->pc;
733         } else {
734             env->pc = tb->pc;
735         }
736     }
737 }
738 
739 static bool riscv_cpu_has_work(CPUState *cs)
740 {
741 #ifndef CONFIG_USER_ONLY
742     RISCVCPU *cpu = RISCV_CPU(cs);
743     CPURISCVState *env = &cpu->env;
744     /*
745      * Definition of the WFI instruction requires it to ignore the privilege
746      * mode and delegation registers, but respect individual enables
747      */
748     return riscv_cpu_all_pending(env) != 0;
749 #else
750     return true;
751 #endif
752 }
753 
754 static void riscv_restore_state_to_opc(CPUState *cs,
755                                        const TranslationBlock *tb,
756                                        const uint64_t *data)
757 {
758     RISCVCPU *cpu = RISCV_CPU(cs);
759     CPURISCVState *env = &cpu->env;
760     RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL);
761     target_ulong pc;
762 
763     if (tb_cflags(tb) & CF_PCREL) {
764         pc = (env->pc & TARGET_PAGE_MASK) | data[0];
765     } else {
766         pc = data[0];
767     }
768 
769     if (xl == MXL_RV32) {
770         env->pc = (int32_t)pc;
771     } else {
772         env->pc = pc;
773     }
774     env->bins = data[1];
775 }
776 
777 static void riscv_cpu_reset_hold(Object *obj)
778 {
779 #ifndef CONFIG_USER_ONLY
780     uint8_t iprio;
781     int i, irq, rdzero;
782 #endif
783     CPUState *cs = CPU(obj);
784     RISCVCPU *cpu = RISCV_CPU(cs);
785     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
786     CPURISCVState *env = &cpu->env;
787 
788     if (mcc->parent_phases.hold) {
789         mcc->parent_phases.hold(obj);
790     }
791 #ifndef CONFIG_USER_ONLY
792     env->misa_mxl = env->misa_mxl_max;
793     env->priv = PRV_M;
794     env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV);
795     if (env->misa_mxl > MXL_RV32) {
796         /*
797          * The reset status of SXL/UXL is undefined, but mstatus is WARL
798          * and we must ensure that the value after init is valid for read.
799          */
800         env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
801         env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
802         if (riscv_has_ext(env, RVH)) {
803             env->vsstatus = set_field(env->vsstatus,
804                                       MSTATUS64_SXL, env->misa_mxl);
805             env->vsstatus = set_field(env->vsstatus,
806                                       MSTATUS64_UXL, env->misa_mxl);
807             env->mstatus_hs = set_field(env->mstatus_hs,
808                                         MSTATUS64_SXL, env->misa_mxl);
809             env->mstatus_hs = set_field(env->mstatus_hs,
810                                         MSTATUS64_UXL, env->misa_mxl);
811         }
812     }
813     env->mcause = 0;
814     env->miclaim = MIP_SGEIP;
815     env->pc = env->resetvec;
816     env->bins = 0;
817     env->two_stage_lookup = false;
818 
819     env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) |
820                    (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0);
821     env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) |
822                    (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0);
823 
824     /* Initialized default priorities of local interrupts. */
825     for (i = 0; i < ARRAY_SIZE(env->miprio); i++) {
826         iprio = riscv_cpu_default_priority(i);
827         env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio;
828         env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio;
829         env->hviprio[i] = 0;
830     }
831     i = 0;
832     while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) {
833         if (!rdzero) {
834             env->hviprio[irq] = env->miprio[irq];
835         }
836         i++;
837     }
838     /* mmte is supposed to have pm.current hardwired to 1 */
839     env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT);
840 #endif
841     env->xl = riscv_cpu_mxl(env);
842     riscv_cpu_update_mask(env);
843     cs->exception_index = RISCV_EXCP_NONE;
844     env->load_res = -1;
845     set_default_nan_mode(1, &env->fp_status);
846 
847 #ifndef CONFIG_USER_ONLY
848     if (cpu->cfg.debug) {
849         riscv_trigger_init(env);
850     }
851 
852     if (kvm_enabled()) {
853         kvm_riscv_reset_vcpu(cpu);
854     }
855 #endif
856 }
857 
858 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info)
859 {
860     RISCVCPU *cpu = RISCV_CPU(s);
861     CPURISCVState *env = &cpu->env;
862     info->target_info = &cpu->cfg;
863 
864     switch (env->xl) {
865     case MXL_RV32:
866         info->print_insn = print_insn_riscv32;
867         break;
868     case MXL_RV64:
869         info->print_insn = print_insn_riscv64;
870         break;
871     case MXL_RV128:
872         info->print_insn = print_insn_riscv128;
873         break;
874     default:
875         g_assert_not_reached();
876     }
877 }
878 
879 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg,
880                                  Error **errp)
881 {
882     int vext_version = VEXT_VERSION_1_00_0;
883 
884     if (!is_power_of_2(cfg->vlen)) {
885         error_setg(errp, "Vector extension VLEN must be power of 2");
886         return;
887     }
888     if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) {
889         error_setg(errp,
890                    "Vector extension implementation only supports VLEN "
891                    "in the range [128, %d]", RV_VLEN_MAX);
892         return;
893     }
894     if (!is_power_of_2(cfg->elen)) {
895         error_setg(errp, "Vector extension ELEN must be power of 2");
896         return;
897     }
898     if (cfg->elen > 64 || cfg->elen < 8) {
899         error_setg(errp,
900                    "Vector extension implementation only supports ELEN "
901                    "in the range [8, 64]");
902         return;
903     }
904     if (cfg->vext_spec) {
905         if (!g_strcmp0(cfg->vext_spec, "v1.0")) {
906             vext_version = VEXT_VERSION_1_00_0;
907         } else {
908             error_setg(errp, "Unsupported vector spec version '%s'",
909                        cfg->vext_spec);
910             return;
911         }
912     } else {
913         qemu_log("vector version is not specified, "
914                  "use the default value v1.0\n");
915     }
916     env->vext_ver = vext_version;
917 }
918 
919 static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp)
920 {
921     CPURISCVState *env = &cpu->env;
922     int priv_version = -1;
923 
924     if (cpu->cfg.priv_spec) {
925         if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) {
926             priv_version = PRIV_VERSION_1_12_0;
927         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) {
928             priv_version = PRIV_VERSION_1_11_0;
929         } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) {
930             priv_version = PRIV_VERSION_1_10_0;
931         } else {
932             error_setg(errp,
933                        "Unsupported privilege spec version '%s'",
934                        cpu->cfg.priv_spec);
935             return;
936         }
937 
938         env->priv_ver = priv_version;
939     }
940 }
941 
942 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu)
943 {
944     CPURISCVState *env = &cpu->env;
945     int i;
946 
947     /* Force disable extensions if priv spec version does not match */
948     for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
949         if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) &&
950             (env->priv_ver < isa_edata_arr[i].min_version)) {
951             isa_ext_update_enabled(cpu, &isa_edata_arr[i], false);
952 #ifndef CONFIG_USER_ONLY
953             warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx
954                         " because privilege spec version does not match",
955                         isa_edata_arr[i].name, env->mhartid);
956 #else
957             warn_report("disabling %s extension because "
958                         "privilege spec version does not match",
959                         isa_edata_arr[i].name);
960 #endif
961         }
962     }
963 }
964 
965 static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp)
966 {
967     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu);
968     CPUClass *cc = CPU_CLASS(mcc);
969     CPURISCVState *env = &cpu->env;
970 
971     /* Validate that MISA_MXL is set properly. */
972     switch (env->misa_mxl_max) {
973 #ifdef TARGET_RISCV64
974     case MXL_RV64:
975     case MXL_RV128:
976         cc->gdb_core_xml_file = "riscv-64bit-cpu.xml";
977         break;
978 #endif
979     case MXL_RV32:
980         cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
981         break;
982     default:
983         g_assert_not_reached();
984     }
985 
986     if (env->misa_mxl_max != env->misa_mxl) {
987         error_setg(errp, "misa_mxl_max must be equal to misa_mxl");
988         return;
989     }
990 }
991 
992 /*
993  * Check consistency between chosen extensions while setting
994  * cpu->cfg accordingly.
995  */
996 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp)
997 {
998     CPURISCVState *env = &cpu->env;
999     Error *local_err = NULL;
1000 
1001     /* Do some ISA extension error checking */
1002     if (riscv_has_ext(env, RVG) &&
1003         !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) &&
1004           riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) &&
1005           riscv_has_ext(env, RVD) &&
1006           cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) {
1007         warn_report("Setting G will also set IMAFD_Zicsr_Zifencei");
1008         cpu->cfg.ext_icsr = true;
1009         cpu->cfg.ext_ifencei = true;
1010 
1011         env->misa_ext |= RVI | RVM | RVA | RVF | RVD;
1012         env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD;
1013     }
1014 
1015     if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) {
1016         error_setg(errp,
1017                    "I and E extensions are incompatible");
1018         return;
1019     }
1020 
1021     if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) {
1022         error_setg(errp,
1023                    "Either I or E extension must be set");
1024         return;
1025     }
1026 
1027     if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) {
1028         error_setg(errp,
1029                    "Setting S extension without U extension is illegal");
1030         return;
1031     }
1032 
1033     if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) {
1034         error_setg(errp,
1035                    "H depends on an I base integer ISA with 32 x registers");
1036         return;
1037     }
1038 
1039     if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) {
1040         error_setg(errp, "H extension implicitly requires S-mode");
1041         return;
1042     }
1043 
1044     if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) {
1045         error_setg(errp, "F extension requires Zicsr");
1046         return;
1047     }
1048 
1049     if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) {
1050         error_setg(errp, "Zawrs extension requires A extension");
1051         return;
1052     }
1053 
1054     if (cpu->cfg.ext_zfh) {
1055         cpu->cfg.ext_zfhmin = true;
1056     }
1057 
1058     if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) {
1059         error_setg(errp, "Zfh/Zfhmin extensions require F extension");
1060         return;
1061     }
1062 
1063     if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) {
1064         error_setg(errp, "D extension requires F extension");
1065         return;
1066     }
1067 
1068     if (riscv_has_ext(env, RVV)) {
1069         riscv_cpu_validate_v(env, &cpu->cfg, &local_err);
1070         if (local_err != NULL) {
1071             error_propagate(errp, local_err);
1072             return;
1073         }
1074 
1075         /* The V vector extension depends on the Zve64d extension */
1076         cpu->cfg.ext_zve64d = true;
1077     }
1078 
1079     /* The Zve64d extension depends on the Zve64f extension */
1080     if (cpu->cfg.ext_zve64d) {
1081         cpu->cfg.ext_zve64f = true;
1082     }
1083 
1084     /* The Zve64f extension depends on the Zve32f extension */
1085     if (cpu->cfg.ext_zve64f) {
1086         cpu->cfg.ext_zve32f = true;
1087     }
1088 
1089     if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) {
1090         error_setg(errp, "Zve64d/V extensions require D extension");
1091         return;
1092     }
1093 
1094     if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) {
1095         error_setg(errp, "Zve32f/Zve64f extensions require F extension");
1096         return;
1097     }
1098 
1099     if (cpu->cfg.ext_zvfh) {
1100         cpu->cfg.ext_zvfhmin = true;
1101     }
1102 
1103     if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) {
1104         error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension");
1105         return;
1106     }
1107 
1108     if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) {
1109         error_setg(errp, "Zvfh extensions requires Zfhmin extension");
1110         return;
1111     }
1112 
1113     /* Set the ISA extensions, checks should have happened above */
1114     if (cpu->cfg.ext_zhinx) {
1115         cpu->cfg.ext_zhinxmin = true;
1116     }
1117 
1118     if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) {
1119         error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx");
1120         return;
1121     }
1122 
1123     if (cpu->cfg.ext_zfinx) {
1124         if (!cpu->cfg.ext_icsr) {
1125             error_setg(errp, "Zfinx extension requires Zicsr");
1126             return;
1127         }
1128         if (riscv_has_ext(env, RVF)) {
1129             error_setg(errp,
1130                        "Zfinx cannot be supported together with F extension");
1131             return;
1132         }
1133     }
1134 
1135     if (cpu->cfg.ext_zce) {
1136         cpu->cfg.ext_zca = true;
1137         cpu->cfg.ext_zcb = true;
1138         cpu->cfg.ext_zcmp = true;
1139         cpu->cfg.ext_zcmt = true;
1140         if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
1141             cpu->cfg.ext_zcf = true;
1142         }
1143     }
1144 
1145     if (riscv_has_ext(env, RVC)) {
1146         cpu->cfg.ext_zca = true;
1147         if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) {
1148             cpu->cfg.ext_zcf = true;
1149         }
1150         if (riscv_has_ext(env, RVD)) {
1151             cpu->cfg.ext_zcd = true;
1152         }
1153     }
1154 
1155     if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) {
1156         error_setg(errp, "Zcf extension is only relevant to RV32");
1157         return;
1158     }
1159 
1160     if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) {
1161         error_setg(errp, "Zcf extension requires F extension");
1162         return;
1163     }
1164 
1165     if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) {
1166         error_setg(errp, "Zcd extension requires D extension");
1167         return;
1168     }
1169 
1170     if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb ||
1171          cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) {
1172         error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca "
1173                          "extension");
1174         return;
1175     }
1176 
1177     if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) {
1178         error_setg(errp, "Zcmp/Zcmt extensions are incompatible with "
1179                          "Zcd extension");
1180         return;
1181     }
1182 
1183     if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) {
1184         error_setg(errp, "Zcmt extension requires Zicsr extension");
1185         return;
1186     }
1187 
1188     if (cpu->cfg.ext_zk) {
1189         cpu->cfg.ext_zkn = true;
1190         cpu->cfg.ext_zkr = true;
1191         cpu->cfg.ext_zkt = true;
1192     }
1193 
1194     if (cpu->cfg.ext_zkn) {
1195         cpu->cfg.ext_zbkb = true;
1196         cpu->cfg.ext_zbkc = true;
1197         cpu->cfg.ext_zbkx = true;
1198         cpu->cfg.ext_zkne = true;
1199         cpu->cfg.ext_zknd = true;
1200         cpu->cfg.ext_zknh = true;
1201     }
1202 
1203     if (cpu->cfg.ext_zks) {
1204         cpu->cfg.ext_zbkb = true;
1205         cpu->cfg.ext_zbkc = true;
1206         cpu->cfg.ext_zbkx = true;
1207         cpu->cfg.ext_zksed = true;
1208         cpu->cfg.ext_zksh = true;
1209     }
1210 
1211     /*
1212      * Disable isa extensions based on priv spec after we
1213      * validated and set everything we need.
1214      */
1215     riscv_cpu_disable_priv_spec_isa_exts(cpu);
1216 }
1217 
1218 #ifndef CONFIG_USER_ONLY
1219 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp)
1220 {
1221     bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32;
1222     uint8_t satp_mode_map_max;
1223     uint8_t satp_mode_supported_max =
1224                         satp_mode_max_from_map(cpu->cfg.satp_mode.supported);
1225 
1226     if (cpu->cfg.satp_mode.map == 0) {
1227         if (cpu->cfg.satp_mode.init == 0) {
1228             /* If unset by the user, we fallback to the default satp mode. */
1229             set_satp_mode_default_map(cpu);
1230         } else {
1231             /*
1232              * Find the lowest level that was disabled and then enable the
1233              * first valid level below which can be found in
1234              * valid_vm_1_10_32/64.
1235              */
1236             for (int i = 1; i < 16; ++i) {
1237                 if ((cpu->cfg.satp_mode.init & (1 << i)) &&
1238                     (cpu->cfg.satp_mode.supported & (1 << i))) {
1239                     for (int j = i - 1; j >= 0; --j) {
1240                         if (cpu->cfg.satp_mode.supported & (1 << j)) {
1241                             cpu->cfg.satp_mode.map |= (1 << j);
1242                             break;
1243                         }
1244                     }
1245                     break;
1246                 }
1247             }
1248         }
1249     }
1250 
1251     satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map);
1252 
1253     /* Make sure the user asked for a supported configuration (HW and qemu) */
1254     if (satp_mode_map_max > satp_mode_supported_max) {
1255         error_setg(errp, "satp_mode %s is higher than hw max capability %s",
1256                    satp_mode_str(satp_mode_map_max, rv32),
1257                    satp_mode_str(satp_mode_supported_max, rv32));
1258         return;
1259     }
1260 
1261     /*
1262      * Make sure the user did not ask for an invalid configuration as per
1263      * the specification.
1264      */
1265     if (!rv32) {
1266         for (int i = satp_mode_map_max - 1; i >= 0; --i) {
1267             if (!(cpu->cfg.satp_mode.map & (1 << i)) &&
1268                 (cpu->cfg.satp_mode.init & (1 << i)) &&
1269                 (cpu->cfg.satp_mode.supported & (1 << i))) {
1270                 error_setg(errp, "cannot disable %s satp mode if %s "
1271                            "is enabled", satp_mode_str(i, false),
1272                            satp_mode_str(satp_mode_map_max, false));
1273                 return;
1274             }
1275         }
1276     }
1277 
1278     /* Finally expand the map so that all valid modes are set */
1279     for (int i = satp_mode_map_max - 1; i >= 0; --i) {
1280         if (cpu->cfg.satp_mode.supported & (1 << i)) {
1281             cpu->cfg.satp_mode.map |= (1 << i);
1282         }
1283     }
1284 }
1285 #endif
1286 
1287 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp)
1288 {
1289 #ifndef CONFIG_USER_ONLY
1290     Error *local_err = NULL;
1291 
1292     riscv_cpu_satp_mode_finalize(cpu, &local_err);
1293     if (local_err != NULL) {
1294         error_propagate(errp, local_err);
1295         return;
1296     }
1297 #endif
1298 }
1299 
1300 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp)
1301 {
1302     if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) {
1303         error_setg(errp, "H extension requires priv spec 1.12.0");
1304         return;
1305     }
1306 }
1307 
1308 static void riscv_cpu_realize(DeviceState *dev, Error **errp)
1309 {
1310     CPUState *cs = CPU(dev);
1311     RISCVCPU *cpu = RISCV_CPU(dev);
1312     CPURISCVState *env = &cpu->env;
1313     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev);
1314     Error *local_err = NULL;
1315 
1316     cpu_exec_realizefn(cs, &local_err);
1317     if (local_err != NULL) {
1318         error_propagate(errp, local_err);
1319         return;
1320     }
1321 
1322     riscv_cpu_validate_misa_mxl(cpu, &local_err);
1323     if (local_err != NULL) {
1324         error_propagate(errp, local_err);
1325         return;
1326     }
1327 
1328     riscv_cpu_validate_priv_spec(cpu, &local_err);
1329     if (local_err != NULL) {
1330         error_propagate(errp, local_err);
1331         return;
1332     }
1333 
1334     riscv_cpu_validate_misa_priv(env, &local_err);
1335     if (local_err != NULL) {
1336         error_propagate(errp, local_err);
1337         return;
1338     }
1339 
1340     if (cpu->cfg.epmp && !cpu->cfg.pmp) {
1341         /*
1342          * Enhanced PMP should only be available
1343          * on harts with PMP support
1344          */
1345         error_setg(errp, "Invalid configuration: EPMP requires PMP support");
1346         return;
1347     }
1348 
1349     riscv_cpu_validate_set_extensions(cpu, &local_err);
1350     if (local_err != NULL) {
1351         error_propagate(errp, local_err);
1352         return;
1353     }
1354 
1355 #ifndef CONFIG_USER_ONLY
1356     cs->tcg_cflags |= CF_PCREL;
1357 
1358     if (cpu->cfg.ext_sstc) {
1359         riscv_timer_init(cpu);
1360     }
1361 
1362     if (cpu->cfg.pmu_num) {
1363         if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) {
1364             cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
1365                                           riscv_pmu_timer_cb, cpu);
1366         }
1367      }
1368 #endif
1369 
1370     riscv_cpu_finalize_features(cpu, &local_err);
1371     if (local_err != NULL) {
1372         error_propagate(errp, local_err);
1373         return;
1374     }
1375 
1376     riscv_cpu_register_gdb_regs_for_features(cs);
1377 
1378     qemu_init_vcpu(cs);
1379     cpu_reset(cs);
1380 
1381     mcc->parent_realize(dev, errp);
1382 }
1383 
1384 #ifndef CONFIG_USER_ONLY
1385 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name,
1386                                void *opaque, Error **errp)
1387 {
1388     RISCVSATPMap *satp_map = opaque;
1389     uint8_t satp = satp_mode_from_str(name);
1390     bool value;
1391 
1392     value = satp_map->map & (1 << satp);
1393 
1394     visit_type_bool(v, name, &value, errp);
1395 }
1396 
1397 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name,
1398                                void *opaque, Error **errp)
1399 {
1400     RISCVSATPMap *satp_map = opaque;
1401     uint8_t satp = satp_mode_from_str(name);
1402     bool value;
1403 
1404     if (!visit_type_bool(v, name, &value, errp)) {
1405         return;
1406     }
1407 
1408     satp_map->map = deposit32(satp_map->map, satp, 1, value);
1409     satp_map->init |= 1 << satp;
1410 }
1411 
1412 static void riscv_add_satp_mode_properties(Object *obj)
1413 {
1414     RISCVCPU *cpu = RISCV_CPU(obj);
1415 
1416     if (cpu->env.misa_mxl == MXL_RV32) {
1417         object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp,
1418                             cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1419     } else {
1420         object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp,
1421                             cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1422         object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp,
1423                             cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1424         object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp,
1425                             cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1426         object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp,
1427                             cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode);
1428     }
1429 }
1430 
1431 static void riscv_cpu_set_irq(void *opaque, int irq, int level)
1432 {
1433     RISCVCPU *cpu = RISCV_CPU(opaque);
1434     CPURISCVState *env = &cpu->env;
1435 
1436     if (irq < IRQ_LOCAL_MAX) {
1437         switch (irq) {
1438         case IRQ_U_SOFT:
1439         case IRQ_S_SOFT:
1440         case IRQ_VS_SOFT:
1441         case IRQ_M_SOFT:
1442         case IRQ_U_TIMER:
1443         case IRQ_S_TIMER:
1444         case IRQ_VS_TIMER:
1445         case IRQ_M_TIMER:
1446         case IRQ_U_EXT:
1447         case IRQ_VS_EXT:
1448         case IRQ_M_EXT:
1449             if (kvm_enabled()) {
1450                 kvm_riscv_set_irq(cpu, irq, level);
1451             } else {
1452                 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level));
1453             }
1454              break;
1455         case IRQ_S_EXT:
1456             if (kvm_enabled()) {
1457                 kvm_riscv_set_irq(cpu, irq, level);
1458             } else {
1459                 env->external_seip = level;
1460                 riscv_cpu_update_mip(env, 1 << irq,
1461                                      BOOL_TO_MASK(level | env->software_seip));
1462             }
1463             break;
1464         default:
1465             g_assert_not_reached();
1466         }
1467     } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) {
1468         /* Require H-extension for handling guest local interrupts */
1469         if (!riscv_has_ext(env, RVH)) {
1470             g_assert_not_reached();
1471         }
1472 
1473         /* Compute bit position in HGEIP CSR */
1474         irq = irq - IRQ_LOCAL_MAX + 1;
1475         if (env->geilen < irq) {
1476             g_assert_not_reached();
1477         }
1478 
1479         /* Update HGEIP CSR */
1480         env->hgeip &= ~((target_ulong)1 << irq);
1481         if (level) {
1482             env->hgeip |= (target_ulong)1 << irq;
1483         }
1484 
1485         /* Update mip.SGEIP bit */
1486         riscv_cpu_update_mip(env, MIP_SGEIP,
1487                              BOOL_TO_MASK(!!(env->hgeie & env->hgeip)));
1488     } else {
1489         g_assert_not_reached();
1490     }
1491 }
1492 #endif /* CONFIG_USER_ONLY */
1493 
1494 static void riscv_cpu_init(Object *obj)
1495 {
1496     RISCVCPU *cpu = RISCV_CPU(obj);
1497 
1498     cpu_set_cpustate_pointers(cpu);
1499 
1500 #ifndef CONFIG_USER_ONLY
1501     qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq,
1502                       IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX);
1503 #endif /* CONFIG_USER_ONLY */
1504 }
1505 
1506 typedef struct RISCVCPUMisaExtConfig {
1507     const char *name;
1508     const char *description;
1509     target_ulong misa_bit;
1510     bool enabled;
1511 } RISCVCPUMisaExtConfig;
1512 
1513 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
1514                                  void *opaque, Error **errp)
1515 {
1516     const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
1517     target_ulong misa_bit = misa_ext_cfg->misa_bit;
1518     RISCVCPU *cpu = RISCV_CPU(obj);
1519     CPURISCVState *env = &cpu->env;
1520     bool value;
1521 
1522     if (!visit_type_bool(v, name, &value, errp)) {
1523         return;
1524     }
1525 
1526     if (value) {
1527         env->misa_ext |= misa_bit;
1528         env->misa_ext_mask |= misa_bit;
1529     } else {
1530         env->misa_ext &= ~misa_bit;
1531         env->misa_ext_mask &= ~misa_bit;
1532     }
1533 }
1534 
1535 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,
1536                                  void *opaque, Error **errp)
1537 {
1538     const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque;
1539     target_ulong misa_bit = misa_ext_cfg->misa_bit;
1540     RISCVCPU *cpu = RISCV_CPU(obj);
1541     CPURISCVState *env = &cpu->env;
1542     bool value;
1543 
1544     value = env->misa_ext & misa_bit;
1545 
1546     visit_type_bool(v, name, &value, errp);
1547 }
1548 
1549 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
1550     {.name = "a", .description = "Atomic instructions",
1551      .misa_bit = RVA, .enabled = true},
1552     {.name = "c", .description = "Compressed instructions",
1553      .misa_bit = RVC, .enabled = true},
1554     {.name = "d", .description = "Double-precision float point",
1555      .misa_bit = RVD, .enabled = true},
1556     {.name = "f", .description = "Single-precision float point",
1557      .misa_bit = RVF, .enabled = true},
1558     {.name = "i", .description = "Base integer instruction set",
1559      .misa_bit = RVI, .enabled = true},
1560     {.name = "e", .description = "Base integer instruction set (embedded)",
1561      .misa_bit = RVE, .enabled = false},
1562     {.name = "m", .description = "Integer multiplication and division",
1563      .misa_bit = RVM, .enabled = true},
1564     {.name = "s", .description = "Supervisor-level instructions",
1565      .misa_bit = RVS, .enabled = true},
1566     {.name = "u", .description = "User-level instructions",
1567      .misa_bit = RVU, .enabled = true},
1568     {.name = "h", .description = "Hypervisor",
1569      .misa_bit = RVH, .enabled = true},
1570     {.name = "x-j", .description = "Dynamic translated languages",
1571      .misa_bit = RVJ, .enabled = false},
1572     {.name = "v", .description = "Vector operations",
1573      .misa_bit = RVV, .enabled = false},
1574     {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)",
1575      .misa_bit = RVG, .enabled = false},
1576 };
1577 
1578 static void riscv_cpu_add_misa_properties(Object *cpu_obj)
1579 {
1580     int i;
1581 
1582     for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) {
1583         const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i];
1584 
1585         object_property_add(cpu_obj, misa_cfg->name, "bool",
1586                             cpu_get_misa_ext_cfg,
1587                             cpu_set_misa_ext_cfg,
1588                             NULL, (void *)misa_cfg);
1589         object_property_set_description(cpu_obj, misa_cfg->name,
1590                                         misa_cfg->description);
1591         object_property_set_bool(cpu_obj, misa_cfg->name,
1592                                  misa_cfg->enabled, NULL);
1593     }
1594 }
1595 
1596 static Property riscv_cpu_extensions[] = {
1597     /* Defaults for standard extensions */
1598     DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16),
1599     DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false),
1600     DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
1601     DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
1602     DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true),
1603     DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true),
1604     DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false),
1605     DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false),
1606     DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false),
1607     DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
1608     DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false),
1609     DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
1610     DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
1611     DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true),
1612 
1613     DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
1614     DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
1615     DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
1616     DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
1617 
1618     DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false),
1619     DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true),
1620     DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
1621     DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
1622     DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
1623 
1624     DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true),
1625     DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true),
1626     DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true),
1627     DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false),
1628     DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false),
1629     DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false),
1630     DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true),
1631     DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false),
1632     DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false),
1633     DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false),
1634     DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false),
1635     DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false),
1636     DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false),
1637     DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false),
1638     DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false),
1639     DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false),
1640     DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false),
1641 
1642     DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false),
1643     DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false),
1644     DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false),
1645     DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false),
1646 
1647     DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true),
1648     DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64),
1649     DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true),
1650     DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64),
1651 
1652     DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
1653 
1654     DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false),
1655     DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false),
1656     DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false),
1657     DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false),
1658     DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false),
1659     DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
1660     DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
1661 
1662     /* Vendor-specific custom extensions */
1663     DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
1664     DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false),
1665     DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false),
1666     DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
1667     DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false),
1668     DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false),
1669     DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false),
1670     DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false),
1671     DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false),
1672     DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false),
1673     DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
1674     DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
1675 
1676     /* These are experimental so mark with 'x-' */
1677     DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false),
1678 
1679     /* ePMP 0.9.3 */
1680     DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),
1681     DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false),
1682     DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false),
1683 
1684     DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false),
1685     DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false),
1686 
1687     DEFINE_PROP_END_OF_LIST(),
1688 };
1689 
1690 /*
1691  * Add CPU properties with user-facing flags.
1692  *
1693  * This will overwrite existing env->misa_ext values with the
1694  * defaults set via riscv_cpu_add_misa_properties().
1695  */
1696 static void riscv_cpu_add_user_properties(Object *obj)
1697 {
1698     Property *prop;
1699     DeviceState *dev = DEVICE(obj);
1700 
1701     riscv_cpu_add_misa_properties(obj);
1702 
1703     for (prop = riscv_cpu_extensions; prop && prop->name; prop++) {
1704         qdev_property_add_static(dev, prop);
1705     }
1706 
1707 #ifndef CONFIG_USER_ONLY
1708     riscv_add_satp_mode_properties(obj);
1709 #endif
1710 }
1711 
1712 static Property riscv_cpu_properties[] = {
1713     DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
1714 
1715     DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
1716     DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID),
1717     DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID),
1718 
1719 #ifndef CONFIG_USER_ONLY
1720     DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC),
1721 #endif
1722 
1723     DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false),
1724 
1725     DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false),
1726     DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false),
1727 
1728     /*
1729      * write_misa() is marked as experimental for now so mark
1730      * it with -x and default to 'false'.
1731      */
1732     DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false),
1733     DEFINE_PROP_END_OF_LIST(),
1734 };
1735 
1736 static gchar *riscv_gdb_arch_name(CPUState *cs)
1737 {
1738     RISCVCPU *cpu = RISCV_CPU(cs);
1739     CPURISCVState *env = &cpu->env;
1740 
1741     switch (riscv_cpu_mxl(env)) {
1742     case MXL_RV32:
1743         return g_strdup("riscv:rv32");
1744     case MXL_RV64:
1745     case MXL_RV128:
1746         return g_strdup("riscv:rv64");
1747     default:
1748         g_assert_not_reached();
1749     }
1750 }
1751 
1752 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname)
1753 {
1754     RISCVCPU *cpu = RISCV_CPU(cs);
1755 
1756     if (strcmp(xmlname, "riscv-csr.xml") == 0) {
1757         return cpu->dyn_csr_xml;
1758     } else if (strcmp(xmlname, "riscv-vector.xml") == 0) {
1759         return cpu->dyn_vreg_xml;
1760     }
1761 
1762     return NULL;
1763 }
1764 
1765 #ifndef CONFIG_USER_ONLY
1766 static int64_t riscv_get_arch_id(CPUState *cs)
1767 {
1768     RISCVCPU *cpu = RISCV_CPU(cs);
1769 
1770     return cpu->env.mhartid;
1771 }
1772 
1773 #include "hw/core/sysemu-cpu-ops.h"
1774 
1775 static const struct SysemuCPUOps riscv_sysemu_ops = {
1776     .get_phys_page_debug = riscv_cpu_get_phys_page_debug,
1777     .write_elf64_note = riscv_cpu_write_elf64_note,
1778     .write_elf32_note = riscv_cpu_write_elf32_note,
1779     .legacy_vmsd = &vmstate_riscv_cpu,
1780 };
1781 #endif
1782 
1783 #include "hw/core/tcg-cpu-ops.h"
1784 
1785 static const struct TCGCPUOps riscv_tcg_ops = {
1786     .initialize = riscv_translate_init,
1787     .synchronize_from_tb = riscv_cpu_synchronize_from_tb,
1788     .restore_state_to_opc = riscv_restore_state_to_opc,
1789 
1790 #ifndef CONFIG_USER_ONLY
1791     .tlb_fill = riscv_cpu_tlb_fill,
1792     .cpu_exec_interrupt = riscv_cpu_exec_interrupt,
1793     .do_interrupt = riscv_cpu_do_interrupt,
1794     .do_transaction_failed = riscv_cpu_do_transaction_failed,
1795     .do_unaligned_access = riscv_cpu_do_unaligned_access,
1796     .debug_excp_handler = riscv_cpu_debug_excp_handler,
1797     .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
1798     .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
1799 #endif /* !CONFIG_USER_ONLY */
1800 };
1801 
1802 static void riscv_cpu_class_init(ObjectClass *c, void *data)
1803 {
1804     RISCVCPUClass *mcc = RISCV_CPU_CLASS(c);
1805     CPUClass *cc = CPU_CLASS(c);
1806     DeviceClass *dc = DEVICE_CLASS(c);
1807     ResettableClass *rc = RESETTABLE_CLASS(c);
1808 
1809     device_class_set_parent_realize(dc, riscv_cpu_realize,
1810                                     &mcc->parent_realize);
1811 
1812     resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL,
1813                                        &mcc->parent_phases);
1814 
1815     cc->class_by_name = riscv_cpu_class_by_name;
1816     cc->has_work = riscv_cpu_has_work;
1817     cc->dump_state = riscv_cpu_dump_state;
1818     cc->set_pc = riscv_cpu_set_pc;
1819     cc->get_pc = riscv_cpu_get_pc;
1820     cc->gdb_read_register = riscv_cpu_gdb_read_register;
1821     cc->gdb_write_register = riscv_cpu_gdb_write_register;
1822     cc->gdb_num_core_regs = 33;
1823     cc->gdb_stop_before_watchpoint = true;
1824     cc->disas_set_info = riscv_cpu_disas_set_info;
1825 #ifndef CONFIG_USER_ONLY
1826     cc->sysemu_ops = &riscv_sysemu_ops;
1827     cc->get_arch_id = riscv_get_arch_id;
1828 #endif
1829     cc->gdb_arch_name = riscv_gdb_arch_name;
1830     cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml;
1831     cc->tcg_ops = &riscv_tcg_ops;
1832 
1833     device_class_set_props(dc, riscv_cpu_properties);
1834 }
1835 
1836 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str,
1837                                  int max_str_len)
1838 {
1839     char *old = *isa_str;
1840     char *new = *isa_str;
1841     int i;
1842 
1843     for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) {
1844         if (cpu->env.priv_ver >= isa_edata_arr[i].min_version &&
1845             isa_ext_is_enabled(cpu, &isa_edata_arr[i])) {
1846             new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL);
1847             g_free(old);
1848             old = new;
1849         }
1850     }
1851 
1852     *isa_str = new;
1853 }
1854 
1855 char *riscv_isa_string(RISCVCPU *cpu)
1856 {
1857     int i;
1858     const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts);
1859     char *isa_str = g_new(char, maxlen);
1860     char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS);
1861     for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) {
1862         if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) {
1863             *p++ = qemu_tolower(riscv_single_letter_exts[i]);
1864         }
1865     }
1866     *p = '\0';
1867     if (!cpu->cfg.short_isa_string) {
1868         riscv_isa_string_ext(cpu, &isa_str, maxlen);
1869     }
1870     return isa_str;
1871 }
1872 
1873 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b)
1874 {
1875     ObjectClass *class_a = (ObjectClass *)a;
1876     ObjectClass *class_b = (ObjectClass *)b;
1877     const char *name_a, *name_b;
1878 
1879     name_a = object_class_get_name(class_a);
1880     name_b = object_class_get_name(class_b);
1881     return strcmp(name_a, name_b);
1882 }
1883 
1884 static void riscv_cpu_list_entry(gpointer data, gpointer user_data)
1885 {
1886     const char *typename = object_class_get_name(OBJECT_CLASS(data));
1887     int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX);
1888 
1889     qemu_printf("%.*s\n", len, typename);
1890 }
1891 
1892 void riscv_cpu_list(void)
1893 {
1894     GSList *list;
1895 
1896     list = object_class_get_list(TYPE_RISCV_CPU, false);
1897     list = g_slist_sort(list, riscv_cpu_list_compare);
1898     g_slist_foreach(list, riscv_cpu_list_entry, NULL);
1899     g_slist_free(list);
1900 }
1901 
1902 #define DEFINE_CPU(type_name, initfn)      \
1903     {                                      \
1904         .name = type_name,                 \
1905         .parent = TYPE_RISCV_CPU,          \
1906         .instance_init = initfn            \
1907     }
1908 
1909 #define DEFINE_DYNAMIC_CPU(type_name, initfn) \
1910     {                                         \
1911         .name = type_name,                    \
1912         .parent = TYPE_RISCV_DYNAMIC_CPU,     \
1913         .instance_init = initfn               \
1914     }
1915 
1916 static const TypeInfo riscv_cpu_type_infos[] = {
1917     {
1918         .name = TYPE_RISCV_CPU,
1919         .parent = TYPE_CPU,
1920         .instance_size = sizeof(RISCVCPU),
1921         .instance_align = __alignof__(RISCVCPU),
1922         .instance_init = riscv_cpu_init,
1923         .abstract = true,
1924         .class_size = sizeof(RISCVCPUClass),
1925         .class_init = riscv_cpu_class_init,
1926     },
1927     {
1928         .name = TYPE_RISCV_DYNAMIC_CPU,
1929         .parent = TYPE_RISCV_CPU,
1930         .abstract = true,
1931     },
1932     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY,      riscv_any_cpu_init),
1933 #if defined(CONFIG_KVM)
1934     DEFINE_CPU(TYPE_RISCV_CPU_HOST,             riscv_host_cpu_init),
1935 #endif
1936 #if defined(TARGET_RISCV32)
1937     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32,   rv32_base_cpu_init),
1938     DEFINE_CPU(TYPE_RISCV_CPU_IBEX,             rv32_ibex_cpu_init),
1939     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31,       rv32_sifive_e_cpu_init),
1940     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34,       rv32_imafcu_nommu_cpu_init),
1941     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34,       rv32_sifive_u_cpu_init),
1942 #elif defined(TARGET_RISCV64)
1943     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64,   rv64_base_cpu_init),
1944     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51,       rv64_sifive_e_cpu_init),
1945     DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54,       rv64_sifive_u_cpu_init),
1946     DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C,         rv64_sifive_u_cpu_init),
1947     DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906,       rv64_thead_c906_cpu_init),
1948     DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1,        rv64_veyron_v1_cpu_init),
1949     DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128,  rv128_base_cpu_init),
1950 #endif
1951 };
1952 
1953 DEFINE_TYPES(riscv_cpu_type_infos)
1954