1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "exec/exec-all.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "fpu/softfloat-helpers.h" 32 33 /* RISC-V CPU definitions */ 34 35 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 36 37 const char * const riscv_int_regnames[] = { 38 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 39 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 40 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 41 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 42 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 43 }; 44 45 const char * const riscv_fpr_regnames[] = { 46 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 47 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 48 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 49 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 50 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 51 "f30/ft10", "f31/ft11" 52 }; 53 54 const char * const riscv_excp_names[] = { 55 "misaligned_fetch", 56 "fault_fetch", 57 "illegal_instruction", 58 "breakpoint", 59 "misaligned_load", 60 "fault_load", 61 "misaligned_store", 62 "fault_store", 63 "user_ecall", 64 "supervisor_ecall", 65 "hypervisor_ecall", 66 "machine_ecall", 67 "exec_page_fault", 68 "load_page_fault", 69 "reserved", 70 "store_page_fault", 71 "reserved", 72 "reserved", 73 "reserved", 74 "reserved", 75 "guest_exec_page_fault", 76 "guest_load_page_fault", 77 "reserved", 78 "guest_store_page_fault", 79 }; 80 81 const char * const riscv_intr_names[] = { 82 "u_software", 83 "s_software", 84 "vs_software", 85 "m_software", 86 "u_timer", 87 "s_timer", 88 "vs_timer", 89 "m_timer", 90 "u_external", 91 "vs_external", 92 "h_external", 93 "m_external", 94 "reserved", 95 "reserved", 96 "reserved", 97 "reserved" 98 }; 99 100 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 101 { 102 if (async) { 103 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 104 riscv_intr_names[cause] : "(unknown)"; 105 } else { 106 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 107 riscv_excp_names[cause] : "(unknown)"; 108 } 109 } 110 111 bool riscv_cpu_is_32bit(CPURISCVState *env) 112 { 113 if (env->misa & RV64) { 114 return false; 115 } 116 117 return true; 118 } 119 120 static void set_misa(CPURISCVState *env, target_ulong misa) 121 { 122 env->misa_mask = env->misa = misa; 123 } 124 125 static void set_priv_version(CPURISCVState *env, int priv_ver) 126 { 127 env->priv_ver = priv_ver; 128 } 129 130 static void set_vext_version(CPURISCVState *env, int vext_ver) 131 { 132 env->vext_ver = vext_ver; 133 } 134 135 static void set_feature(CPURISCVState *env, int feature) 136 { 137 env->features |= (1ULL << feature); 138 } 139 140 static void set_resetvec(CPURISCVState *env, int resetvec) 141 { 142 #ifndef CONFIG_USER_ONLY 143 env->resetvec = resetvec; 144 #endif 145 } 146 147 static void riscv_any_cpu_init(Object *obj) 148 { 149 CPURISCVState *env = &RISCV_CPU(obj)->env; 150 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); 151 set_priv_version(env, PRIV_VERSION_1_11_0); 152 } 153 154 static void riscv_base_cpu_init(Object *obj) 155 { 156 CPURISCVState *env = &RISCV_CPU(obj)->env; 157 /* We set this in the realise function */ 158 set_misa(env, 0); 159 } 160 161 static void rvxx_sifive_u_cpu_init(Object *obj) 162 { 163 CPURISCVState *env = &RISCV_CPU(obj)->env; 164 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 165 set_priv_version(env, PRIV_VERSION_1_10_0); 166 } 167 168 static void rvxx_sifive_e_cpu_init(Object *obj) 169 { 170 CPURISCVState *env = &RISCV_CPU(obj)->env; 171 set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU); 172 set_priv_version(env, PRIV_VERSION_1_10_0); 173 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 174 } 175 176 #if defined(TARGET_RISCV32) 177 178 static void rv32_ibex_cpu_init(Object *obj) 179 { 180 CPURISCVState *env = &RISCV_CPU(obj)->env; 181 set_misa(env, RV32 | RVI | RVM | RVC | RVU); 182 set_priv_version(env, PRIV_VERSION_1_10_0); 183 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 184 } 185 186 static void rv32_imafcu_nommu_cpu_init(Object *obj) 187 { 188 CPURISCVState *env = &RISCV_CPU(obj)->env; 189 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); 190 set_priv_version(env, PRIV_VERSION_1_10_0); 191 set_resetvec(env, DEFAULT_RSTVEC); 192 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 193 } 194 195 #endif 196 197 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 198 { 199 ObjectClass *oc; 200 char *typename; 201 char **cpuname; 202 203 cpuname = g_strsplit(cpu_model, ",", 1); 204 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 205 oc = object_class_by_name(typename); 206 g_strfreev(cpuname); 207 g_free(typename); 208 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 209 object_class_is_abstract(oc)) { 210 return NULL; 211 } 212 return oc; 213 } 214 215 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 216 { 217 RISCVCPU *cpu = RISCV_CPU(cs); 218 CPURISCVState *env = &cpu->env; 219 int i; 220 221 #if !defined(CONFIG_USER_ONLY) 222 if (riscv_has_ext(env, RVH)) { 223 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 224 } 225 #endif 226 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 227 #ifndef CONFIG_USER_ONLY 228 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); 229 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); 230 #ifdef TARGET_RISCV32 231 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", 232 (target_ulong)(env->mstatus >> 32)); 233 #endif 234 if (riscv_has_ext(env, RVH)) { 235 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); 236 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", 237 (target_ulong)env->vsstatus); 238 } 239 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); 240 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); 241 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); 242 if (riscv_has_ext(env, RVH)) { 243 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); 244 } 245 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); 246 if (riscv_has_ext(env, RVH)) { 247 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); 248 } 249 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); 250 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); 251 if (riscv_has_ext(env, RVH)) { 252 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); 253 } 254 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); 255 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); 256 if (riscv_has_ext(env, RVH)) { 257 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); 258 } 259 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); 260 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); 261 if (riscv_has_ext(env, RVH)) { 262 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); 263 } 264 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); 265 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->sbadaddr); 266 if (riscv_has_ext(env, RVH)) { 267 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); 268 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); 269 } 270 #endif 271 272 for (i = 0; i < 32; i++) { 273 qemu_fprintf(f, " %s " TARGET_FMT_lx, 274 riscv_int_regnames[i], env->gpr[i]); 275 if ((i & 3) == 3) { 276 qemu_fprintf(f, "\n"); 277 } 278 } 279 if (flags & CPU_DUMP_FPU) { 280 for (i = 0; i < 32; i++) { 281 qemu_fprintf(f, " %s %016" PRIx64, 282 riscv_fpr_regnames[i], env->fpr[i]); 283 if ((i & 3) == 3) { 284 qemu_fprintf(f, "\n"); 285 } 286 } 287 } 288 } 289 290 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 291 { 292 RISCVCPU *cpu = RISCV_CPU(cs); 293 CPURISCVState *env = &cpu->env; 294 env->pc = value; 295 } 296 297 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 298 { 299 RISCVCPU *cpu = RISCV_CPU(cs); 300 CPURISCVState *env = &cpu->env; 301 env->pc = tb->pc; 302 } 303 304 static bool riscv_cpu_has_work(CPUState *cs) 305 { 306 #ifndef CONFIG_USER_ONLY 307 RISCVCPU *cpu = RISCV_CPU(cs); 308 CPURISCVState *env = &cpu->env; 309 /* 310 * Definition of the WFI instruction requires it to ignore the privilege 311 * mode and delegation registers, but respect individual enables 312 */ 313 return (env->mip & env->mie) != 0; 314 #else 315 return true; 316 #endif 317 } 318 319 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 320 target_ulong *data) 321 { 322 env->pc = data[0]; 323 } 324 325 static void riscv_cpu_reset(DeviceState *dev) 326 { 327 CPUState *cs = CPU(dev); 328 RISCVCPU *cpu = RISCV_CPU(cs); 329 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 330 CPURISCVState *env = &cpu->env; 331 332 mcc->parent_reset(dev); 333 #ifndef CONFIG_USER_ONLY 334 env->priv = PRV_M; 335 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 336 env->mcause = 0; 337 env->pc = env->resetvec; 338 #endif 339 cs->exception_index = EXCP_NONE; 340 env->load_res = -1; 341 set_default_nan_mode(1, &env->fp_status); 342 } 343 344 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 345 { 346 #if defined(TARGET_RISCV32) 347 info->print_insn = print_insn_riscv32; 348 #elif defined(TARGET_RISCV64) 349 info->print_insn = print_insn_riscv64; 350 #endif 351 } 352 353 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 354 { 355 CPUState *cs = CPU(dev); 356 RISCVCPU *cpu = RISCV_CPU(dev); 357 CPURISCVState *env = &cpu->env; 358 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 359 int priv_version = PRIV_VERSION_1_11_0; 360 int vext_version = VEXT_VERSION_0_07_1; 361 target_ulong target_misa = 0; 362 Error *local_err = NULL; 363 364 cpu_exec_realizefn(cs, &local_err); 365 if (local_err != NULL) { 366 error_propagate(errp, local_err); 367 return; 368 } 369 370 if (cpu->cfg.priv_spec) { 371 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 372 priv_version = PRIV_VERSION_1_11_0; 373 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 374 priv_version = PRIV_VERSION_1_10_0; 375 } else { 376 error_setg(errp, 377 "Unsupported privilege spec version '%s'", 378 cpu->cfg.priv_spec); 379 return; 380 } 381 } 382 383 set_priv_version(env, priv_version); 384 set_vext_version(env, vext_version); 385 386 if (cpu->cfg.mmu) { 387 set_feature(env, RISCV_FEATURE_MMU); 388 } 389 390 if (cpu->cfg.pmp) { 391 set_feature(env, RISCV_FEATURE_PMP); 392 } 393 394 set_resetvec(env, cpu->cfg.resetvec); 395 396 /* If misa isn't set (rv32 and rv64 machines) set it here */ 397 if (!env->misa) { 398 /* Do some ISA extension error checking */ 399 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 400 error_setg(errp, 401 "I and E extensions are incompatible"); 402 return; 403 } 404 405 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 406 error_setg(errp, 407 "Either I or E extension must be set"); 408 return; 409 } 410 411 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 412 cpu->cfg.ext_a & cpu->cfg.ext_f & 413 cpu->cfg.ext_d)) { 414 warn_report("Setting G will also set IMAFD"); 415 cpu->cfg.ext_i = true; 416 cpu->cfg.ext_m = true; 417 cpu->cfg.ext_a = true; 418 cpu->cfg.ext_f = true; 419 cpu->cfg.ext_d = true; 420 } 421 422 /* Set the ISA extensions, checks should have happened above */ 423 if (cpu->cfg.ext_i) { 424 target_misa |= RVI; 425 } 426 if (cpu->cfg.ext_e) { 427 target_misa |= RVE; 428 } 429 if (cpu->cfg.ext_m) { 430 target_misa |= RVM; 431 } 432 if (cpu->cfg.ext_a) { 433 target_misa |= RVA; 434 } 435 if (cpu->cfg.ext_f) { 436 target_misa |= RVF; 437 } 438 if (cpu->cfg.ext_d) { 439 target_misa |= RVD; 440 } 441 if (cpu->cfg.ext_c) { 442 target_misa |= RVC; 443 } 444 if (cpu->cfg.ext_s) { 445 target_misa |= RVS; 446 } 447 if (cpu->cfg.ext_u) { 448 target_misa |= RVU; 449 } 450 if (cpu->cfg.ext_h) { 451 target_misa |= RVH; 452 } 453 if (cpu->cfg.ext_v) { 454 target_misa |= RVV; 455 if (!is_power_of_2(cpu->cfg.vlen)) { 456 error_setg(errp, 457 "Vector extension VLEN must be power of 2"); 458 return; 459 } 460 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 461 error_setg(errp, 462 "Vector extension implementation only supports VLEN " 463 "in the range [128, %d]", RV_VLEN_MAX); 464 return; 465 } 466 if (!is_power_of_2(cpu->cfg.elen)) { 467 error_setg(errp, 468 "Vector extension ELEN must be power of 2"); 469 return; 470 } 471 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 472 error_setg(errp, 473 "Vector extension implementation only supports ELEN " 474 "in the range [8, 64]"); 475 return; 476 } 477 if (cpu->cfg.vext_spec) { 478 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { 479 vext_version = VEXT_VERSION_0_07_1; 480 } else { 481 error_setg(errp, 482 "Unsupported vector spec version '%s'", 483 cpu->cfg.vext_spec); 484 return; 485 } 486 } else { 487 qemu_log("vector verison is not specified, " 488 "use the default value v0.7.1\n"); 489 } 490 set_vext_version(env, vext_version); 491 } 492 493 set_misa(env, RVXLEN | target_misa); 494 } 495 496 riscv_cpu_register_gdb_regs_for_features(cs); 497 498 qemu_init_vcpu(cs); 499 cpu_reset(cs); 500 501 mcc->parent_realize(dev, errp); 502 } 503 504 static void riscv_cpu_init(Object *obj) 505 { 506 RISCVCPU *cpu = RISCV_CPU(obj); 507 508 cpu_set_cpustate_pointers(cpu); 509 } 510 511 static Property riscv_cpu_properties[] = { 512 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 513 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 514 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 515 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 516 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 517 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 518 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 519 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 520 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 521 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 522 /* This is experimental so mark with 'x-' */ 523 DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), 524 DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), 525 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 526 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 527 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 528 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 529 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 530 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 531 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 532 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 533 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 534 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 535 DEFINE_PROP_END_OF_LIST(), 536 }; 537 538 static void riscv_cpu_class_init(ObjectClass *c, void *data) 539 { 540 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 541 CPUClass *cc = CPU_CLASS(c); 542 DeviceClass *dc = DEVICE_CLASS(c); 543 544 device_class_set_parent_realize(dc, riscv_cpu_realize, 545 &mcc->parent_realize); 546 547 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 548 549 cc->class_by_name = riscv_cpu_class_by_name; 550 cc->has_work = riscv_cpu_has_work; 551 cc->do_interrupt = riscv_cpu_do_interrupt; 552 cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt; 553 cc->dump_state = riscv_cpu_dump_state; 554 cc->set_pc = riscv_cpu_set_pc; 555 cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb; 556 cc->gdb_read_register = riscv_cpu_gdb_read_register; 557 cc->gdb_write_register = riscv_cpu_gdb_write_register; 558 cc->gdb_num_core_regs = 33; 559 #if defined(TARGET_RISCV32) 560 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 561 #elif defined(TARGET_RISCV64) 562 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 563 #endif 564 cc->gdb_stop_before_watchpoint = true; 565 cc->disas_set_info = riscv_cpu_disas_set_info; 566 #ifndef CONFIG_USER_ONLY 567 cc->do_transaction_failed = riscv_cpu_do_transaction_failed; 568 cc->do_unaligned_access = riscv_cpu_do_unaligned_access; 569 cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; 570 /* For now, mark unmigratable: */ 571 cc->vmsd = &vmstate_riscv_cpu; 572 #endif 573 #ifdef CONFIG_TCG 574 cc->tcg_initialize = riscv_translate_init; 575 cc->tlb_fill = riscv_cpu_tlb_fill; 576 #endif 577 device_class_set_props(dc, riscv_cpu_properties); 578 } 579 580 char *riscv_isa_string(RISCVCPU *cpu) 581 { 582 int i; 583 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 584 char *isa_str = g_new(char, maxlen); 585 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 586 for (i = 0; i < sizeof(riscv_exts); i++) { 587 if (cpu->env.misa & RV(riscv_exts[i])) { 588 *p++ = qemu_tolower(riscv_exts[i]); 589 } 590 } 591 *p = '\0'; 592 return isa_str; 593 } 594 595 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 596 { 597 ObjectClass *class_a = (ObjectClass *)a; 598 ObjectClass *class_b = (ObjectClass *)b; 599 const char *name_a, *name_b; 600 601 name_a = object_class_get_name(class_a); 602 name_b = object_class_get_name(class_b); 603 return strcmp(name_a, name_b); 604 } 605 606 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 607 { 608 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 609 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 610 611 qemu_printf("%.*s\n", len, typename); 612 } 613 614 void riscv_cpu_list(void) 615 { 616 GSList *list; 617 618 list = object_class_get_list(TYPE_RISCV_CPU, false); 619 list = g_slist_sort(list, riscv_cpu_list_compare); 620 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 621 g_slist_free(list); 622 } 623 624 #define DEFINE_CPU(type_name, initfn) \ 625 { \ 626 .name = type_name, \ 627 .parent = TYPE_RISCV_CPU, \ 628 .instance_init = initfn \ 629 } 630 631 static const TypeInfo riscv_cpu_type_infos[] = { 632 { 633 .name = TYPE_RISCV_CPU, 634 .parent = TYPE_CPU, 635 .instance_size = sizeof(RISCVCPU), 636 .instance_align = __alignof__(RISCVCPU), 637 .instance_init = riscv_cpu_init, 638 .abstract = true, 639 .class_size = sizeof(RISCVCPUClass), 640 .class_init = riscv_cpu_class_init, 641 }, 642 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 643 #if defined(TARGET_RISCV32) 644 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base_cpu_init), 645 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 646 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rvxx_sifive_e_cpu_init), 647 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 648 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rvxx_sifive_u_cpu_init), 649 #elif defined(TARGET_RISCV64) 650 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base_cpu_init), 651 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rvxx_sifive_e_cpu_init), 652 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rvxx_sifive_u_cpu_init), 653 #endif 654 }; 655 656 DEFINE_TYPES(riscv_cpu_type_infos) 657