1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "exec/exec-all.h" 26 #include "qapi/error.h" 27 #include "hw/qdev-properties.h" 28 #include "migration/vmstate.h" 29 30 /* RISC-V CPU definitions */ 31 32 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 33 34 const char * const riscv_int_regnames[] = { 35 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", 36 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 37 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", 38 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" 39 }; 40 41 const char * const riscv_fpr_regnames[] = { 42 "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", 43 "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", 44 "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", 45 "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" 46 }; 47 48 const char * const riscv_excp_names[] = { 49 "misaligned_fetch", 50 "fault_fetch", 51 "illegal_instruction", 52 "breakpoint", 53 "misaligned_load", 54 "fault_load", 55 "misaligned_store", 56 "fault_store", 57 "user_ecall", 58 "supervisor_ecall", 59 "hypervisor_ecall", 60 "machine_ecall", 61 "exec_page_fault", 62 "load_page_fault", 63 "reserved", 64 "store_page_fault" 65 }; 66 67 const char * const riscv_intr_names[] = { 68 "u_software", 69 "s_software", 70 "h_software", 71 "m_software", 72 "u_timer", 73 "s_timer", 74 "h_timer", 75 "m_timer", 76 "u_external", 77 "s_external", 78 "h_external", 79 "m_external", 80 "reserved", 81 "reserved", 82 "reserved", 83 "reserved" 84 }; 85 86 static void set_misa(CPURISCVState *env, target_ulong misa) 87 { 88 env->misa_mask = env->misa = misa; 89 } 90 91 static void set_versions(CPURISCVState *env, int user_ver, int priv_ver) 92 { 93 env->user_ver = user_ver; 94 env->priv_ver = priv_ver; 95 } 96 97 static void set_feature(CPURISCVState *env, int feature) 98 { 99 env->features |= (1ULL << feature); 100 } 101 102 static void set_resetvec(CPURISCVState *env, int resetvec) 103 { 104 #ifndef CONFIG_USER_ONLY 105 env->resetvec = resetvec; 106 #endif 107 } 108 109 static void riscv_any_cpu_init(Object *obj) 110 { 111 CPURISCVState *env = &RISCV_CPU(obj)->env; 112 set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); 113 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); 114 set_resetvec(env, DEFAULT_RSTVEC); 115 } 116 117 #if defined(TARGET_RISCV32) 118 119 static void riscv_base32_cpu_init(Object *obj) 120 { 121 CPURISCVState *env = &RISCV_CPU(obj)->env; 122 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 123 } 124 125 static void rv32gcsu_priv1_09_1_cpu_init(Object *obj) 126 { 127 CPURISCVState *env = &RISCV_CPU(obj)->env; 128 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 129 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1); 130 set_resetvec(env, DEFAULT_RSTVEC); 131 set_feature(env, RISCV_FEATURE_MMU); 132 set_feature(env, RISCV_FEATURE_PMP); 133 } 134 135 static void rv32gcsu_priv1_10_0_cpu_init(Object *obj) 136 { 137 CPURISCVState *env = &RISCV_CPU(obj)->env; 138 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 139 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); 140 set_resetvec(env, DEFAULT_RSTVEC); 141 set_feature(env, RISCV_FEATURE_MMU); 142 set_feature(env, RISCV_FEATURE_PMP); 143 } 144 145 static void rv32imacu_nommu_cpu_init(Object *obj) 146 { 147 CPURISCVState *env = &RISCV_CPU(obj)->env; 148 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); 149 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); 150 set_resetvec(env, DEFAULT_RSTVEC); 151 set_feature(env, RISCV_FEATURE_PMP); 152 } 153 154 #elif defined(TARGET_RISCV64) 155 156 static void riscv_base64_cpu_init(Object *obj) 157 { 158 CPURISCVState *env = &RISCV_CPU(obj)->env; 159 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 160 } 161 162 static void rv64gcsu_priv1_09_1_cpu_init(Object *obj) 163 { 164 CPURISCVState *env = &RISCV_CPU(obj)->env; 165 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 166 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1); 167 set_resetvec(env, DEFAULT_RSTVEC); 168 set_feature(env, RISCV_FEATURE_MMU); 169 set_feature(env, RISCV_FEATURE_PMP); 170 } 171 172 static void rv64gcsu_priv1_10_0_cpu_init(Object *obj) 173 { 174 CPURISCVState *env = &RISCV_CPU(obj)->env; 175 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 176 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); 177 set_resetvec(env, DEFAULT_RSTVEC); 178 set_feature(env, RISCV_FEATURE_MMU); 179 set_feature(env, RISCV_FEATURE_PMP); 180 } 181 182 static void rv64imacu_nommu_cpu_init(Object *obj) 183 { 184 CPURISCVState *env = &RISCV_CPU(obj)->env; 185 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); 186 set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); 187 set_resetvec(env, DEFAULT_RSTVEC); 188 set_feature(env, RISCV_FEATURE_PMP); 189 } 190 191 #endif 192 193 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 194 { 195 ObjectClass *oc; 196 char *typename; 197 char **cpuname; 198 199 cpuname = g_strsplit(cpu_model, ",", 1); 200 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 201 oc = object_class_by_name(typename); 202 g_strfreev(cpuname); 203 g_free(typename); 204 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 205 object_class_is_abstract(oc)) { 206 return NULL; 207 } 208 return oc; 209 } 210 211 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 212 { 213 RISCVCPU *cpu = RISCV_CPU(cs); 214 CPURISCVState *env = &cpu->env; 215 int i; 216 217 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 218 #ifndef CONFIG_USER_ONLY 219 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); 220 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); 221 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", 222 (target_ulong)atomic_read(&env->mip)); 223 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); 224 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); 225 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); 226 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); 227 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); 228 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); 229 #endif 230 231 for (i = 0; i < 32; i++) { 232 qemu_fprintf(f, " %s " TARGET_FMT_lx, 233 riscv_int_regnames[i], env->gpr[i]); 234 if ((i & 3) == 3) { 235 qemu_fprintf(f, "\n"); 236 } 237 } 238 if (flags & CPU_DUMP_FPU) { 239 for (i = 0; i < 32; i++) { 240 qemu_fprintf(f, " %s %016" PRIx64, 241 riscv_fpr_regnames[i], env->fpr[i]); 242 if ((i & 3) == 3) { 243 qemu_fprintf(f, "\n"); 244 } 245 } 246 } 247 } 248 249 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 250 { 251 RISCVCPU *cpu = RISCV_CPU(cs); 252 CPURISCVState *env = &cpu->env; 253 env->pc = value; 254 } 255 256 static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) 257 { 258 RISCVCPU *cpu = RISCV_CPU(cs); 259 CPURISCVState *env = &cpu->env; 260 env->pc = tb->pc; 261 } 262 263 static bool riscv_cpu_has_work(CPUState *cs) 264 { 265 #ifndef CONFIG_USER_ONLY 266 RISCVCPU *cpu = RISCV_CPU(cs); 267 CPURISCVState *env = &cpu->env; 268 /* 269 * Definition of the WFI instruction requires it to ignore the privilege 270 * mode and delegation registers, but respect individual enables 271 */ 272 return (atomic_read(&env->mip) & env->mie) != 0; 273 #else 274 return true; 275 #endif 276 } 277 278 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 279 target_ulong *data) 280 { 281 env->pc = data[0]; 282 } 283 284 static void riscv_cpu_reset(CPUState *cs) 285 { 286 RISCVCPU *cpu = RISCV_CPU(cs); 287 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 288 CPURISCVState *env = &cpu->env; 289 290 mcc->parent_reset(cs); 291 #ifndef CONFIG_USER_ONLY 292 env->priv = PRV_M; 293 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 294 env->mcause = 0; 295 env->pc = env->resetvec; 296 #endif 297 cs->exception_index = EXCP_NONE; 298 set_default_nan_mode(1, &env->fp_status); 299 } 300 301 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 302 { 303 #if defined(TARGET_RISCV32) 304 info->print_insn = print_insn_riscv32; 305 #elif defined(TARGET_RISCV64) 306 info->print_insn = print_insn_riscv64; 307 #endif 308 } 309 310 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 311 { 312 CPUState *cs = CPU(dev); 313 RISCVCPU *cpu = RISCV_CPU(dev); 314 CPURISCVState *env = &cpu->env; 315 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 316 int priv_version = PRIV_VERSION_1_10_0; 317 int user_version = USER_VERSION_2_02_0; 318 Error *local_err = NULL; 319 320 cpu_exec_realizefn(cs, &local_err); 321 if (local_err != NULL) { 322 error_propagate(errp, local_err); 323 return; 324 } 325 326 if (cpu->cfg.priv_spec) { 327 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 328 priv_version = PRIV_VERSION_1_10_0; 329 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.9.1")) { 330 priv_version = PRIV_VERSION_1_09_1; 331 } else { 332 error_setg(errp, 333 "Unsupported privilege spec version '%s'", 334 cpu->cfg.priv_spec); 335 return; 336 } 337 } 338 339 if (cpu->cfg.user_spec) { 340 if (!g_strcmp0(cpu->cfg.user_spec, "v2.02.0")) { 341 user_version = USER_VERSION_2_02_0; 342 } else { 343 error_setg(errp, 344 "Unsupported user spec version '%s'", 345 cpu->cfg.user_spec); 346 return; 347 } 348 } 349 350 set_versions(env, user_version, priv_version); 351 set_resetvec(env, DEFAULT_RSTVEC); 352 353 if (cpu->cfg.mmu) { 354 set_feature(env, RISCV_FEATURE_MMU); 355 } 356 357 if (cpu->cfg.pmp) { 358 set_feature(env, RISCV_FEATURE_PMP); 359 } 360 361 riscv_cpu_register_gdb_regs_for_features(cs); 362 363 qemu_init_vcpu(cs); 364 cpu_reset(cs); 365 366 mcc->parent_realize(dev, errp); 367 } 368 369 static void riscv_cpu_init(Object *obj) 370 { 371 RISCVCPU *cpu = RISCV_CPU(obj); 372 373 cpu_set_cpustate_pointers(cpu); 374 } 375 376 static const VMStateDescription vmstate_riscv_cpu = { 377 .name = "cpu", 378 .unmigratable = 1, 379 }; 380 381 static Property riscv_cpu_properties[] = { 382 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 383 DEFINE_PROP_STRING("user_spec", RISCVCPU, cfg.user_spec), 384 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 385 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 386 DEFINE_PROP_END_OF_LIST(), 387 }; 388 389 static void riscv_cpu_class_init(ObjectClass *c, void *data) 390 { 391 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 392 CPUClass *cc = CPU_CLASS(c); 393 DeviceClass *dc = DEVICE_CLASS(c); 394 395 device_class_set_parent_realize(dc, riscv_cpu_realize, 396 &mcc->parent_realize); 397 398 mcc->parent_reset = cc->reset; 399 cc->reset = riscv_cpu_reset; 400 401 cc->class_by_name = riscv_cpu_class_by_name; 402 cc->has_work = riscv_cpu_has_work; 403 cc->do_interrupt = riscv_cpu_do_interrupt; 404 cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt; 405 cc->dump_state = riscv_cpu_dump_state; 406 cc->set_pc = riscv_cpu_set_pc; 407 cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb; 408 cc->gdb_read_register = riscv_cpu_gdb_read_register; 409 cc->gdb_write_register = riscv_cpu_gdb_write_register; 410 cc->gdb_num_core_regs = 33; 411 #if defined(TARGET_RISCV32) 412 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 413 #elif defined(TARGET_RISCV64) 414 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 415 #endif 416 cc->gdb_stop_before_watchpoint = true; 417 cc->disas_set_info = riscv_cpu_disas_set_info; 418 #ifndef CONFIG_USER_ONLY 419 cc->do_unaligned_access = riscv_cpu_do_unaligned_access; 420 cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; 421 #endif 422 #ifdef CONFIG_TCG 423 cc->tcg_initialize = riscv_translate_init; 424 cc->tlb_fill = riscv_cpu_tlb_fill; 425 #endif 426 /* For now, mark unmigratable: */ 427 cc->vmsd = &vmstate_riscv_cpu; 428 dc->props = riscv_cpu_properties; 429 } 430 431 char *riscv_isa_string(RISCVCPU *cpu) 432 { 433 int i; 434 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 435 char *isa_str = g_new(char, maxlen); 436 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 437 for (i = 0; i < sizeof(riscv_exts); i++) { 438 if (cpu->env.misa & RV(riscv_exts[i])) { 439 *p++ = qemu_tolower(riscv_exts[i]); 440 } 441 } 442 *p = '\0'; 443 return isa_str; 444 } 445 446 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 447 { 448 ObjectClass *class_a = (ObjectClass *)a; 449 ObjectClass *class_b = (ObjectClass *)b; 450 const char *name_a, *name_b; 451 452 name_a = object_class_get_name(class_a); 453 name_b = object_class_get_name(class_b); 454 return strcmp(name_a, name_b); 455 } 456 457 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 458 { 459 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 460 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 461 462 qemu_printf("%.*s\n", len, typename); 463 } 464 465 void riscv_cpu_list(void) 466 { 467 GSList *list; 468 469 list = object_class_get_list(TYPE_RISCV_CPU, false); 470 list = g_slist_sort(list, riscv_cpu_list_compare); 471 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 472 g_slist_free(list); 473 } 474 475 #define DEFINE_CPU(type_name, initfn) \ 476 { \ 477 .name = type_name, \ 478 .parent = TYPE_RISCV_CPU, \ 479 .instance_init = initfn \ 480 } 481 482 static const TypeInfo riscv_cpu_type_infos[] = { 483 { 484 .name = TYPE_RISCV_CPU, 485 .parent = TYPE_CPU, 486 .instance_size = sizeof(RISCVCPU), 487 .instance_init = riscv_cpu_init, 488 .abstract = true, 489 .class_size = sizeof(RISCVCPUClass), 490 .class_init = riscv_cpu_class_init, 491 }, 492 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 493 #if defined(TARGET_RISCV32) 494 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), 495 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init), 496 DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init), 497 DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), 498 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), 499 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init) 500 #elif defined(TARGET_RISCV64) 501 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), 502 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init), 503 DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init), 504 DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), 505 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), 506 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init) 507 #endif 508 }; 509 510 DEFINE_TYPES(riscv_cpu_type_infos) 511