1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "qemu/error-report.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "fpu/softfloat-helpers.h" 36 #include "sysemu/kvm.h" 37 #include "kvm_riscv.h" 38 #include "tcg/tcg.h" 39 40 /* RISC-V CPU definitions */ 41 42 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 43 (QEMU_VERSION_MINOR << 8) | \ 44 (QEMU_VERSION_MICRO)) 45 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 46 47 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 48 49 struct isa_ext_data { 50 const char *name; 51 int min_version; 52 int ext_enable_offset; 53 }; 54 55 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ 56 {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 57 58 /* 59 * Here are the ordering rules of extension naming defined by RISC-V 60 * specification : 61 * 1. All extensions should be separated from other multi-letter extensions 62 * by an underscore. 63 * 2. The first letter following the 'Z' conventionally indicates the most 64 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 65 * If multiple 'Z' extensions are named, they should be ordered first 66 * by category, then alphabetically within a category. 67 * 3. Standard supervisor-level extensions (starts with 'S') should be 68 * listed after standard unprivileged extensions. If multiple 69 * supervisor-level extensions are listed, they should be ordered 70 * alphabetically. 71 * 4. Non-standard extensions (starts with 'X') must be listed after all 72 * standard extensions. They must be separated from other multi-letter 73 * extensions by an underscore. 74 * 75 * Single letter extensions are checked in riscv_cpu_validate_misa_priv() 76 * instead. 77 */ 78 static const struct isa_ext_data isa_edata_arr[] = { 79 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), 80 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), 81 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), 82 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), 83 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), 84 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), 85 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), 86 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), 87 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), 88 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), 89 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), 90 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), 91 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), 92 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), 93 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), 94 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), 95 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), 96 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), 97 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), 98 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), 99 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), 100 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), 101 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), 102 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), 103 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), 104 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), 105 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), 106 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), 107 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), 108 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), 109 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), 110 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), 111 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), 112 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), 113 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), 114 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), 115 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), 116 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), 117 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), 118 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), 119 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), 120 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), 121 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), 122 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), 123 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), 124 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), 125 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), 126 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), 127 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), 128 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), 129 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), 130 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), 131 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), 132 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), 133 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 134 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 135 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), 136 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), 137 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 138 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), 139 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), 140 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 141 }; 142 143 static bool isa_ext_is_enabled(RISCVCPU *cpu, 144 const struct isa_ext_data *edata) 145 { 146 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 147 148 return *ext_enabled; 149 } 150 151 static void isa_ext_update_enabled(RISCVCPU *cpu, 152 const struct isa_ext_data *edata, bool en) 153 { 154 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 155 156 *ext_enabled = en; 157 } 158 159 const char * const riscv_int_regnames[] = { 160 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 161 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 162 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 163 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 164 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 165 }; 166 167 const char * const riscv_int_regnamesh[] = { 168 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 169 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 170 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 171 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 172 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 173 "x30h/t5h", "x31h/t6h" 174 }; 175 176 const char * const riscv_fpr_regnames[] = { 177 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 178 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 179 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 180 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 181 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 182 "f30/ft10", "f31/ft11" 183 }; 184 185 static const char * const riscv_excp_names[] = { 186 "misaligned_fetch", 187 "fault_fetch", 188 "illegal_instruction", 189 "breakpoint", 190 "misaligned_load", 191 "fault_load", 192 "misaligned_store", 193 "fault_store", 194 "user_ecall", 195 "supervisor_ecall", 196 "hypervisor_ecall", 197 "machine_ecall", 198 "exec_page_fault", 199 "load_page_fault", 200 "reserved", 201 "store_page_fault", 202 "reserved", 203 "reserved", 204 "reserved", 205 "reserved", 206 "guest_exec_page_fault", 207 "guest_load_page_fault", 208 "reserved", 209 "guest_store_page_fault", 210 }; 211 212 static const char * const riscv_intr_names[] = { 213 "u_software", 214 "s_software", 215 "vs_software", 216 "m_software", 217 "u_timer", 218 "s_timer", 219 "vs_timer", 220 "m_timer", 221 "u_external", 222 "s_external", 223 "vs_external", 224 "m_external", 225 "reserved", 226 "reserved", 227 "reserved", 228 "reserved" 229 }; 230 231 static void register_cpu_props(Object *obj); 232 233 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 234 { 235 if (async) { 236 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 237 riscv_intr_names[cause] : "(unknown)"; 238 } else { 239 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 240 riscv_excp_names[cause] : "(unknown)"; 241 } 242 } 243 244 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 245 { 246 env->misa_mxl_max = env->misa_mxl = mxl; 247 env->misa_ext_mask = env->misa_ext = ext; 248 } 249 250 static void set_priv_version(CPURISCVState *env, int priv_ver) 251 { 252 env->priv_ver = priv_ver; 253 } 254 255 static void set_vext_version(CPURISCVState *env, int vext_ver) 256 { 257 env->vext_ver = vext_ver; 258 } 259 260 #ifndef CONFIG_USER_ONLY 261 static uint8_t satp_mode_from_str(const char *satp_mode_str) 262 { 263 if (!strncmp(satp_mode_str, "mbare", 5)) { 264 return VM_1_10_MBARE; 265 } 266 267 if (!strncmp(satp_mode_str, "sv32", 4)) { 268 return VM_1_10_SV32; 269 } 270 271 if (!strncmp(satp_mode_str, "sv39", 4)) { 272 return VM_1_10_SV39; 273 } 274 275 if (!strncmp(satp_mode_str, "sv48", 4)) { 276 return VM_1_10_SV48; 277 } 278 279 if (!strncmp(satp_mode_str, "sv57", 4)) { 280 return VM_1_10_SV57; 281 } 282 283 if (!strncmp(satp_mode_str, "sv64", 4)) { 284 return VM_1_10_SV64; 285 } 286 287 g_assert_not_reached(); 288 } 289 290 uint8_t satp_mode_max_from_map(uint32_t map) 291 { 292 /* map here has at least one bit set, so no problem with clz */ 293 return 31 - __builtin_clz(map); 294 } 295 296 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) 297 { 298 if (is_32_bit) { 299 switch (satp_mode) { 300 case VM_1_10_SV32: 301 return "sv32"; 302 case VM_1_10_MBARE: 303 return "none"; 304 } 305 } else { 306 switch (satp_mode) { 307 case VM_1_10_SV64: 308 return "sv64"; 309 case VM_1_10_SV57: 310 return "sv57"; 311 case VM_1_10_SV48: 312 return "sv48"; 313 case VM_1_10_SV39: 314 return "sv39"; 315 case VM_1_10_MBARE: 316 return "none"; 317 } 318 } 319 320 g_assert_not_reached(); 321 } 322 323 static void set_satp_mode_max_supported(RISCVCPU *cpu, 324 uint8_t satp_mode) 325 { 326 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 327 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; 328 329 for (int i = 0; i <= satp_mode; ++i) { 330 if (valid_vm[i]) { 331 cpu->cfg.satp_mode.supported |= (1 << i); 332 } 333 } 334 } 335 336 /* Set the satp mode to the max supported */ 337 static void set_satp_mode_default_map(RISCVCPU *cpu) 338 { 339 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; 340 } 341 #endif 342 343 static void riscv_any_cpu_init(Object *obj) 344 { 345 CPURISCVState *env = &RISCV_CPU(obj)->env; 346 #if defined(TARGET_RISCV32) 347 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 348 #elif defined(TARGET_RISCV64) 349 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 350 #endif 351 352 #ifndef CONFIG_USER_ONLY 353 set_satp_mode_max_supported(RISCV_CPU(obj), 354 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? 355 VM_1_10_SV32 : VM_1_10_SV57); 356 #endif 357 358 set_priv_version(env, PRIV_VERSION_1_12_0); 359 register_cpu_props(obj); 360 } 361 362 #if defined(TARGET_RISCV64) 363 static void rv64_base_cpu_init(Object *obj) 364 { 365 CPURISCVState *env = &RISCV_CPU(obj)->env; 366 /* We set this in the realise function */ 367 set_misa(env, MXL_RV64, 0); 368 register_cpu_props(obj); 369 /* Set latest version of privileged specification */ 370 set_priv_version(env, PRIV_VERSION_1_12_0); 371 #ifndef CONFIG_USER_ONLY 372 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 373 #endif 374 } 375 376 static void rv64_sifive_u_cpu_init(Object *obj) 377 { 378 CPURISCVState *env = &RISCV_CPU(obj)->env; 379 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 380 register_cpu_props(obj); 381 set_priv_version(env, PRIV_VERSION_1_10_0); 382 #ifndef CONFIG_USER_ONLY 383 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); 384 #endif 385 } 386 387 static void rv64_sifive_e_cpu_init(Object *obj) 388 { 389 CPURISCVState *env = &RISCV_CPU(obj)->env; 390 RISCVCPU *cpu = RISCV_CPU(obj); 391 392 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 393 register_cpu_props(obj); 394 set_priv_version(env, PRIV_VERSION_1_10_0); 395 cpu->cfg.mmu = false; 396 #ifndef CONFIG_USER_ONLY 397 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 398 #endif 399 } 400 401 static void rv64_thead_c906_cpu_init(Object *obj) 402 { 403 CPURISCVState *env = &RISCV_CPU(obj)->env; 404 RISCVCPU *cpu = RISCV_CPU(obj); 405 406 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); 407 set_priv_version(env, PRIV_VERSION_1_11_0); 408 409 cpu->cfg.ext_zfh = true; 410 cpu->cfg.mmu = true; 411 cpu->cfg.ext_xtheadba = true; 412 cpu->cfg.ext_xtheadbb = true; 413 cpu->cfg.ext_xtheadbs = true; 414 cpu->cfg.ext_xtheadcmo = true; 415 cpu->cfg.ext_xtheadcondmov = true; 416 cpu->cfg.ext_xtheadfmemidx = true; 417 cpu->cfg.ext_xtheadmac = true; 418 cpu->cfg.ext_xtheadmemidx = true; 419 cpu->cfg.ext_xtheadmempair = true; 420 cpu->cfg.ext_xtheadsync = true; 421 422 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 423 #ifndef CONFIG_USER_ONLY 424 set_satp_mode_max_supported(cpu, VM_1_10_SV39); 425 #endif 426 } 427 428 static void rv128_base_cpu_init(Object *obj) 429 { 430 if (qemu_tcg_mttcg_enabled()) { 431 /* Missing 128-bit aligned atomics */ 432 error_report("128-bit RISC-V currently does not work with Multi " 433 "Threaded TCG. Please use: -accel tcg,thread=single"); 434 exit(EXIT_FAILURE); 435 } 436 CPURISCVState *env = &RISCV_CPU(obj)->env; 437 /* We set this in the realise function */ 438 set_misa(env, MXL_RV128, 0); 439 register_cpu_props(obj); 440 /* Set latest version of privileged specification */ 441 set_priv_version(env, PRIV_VERSION_1_12_0); 442 #ifndef CONFIG_USER_ONLY 443 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 444 #endif 445 } 446 #else 447 static void rv32_base_cpu_init(Object *obj) 448 { 449 CPURISCVState *env = &RISCV_CPU(obj)->env; 450 /* We set this in the realise function */ 451 set_misa(env, MXL_RV32, 0); 452 register_cpu_props(obj); 453 /* Set latest version of privileged specification */ 454 set_priv_version(env, PRIV_VERSION_1_12_0); 455 #ifndef CONFIG_USER_ONLY 456 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 457 #endif 458 } 459 460 static void rv32_sifive_u_cpu_init(Object *obj) 461 { 462 CPURISCVState *env = &RISCV_CPU(obj)->env; 463 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 464 register_cpu_props(obj); 465 set_priv_version(env, PRIV_VERSION_1_10_0); 466 #ifndef CONFIG_USER_ONLY 467 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 468 #endif 469 } 470 471 static void rv32_sifive_e_cpu_init(Object *obj) 472 { 473 CPURISCVState *env = &RISCV_CPU(obj)->env; 474 RISCVCPU *cpu = RISCV_CPU(obj); 475 476 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 477 register_cpu_props(obj); 478 set_priv_version(env, PRIV_VERSION_1_10_0); 479 cpu->cfg.mmu = false; 480 #ifndef CONFIG_USER_ONLY 481 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 482 #endif 483 } 484 485 static void rv32_ibex_cpu_init(Object *obj) 486 { 487 CPURISCVState *env = &RISCV_CPU(obj)->env; 488 RISCVCPU *cpu = RISCV_CPU(obj); 489 490 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 491 register_cpu_props(obj); 492 set_priv_version(env, PRIV_VERSION_1_11_0); 493 cpu->cfg.mmu = false; 494 #ifndef CONFIG_USER_ONLY 495 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 496 #endif 497 cpu->cfg.epmp = true; 498 } 499 500 static void rv32_imafcu_nommu_cpu_init(Object *obj) 501 { 502 CPURISCVState *env = &RISCV_CPU(obj)->env; 503 RISCVCPU *cpu = RISCV_CPU(obj); 504 505 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 506 register_cpu_props(obj); 507 set_priv_version(env, PRIV_VERSION_1_10_0); 508 cpu->cfg.mmu = false; 509 #ifndef CONFIG_USER_ONLY 510 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 511 #endif 512 } 513 #endif 514 515 #if defined(CONFIG_KVM) 516 static void riscv_host_cpu_init(Object *obj) 517 { 518 CPURISCVState *env = &RISCV_CPU(obj)->env; 519 #if defined(TARGET_RISCV32) 520 set_misa(env, MXL_RV32, 0); 521 #elif defined(TARGET_RISCV64) 522 set_misa(env, MXL_RV64, 0); 523 #endif 524 register_cpu_props(obj); 525 } 526 #endif 527 528 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 529 { 530 ObjectClass *oc; 531 char *typename; 532 char **cpuname; 533 534 cpuname = g_strsplit(cpu_model, ",", 1); 535 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 536 oc = object_class_by_name(typename); 537 g_strfreev(cpuname); 538 g_free(typename); 539 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 540 object_class_is_abstract(oc)) { 541 return NULL; 542 } 543 return oc; 544 } 545 546 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 547 { 548 RISCVCPU *cpu = RISCV_CPU(cs); 549 CPURISCVState *env = &cpu->env; 550 int i; 551 552 #if !defined(CONFIG_USER_ONLY) 553 if (riscv_has_ext(env, RVH)) { 554 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); 555 } 556 #endif 557 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 558 #ifndef CONFIG_USER_ONLY 559 { 560 static const int dump_csrs[] = { 561 CSR_MHARTID, 562 CSR_MSTATUS, 563 CSR_MSTATUSH, 564 /* 565 * CSR_SSTATUS is intentionally omitted here as its value 566 * can be figured out by looking at CSR_MSTATUS 567 */ 568 CSR_HSTATUS, 569 CSR_VSSTATUS, 570 CSR_MIP, 571 CSR_MIE, 572 CSR_MIDELEG, 573 CSR_HIDELEG, 574 CSR_MEDELEG, 575 CSR_HEDELEG, 576 CSR_MTVEC, 577 CSR_STVEC, 578 CSR_VSTVEC, 579 CSR_MEPC, 580 CSR_SEPC, 581 CSR_VSEPC, 582 CSR_MCAUSE, 583 CSR_SCAUSE, 584 CSR_VSCAUSE, 585 CSR_MTVAL, 586 CSR_STVAL, 587 CSR_HTVAL, 588 CSR_MTVAL2, 589 CSR_MSCRATCH, 590 CSR_SSCRATCH, 591 CSR_SATP, 592 CSR_MMTE, 593 CSR_UPMBASE, 594 CSR_UPMMASK, 595 CSR_SPMBASE, 596 CSR_SPMMASK, 597 CSR_MPMBASE, 598 CSR_MPMMASK, 599 }; 600 601 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 602 int csrno = dump_csrs[i]; 603 target_ulong val = 0; 604 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 605 606 /* 607 * Rely on the smode, hmode, etc, predicates within csr.c 608 * to do the filtering of the registers that are present. 609 */ 610 if (res == RISCV_EXCP_NONE) { 611 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 612 csr_ops[csrno].name, val); 613 } 614 } 615 } 616 #endif 617 618 for (i = 0; i < 32; i++) { 619 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 620 riscv_int_regnames[i], env->gpr[i]); 621 if ((i & 3) == 3) { 622 qemu_fprintf(f, "\n"); 623 } 624 } 625 if (flags & CPU_DUMP_FPU) { 626 for (i = 0; i < 32; i++) { 627 qemu_fprintf(f, " %-8s %016" PRIx64, 628 riscv_fpr_regnames[i], env->fpr[i]); 629 if ((i & 3) == 3) { 630 qemu_fprintf(f, "\n"); 631 } 632 } 633 } 634 } 635 636 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 637 { 638 RISCVCPU *cpu = RISCV_CPU(cs); 639 CPURISCVState *env = &cpu->env; 640 641 if (env->xl == MXL_RV32) { 642 env->pc = (int32_t)value; 643 } else { 644 env->pc = value; 645 } 646 } 647 648 static vaddr riscv_cpu_get_pc(CPUState *cs) 649 { 650 RISCVCPU *cpu = RISCV_CPU(cs); 651 CPURISCVState *env = &cpu->env; 652 653 /* Match cpu_get_tb_cpu_state. */ 654 if (env->xl == MXL_RV32) { 655 return env->pc & UINT32_MAX; 656 } 657 return env->pc; 658 } 659 660 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 661 const TranslationBlock *tb) 662 { 663 RISCVCPU *cpu = RISCV_CPU(cs); 664 CPURISCVState *env = &cpu->env; 665 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 666 667 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 668 669 if (xl == MXL_RV32) { 670 env->pc = (int32_t) tb->pc; 671 } else { 672 env->pc = tb->pc; 673 } 674 } 675 676 static bool riscv_cpu_has_work(CPUState *cs) 677 { 678 #ifndef CONFIG_USER_ONLY 679 RISCVCPU *cpu = RISCV_CPU(cs); 680 CPURISCVState *env = &cpu->env; 681 /* 682 * Definition of the WFI instruction requires it to ignore the privilege 683 * mode and delegation registers, but respect individual enables 684 */ 685 return riscv_cpu_all_pending(env) != 0; 686 #else 687 return true; 688 #endif 689 } 690 691 static void riscv_restore_state_to_opc(CPUState *cs, 692 const TranslationBlock *tb, 693 const uint64_t *data) 694 { 695 RISCVCPU *cpu = RISCV_CPU(cs); 696 CPURISCVState *env = &cpu->env; 697 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 698 699 if (xl == MXL_RV32) { 700 env->pc = (int32_t)data[0]; 701 } else { 702 env->pc = data[0]; 703 } 704 env->bins = data[1]; 705 } 706 707 static void riscv_cpu_reset_hold(Object *obj) 708 { 709 #ifndef CONFIG_USER_ONLY 710 uint8_t iprio; 711 int i, irq, rdzero; 712 #endif 713 CPUState *cs = CPU(obj); 714 RISCVCPU *cpu = RISCV_CPU(cs); 715 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 716 CPURISCVState *env = &cpu->env; 717 718 if (mcc->parent_phases.hold) { 719 mcc->parent_phases.hold(obj); 720 } 721 #ifndef CONFIG_USER_ONLY 722 env->misa_mxl = env->misa_mxl_max; 723 env->priv = PRV_M; 724 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 725 if (env->misa_mxl > MXL_RV32) { 726 /* 727 * The reset status of SXL/UXL is undefined, but mstatus is WARL 728 * and we must ensure that the value after init is valid for read. 729 */ 730 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 731 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 732 if (riscv_has_ext(env, RVH)) { 733 env->vsstatus = set_field(env->vsstatus, 734 MSTATUS64_SXL, env->misa_mxl); 735 env->vsstatus = set_field(env->vsstatus, 736 MSTATUS64_UXL, env->misa_mxl); 737 env->mstatus_hs = set_field(env->mstatus_hs, 738 MSTATUS64_SXL, env->misa_mxl); 739 env->mstatus_hs = set_field(env->mstatus_hs, 740 MSTATUS64_UXL, env->misa_mxl); 741 } 742 } 743 env->mcause = 0; 744 env->miclaim = MIP_SGEIP; 745 env->pc = env->resetvec; 746 env->bins = 0; 747 env->two_stage_lookup = false; 748 749 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | 750 (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); 751 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | 752 (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); 753 754 /* Initialized default priorities of local interrupts. */ 755 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 756 iprio = riscv_cpu_default_priority(i); 757 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 758 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 759 env->hviprio[i] = 0; 760 } 761 i = 0; 762 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 763 if (!rdzero) { 764 env->hviprio[irq] = env->miprio[irq]; 765 } 766 i++; 767 } 768 /* mmte is supposed to have pm.current hardwired to 1 */ 769 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 770 #endif 771 env->xl = riscv_cpu_mxl(env); 772 riscv_cpu_update_mask(env); 773 cs->exception_index = RISCV_EXCP_NONE; 774 env->load_res = -1; 775 set_default_nan_mode(1, &env->fp_status); 776 777 #ifndef CONFIG_USER_ONLY 778 if (cpu->cfg.debug) { 779 riscv_trigger_init(env); 780 } 781 782 if (kvm_enabled()) { 783 kvm_riscv_reset_vcpu(cpu); 784 } 785 #endif 786 } 787 788 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 789 { 790 RISCVCPU *cpu = RISCV_CPU(s); 791 792 switch (riscv_cpu_mxl(&cpu->env)) { 793 case MXL_RV32: 794 info->print_insn = print_insn_riscv32; 795 break; 796 case MXL_RV64: 797 info->print_insn = print_insn_riscv64; 798 break; 799 case MXL_RV128: 800 info->print_insn = print_insn_riscv128; 801 break; 802 default: 803 g_assert_not_reached(); 804 } 805 } 806 807 /* 808 * Check consistency between chosen extensions while setting 809 * cpu->cfg accordingly. 810 */ 811 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 812 { 813 CPURISCVState *env = &cpu->env; 814 815 /* Do some ISA extension error checking */ 816 if (riscv_has_ext(env, RVG) && 817 !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && 818 riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && 819 riscv_has_ext(env, RVD) && 820 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 821 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 822 cpu->cfg.ext_icsr = true; 823 cpu->cfg.ext_ifencei = true; 824 825 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; 826 env->misa_ext_mask = env->misa_ext; 827 } 828 829 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 830 error_setg(errp, 831 "I and E extensions are incompatible"); 832 return; 833 } 834 835 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 836 error_setg(errp, 837 "Either I or E extension must be set"); 838 return; 839 } 840 841 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 842 error_setg(errp, 843 "Setting S extension without U extension is illegal"); 844 return; 845 } 846 847 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 848 error_setg(errp, 849 "H depends on an I base integer ISA with 32 x registers"); 850 return; 851 } 852 853 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 854 error_setg(errp, "H extension implicitly requires S-mode"); 855 return; 856 } 857 858 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { 859 error_setg(errp, "F extension requires Zicsr"); 860 return; 861 } 862 863 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 864 error_setg(errp, "Zawrs extension requires A extension"); 865 return; 866 } 867 868 if (cpu->cfg.ext_zfh) { 869 cpu->cfg.ext_zfhmin = true; 870 } 871 872 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 873 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 874 return; 875 } 876 877 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 878 error_setg(errp, "D extension requires F extension"); 879 return; 880 } 881 882 /* The V vector extension depends on the Zve64d extension */ 883 if (riscv_has_ext(env, RVV)) { 884 cpu->cfg.ext_zve64d = true; 885 } 886 887 /* The Zve64d extension depends on the Zve64f extension */ 888 if (cpu->cfg.ext_zve64d) { 889 cpu->cfg.ext_zve64f = true; 890 } 891 892 /* The Zve64f extension depends on the Zve32f extension */ 893 if (cpu->cfg.ext_zve64f) { 894 cpu->cfg.ext_zve32f = true; 895 } 896 897 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 898 error_setg(errp, "Zve64d/V extensions require D extension"); 899 return; 900 } 901 902 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 903 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 904 return; 905 } 906 907 if (cpu->cfg.ext_zvfh) { 908 cpu->cfg.ext_zvfhmin = true; 909 } 910 911 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 912 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 913 return; 914 } 915 916 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 917 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 918 return; 919 } 920 921 /* Set the ISA extensions, checks should have happened above */ 922 if (cpu->cfg.ext_zhinx) { 923 cpu->cfg.ext_zhinxmin = true; 924 } 925 926 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { 927 cpu->cfg.ext_zfinx = true; 928 } 929 930 if (cpu->cfg.ext_zfinx) { 931 if (!cpu->cfg.ext_icsr) { 932 error_setg(errp, "Zfinx extension requires Zicsr"); 933 return; 934 } 935 if (riscv_has_ext(env, RVF)) { 936 error_setg(errp, 937 "Zfinx cannot be supported together with F extension"); 938 return; 939 } 940 } 941 942 if (cpu->cfg.ext_zce) { 943 cpu->cfg.ext_zca = true; 944 cpu->cfg.ext_zcb = true; 945 cpu->cfg.ext_zcmp = true; 946 cpu->cfg.ext_zcmt = true; 947 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 948 cpu->cfg.ext_zcf = true; 949 } 950 } 951 952 if (riscv_has_ext(env, RVC)) { 953 cpu->cfg.ext_zca = true; 954 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 955 cpu->cfg.ext_zcf = true; 956 } 957 if (riscv_has_ext(env, RVD)) { 958 cpu->cfg.ext_zcd = true; 959 } 960 } 961 962 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 963 error_setg(errp, "Zcf extension is only relevant to RV32"); 964 return; 965 } 966 967 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 968 error_setg(errp, "Zcf extension requires F extension"); 969 return; 970 } 971 972 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 973 error_setg(errp, "Zcd extension requires D extension"); 974 return; 975 } 976 977 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 978 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 979 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 980 "extension"); 981 return; 982 } 983 984 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 985 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 986 "Zcd extension"); 987 return; 988 } 989 990 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { 991 error_setg(errp, "Zcmt extension requires Zicsr extension"); 992 return; 993 } 994 995 if (cpu->cfg.ext_zk) { 996 cpu->cfg.ext_zkn = true; 997 cpu->cfg.ext_zkr = true; 998 cpu->cfg.ext_zkt = true; 999 } 1000 1001 if (cpu->cfg.ext_zkn) { 1002 cpu->cfg.ext_zbkb = true; 1003 cpu->cfg.ext_zbkc = true; 1004 cpu->cfg.ext_zbkx = true; 1005 cpu->cfg.ext_zkne = true; 1006 cpu->cfg.ext_zknd = true; 1007 cpu->cfg.ext_zknh = true; 1008 } 1009 1010 if (cpu->cfg.ext_zks) { 1011 cpu->cfg.ext_zbkb = true; 1012 cpu->cfg.ext_zbkc = true; 1013 cpu->cfg.ext_zbkx = true; 1014 cpu->cfg.ext_zksed = true; 1015 cpu->cfg.ext_zksh = true; 1016 } 1017 1018 if (riscv_has_ext(env, RVV)) { 1019 int vext_version = VEXT_VERSION_1_00_0; 1020 if (!is_power_of_2(cpu->cfg.vlen)) { 1021 error_setg(errp, 1022 "Vector extension VLEN must be power of 2"); 1023 return; 1024 } 1025 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 1026 error_setg(errp, 1027 "Vector extension implementation only supports VLEN " 1028 "in the range [128, %d]", RV_VLEN_MAX); 1029 return; 1030 } 1031 if (!is_power_of_2(cpu->cfg.elen)) { 1032 error_setg(errp, 1033 "Vector extension ELEN must be power of 2"); 1034 return; 1035 } 1036 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 1037 error_setg(errp, 1038 "Vector extension implementation only supports ELEN " 1039 "in the range [8, 64]"); 1040 return; 1041 } 1042 if (cpu->cfg.vext_spec) { 1043 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 1044 vext_version = VEXT_VERSION_1_00_0; 1045 } else { 1046 error_setg(errp, 1047 "Unsupported vector spec version '%s'", 1048 cpu->cfg.vext_spec); 1049 return; 1050 } 1051 } else { 1052 qemu_log("vector version is not specified, " 1053 "use the default value v1.0\n"); 1054 } 1055 set_vext_version(env, vext_version); 1056 } 1057 } 1058 1059 #ifndef CONFIG_USER_ONLY 1060 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) 1061 { 1062 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 1063 uint8_t satp_mode_map_max; 1064 uint8_t satp_mode_supported_max = 1065 satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 1066 1067 if (cpu->cfg.satp_mode.map == 0) { 1068 if (cpu->cfg.satp_mode.init == 0) { 1069 /* If unset by the user, we fallback to the default satp mode. */ 1070 set_satp_mode_default_map(cpu); 1071 } else { 1072 /* 1073 * Find the lowest level that was disabled and then enable the 1074 * first valid level below which can be found in 1075 * valid_vm_1_10_32/64. 1076 */ 1077 for (int i = 1; i < 16; ++i) { 1078 if ((cpu->cfg.satp_mode.init & (1 << i)) && 1079 (cpu->cfg.satp_mode.supported & (1 << i))) { 1080 for (int j = i - 1; j >= 0; --j) { 1081 if (cpu->cfg.satp_mode.supported & (1 << j)) { 1082 cpu->cfg.satp_mode.map |= (1 << j); 1083 break; 1084 } 1085 } 1086 break; 1087 } 1088 } 1089 } 1090 } 1091 1092 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 1093 1094 /* Make sure the user asked for a supported configuration (HW and qemu) */ 1095 if (satp_mode_map_max > satp_mode_supported_max) { 1096 error_setg(errp, "satp_mode %s is higher than hw max capability %s", 1097 satp_mode_str(satp_mode_map_max, rv32), 1098 satp_mode_str(satp_mode_supported_max, rv32)); 1099 return; 1100 } 1101 1102 /* 1103 * Make sure the user did not ask for an invalid configuration as per 1104 * the specification. 1105 */ 1106 if (!rv32) { 1107 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1108 if (!(cpu->cfg.satp_mode.map & (1 << i)) && 1109 (cpu->cfg.satp_mode.init & (1 << i)) && 1110 (cpu->cfg.satp_mode.supported & (1 << i))) { 1111 error_setg(errp, "cannot disable %s satp mode if %s " 1112 "is enabled", satp_mode_str(i, false), 1113 satp_mode_str(satp_mode_map_max, false)); 1114 return; 1115 } 1116 } 1117 } 1118 1119 /* Finally expand the map so that all valid modes are set */ 1120 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1121 if (cpu->cfg.satp_mode.supported & (1 << i)) { 1122 cpu->cfg.satp_mode.map |= (1 << i); 1123 } 1124 } 1125 } 1126 #endif 1127 1128 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1129 { 1130 #ifndef CONFIG_USER_ONLY 1131 Error *local_err = NULL; 1132 1133 riscv_cpu_satp_mode_finalize(cpu, &local_err); 1134 if (local_err != NULL) { 1135 error_propagate(errp, local_err); 1136 return; 1137 } 1138 #endif 1139 } 1140 1141 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 1142 { 1143 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 1144 error_setg(errp, "H extension requires priv spec 1.12.0"); 1145 return; 1146 } 1147 } 1148 1149 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 1150 { 1151 CPUState *cs = CPU(dev); 1152 RISCVCPU *cpu = RISCV_CPU(dev); 1153 CPURISCVState *env = &cpu->env; 1154 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 1155 CPUClass *cc = CPU_CLASS(mcc); 1156 int i, priv_version = -1; 1157 Error *local_err = NULL; 1158 1159 cpu_exec_realizefn(cs, &local_err); 1160 if (local_err != NULL) { 1161 error_propagate(errp, local_err); 1162 return; 1163 } 1164 1165 if (cpu->cfg.priv_spec) { 1166 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 1167 priv_version = PRIV_VERSION_1_12_0; 1168 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 1169 priv_version = PRIV_VERSION_1_11_0; 1170 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 1171 priv_version = PRIV_VERSION_1_10_0; 1172 } else { 1173 error_setg(errp, 1174 "Unsupported privilege spec version '%s'", 1175 cpu->cfg.priv_spec); 1176 return; 1177 } 1178 } 1179 1180 if (priv_version >= PRIV_VERSION_1_10_0) { 1181 set_priv_version(env, priv_version); 1182 } 1183 1184 riscv_cpu_validate_misa_priv(env, &local_err); 1185 if (local_err != NULL) { 1186 error_propagate(errp, local_err); 1187 return; 1188 } 1189 1190 /* Force disable extensions if priv spec version does not match */ 1191 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1192 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 1193 (env->priv_ver < isa_edata_arr[i].min_version)) { 1194 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 1195 #ifndef CONFIG_USER_ONLY 1196 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 1197 " because privilege spec version does not match", 1198 isa_edata_arr[i].name, env->mhartid); 1199 #else 1200 warn_report("disabling %s extension because " 1201 "privilege spec version does not match", 1202 isa_edata_arr[i].name); 1203 #endif 1204 } 1205 } 1206 1207 if (cpu->cfg.epmp && !cpu->cfg.pmp) { 1208 /* 1209 * Enhanced PMP should only be available 1210 * on harts with PMP support 1211 */ 1212 error_setg(errp, "Invalid configuration: EPMP requires PMP support"); 1213 return; 1214 } 1215 1216 1217 #ifndef CONFIG_USER_ONLY 1218 if (cpu->cfg.ext_sstc) { 1219 riscv_timer_init(cpu); 1220 } 1221 #endif /* CONFIG_USER_ONLY */ 1222 1223 /* Validate that MISA_MXL is set properly. */ 1224 switch (env->misa_mxl_max) { 1225 #ifdef TARGET_RISCV64 1226 case MXL_RV64: 1227 case MXL_RV128: 1228 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 1229 break; 1230 #endif 1231 case MXL_RV32: 1232 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 1233 break; 1234 default: 1235 g_assert_not_reached(); 1236 } 1237 assert(env->misa_mxl_max == env->misa_mxl); 1238 1239 riscv_cpu_validate_set_extensions(cpu, &local_err); 1240 if (local_err != NULL) { 1241 error_propagate(errp, local_err); 1242 return; 1243 } 1244 1245 #ifndef CONFIG_USER_ONLY 1246 if (cpu->cfg.pmu_num) { 1247 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 1248 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1249 riscv_pmu_timer_cb, cpu); 1250 } 1251 } 1252 #endif 1253 1254 riscv_cpu_finalize_features(cpu, &local_err); 1255 if (local_err != NULL) { 1256 error_propagate(errp, local_err); 1257 return; 1258 } 1259 1260 riscv_cpu_register_gdb_regs_for_features(cs); 1261 1262 qemu_init_vcpu(cs); 1263 cpu_reset(cs); 1264 1265 mcc->parent_realize(dev, errp); 1266 } 1267 1268 #ifndef CONFIG_USER_ONLY 1269 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, 1270 void *opaque, Error **errp) 1271 { 1272 RISCVSATPMap *satp_map = opaque; 1273 uint8_t satp = satp_mode_from_str(name); 1274 bool value; 1275 1276 value = satp_map->map & (1 << satp); 1277 1278 visit_type_bool(v, name, &value, errp); 1279 } 1280 1281 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, 1282 void *opaque, Error **errp) 1283 { 1284 RISCVSATPMap *satp_map = opaque; 1285 uint8_t satp = satp_mode_from_str(name); 1286 bool value; 1287 1288 if (!visit_type_bool(v, name, &value, errp)) { 1289 return; 1290 } 1291 1292 satp_map->map = deposit32(satp_map->map, satp, 1, value); 1293 satp_map->init |= 1 << satp; 1294 } 1295 1296 static void riscv_add_satp_mode_properties(Object *obj) 1297 { 1298 RISCVCPU *cpu = RISCV_CPU(obj); 1299 1300 if (cpu->env.misa_mxl == MXL_RV32) { 1301 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, 1302 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1303 } else { 1304 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, 1305 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1306 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, 1307 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1308 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, 1309 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1310 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, 1311 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1312 } 1313 } 1314 1315 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1316 { 1317 RISCVCPU *cpu = RISCV_CPU(opaque); 1318 CPURISCVState *env = &cpu->env; 1319 1320 if (irq < IRQ_LOCAL_MAX) { 1321 switch (irq) { 1322 case IRQ_U_SOFT: 1323 case IRQ_S_SOFT: 1324 case IRQ_VS_SOFT: 1325 case IRQ_M_SOFT: 1326 case IRQ_U_TIMER: 1327 case IRQ_S_TIMER: 1328 case IRQ_VS_TIMER: 1329 case IRQ_M_TIMER: 1330 case IRQ_U_EXT: 1331 case IRQ_VS_EXT: 1332 case IRQ_M_EXT: 1333 if (kvm_enabled()) { 1334 kvm_riscv_set_irq(cpu, irq, level); 1335 } else { 1336 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); 1337 } 1338 break; 1339 case IRQ_S_EXT: 1340 if (kvm_enabled()) { 1341 kvm_riscv_set_irq(cpu, irq, level); 1342 } else { 1343 env->external_seip = level; 1344 riscv_cpu_update_mip(env, 1 << irq, 1345 BOOL_TO_MASK(level | env->software_seip)); 1346 } 1347 break; 1348 default: 1349 g_assert_not_reached(); 1350 } 1351 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1352 /* Require H-extension for handling guest local interrupts */ 1353 if (!riscv_has_ext(env, RVH)) { 1354 g_assert_not_reached(); 1355 } 1356 1357 /* Compute bit position in HGEIP CSR */ 1358 irq = irq - IRQ_LOCAL_MAX + 1; 1359 if (env->geilen < irq) { 1360 g_assert_not_reached(); 1361 } 1362 1363 /* Update HGEIP CSR */ 1364 env->hgeip &= ~((target_ulong)1 << irq); 1365 if (level) { 1366 env->hgeip |= (target_ulong)1 << irq; 1367 } 1368 1369 /* Update mip.SGEIP bit */ 1370 riscv_cpu_update_mip(env, MIP_SGEIP, 1371 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1372 } else { 1373 g_assert_not_reached(); 1374 } 1375 } 1376 #endif /* CONFIG_USER_ONLY */ 1377 1378 static void riscv_cpu_init(Object *obj) 1379 { 1380 RISCVCPU *cpu = RISCV_CPU(obj); 1381 1382 cpu->cfg.ext_ifencei = true; 1383 cpu->cfg.ext_icsr = true; 1384 cpu->cfg.mmu = true; 1385 cpu->cfg.pmp = true; 1386 1387 cpu_set_cpustate_pointers(cpu); 1388 1389 #ifndef CONFIG_USER_ONLY 1390 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1391 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1392 #endif /* CONFIG_USER_ONLY */ 1393 } 1394 1395 typedef struct RISCVCPUMisaExtConfig { 1396 const char *name; 1397 const char *description; 1398 target_ulong misa_bit; 1399 bool enabled; 1400 } RISCVCPUMisaExtConfig; 1401 1402 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1403 void *opaque, Error **errp) 1404 { 1405 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1406 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1407 RISCVCPU *cpu = RISCV_CPU(obj); 1408 CPURISCVState *env = &cpu->env; 1409 bool value; 1410 1411 if (!visit_type_bool(v, name, &value, errp)) { 1412 return; 1413 } 1414 1415 if (value) { 1416 env->misa_ext |= misa_bit; 1417 env->misa_ext_mask |= misa_bit; 1418 } else { 1419 env->misa_ext &= ~misa_bit; 1420 env->misa_ext_mask &= ~misa_bit; 1421 } 1422 } 1423 1424 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1425 void *opaque, Error **errp) 1426 { 1427 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1428 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1429 RISCVCPU *cpu = RISCV_CPU(obj); 1430 CPURISCVState *env = &cpu->env; 1431 bool value; 1432 1433 value = env->misa_ext & misa_bit; 1434 1435 visit_type_bool(v, name, &value, errp); 1436 } 1437 1438 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1439 {.name = "a", .description = "Atomic instructions", 1440 .misa_bit = RVA, .enabled = true}, 1441 {.name = "c", .description = "Compressed instructions", 1442 .misa_bit = RVC, .enabled = true}, 1443 {.name = "d", .description = "Double-precision float point", 1444 .misa_bit = RVD, .enabled = true}, 1445 {.name = "f", .description = "Single-precision float point", 1446 .misa_bit = RVF, .enabled = true}, 1447 {.name = "i", .description = "Base integer instruction set", 1448 .misa_bit = RVI, .enabled = true}, 1449 {.name = "e", .description = "Base integer instruction set (embedded)", 1450 .misa_bit = RVE, .enabled = false}, 1451 {.name = "m", .description = "Integer multiplication and division", 1452 .misa_bit = RVM, .enabled = true}, 1453 {.name = "s", .description = "Supervisor-level instructions", 1454 .misa_bit = RVS, .enabled = true}, 1455 {.name = "u", .description = "User-level instructions", 1456 .misa_bit = RVU, .enabled = true}, 1457 {.name = "h", .description = "Hypervisor", 1458 .misa_bit = RVH, .enabled = true}, 1459 {.name = "x-j", .description = "Dynamic translated languages", 1460 .misa_bit = RVJ, .enabled = false}, 1461 {.name = "v", .description = "Vector operations", 1462 .misa_bit = RVV, .enabled = false}, 1463 {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)", 1464 .misa_bit = RVG, .enabled = false}, 1465 }; 1466 1467 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1468 { 1469 int i; 1470 1471 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1472 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1473 1474 object_property_add(cpu_obj, misa_cfg->name, "bool", 1475 cpu_get_misa_ext_cfg, 1476 cpu_set_misa_ext_cfg, 1477 NULL, (void *)misa_cfg); 1478 object_property_set_description(cpu_obj, misa_cfg->name, 1479 misa_cfg->description); 1480 object_property_set_bool(cpu_obj, misa_cfg->name, 1481 misa_cfg->enabled, NULL); 1482 } 1483 } 1484 1485 static Property riscv_cpu_extensions[] = { 1486 /* Defaults for standard extensions */ 1487 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1488 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1489 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1490 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1491 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1492 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1493 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1494 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1495 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1496 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1497 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), 1498 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1499 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1500 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1501 1502 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1503 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1504 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1505 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1506 1507 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), 1508 1509 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1510 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1511 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1512 1513 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1514 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1515 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1516 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1517 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1518 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1519 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1520 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1521 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1522 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1523 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1524 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1525 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1526 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1527 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1528 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1529 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1530 1531 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1532 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1533 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1534 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1535 1536 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), 1537 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), 1538 DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), 1539 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), 1540 1541 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1542 1543 /* Vendor-specific custom extensions */ 1544 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1545 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1546 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1547 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1548 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1549 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1550 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1551 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1552 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1553 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1554 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1555 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1556 1557 /* These are experimental so mark with 'x-' */ 1558 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), 1559 1560 DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), 1561 DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), 1562 DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), 1563 DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), 1564 DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), 1565 DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), 1566 DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), 1567 1568 /* ePMP 0.9.3 */ 1569 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1570 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1571 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1572 1573 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), 1574 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), 1575 1576 DEFINE_PROP_END_OF_LIST(), 1577 }; 1578 1579 /* 1580 * Register CPU props based on env.misa_ext. If a non-zero 1581 * value was set, register only the required cpu->cfg.ext_* 1582 * properties and leave. env.misa_ext = 0 means that we want 1583 * all the default properties to be registered. 1584 */ 1585 static void register_cpu_props(Object *obj) 1586 { 1587 RISCVCPU *cpu = RISCV_CPU(obj); 1588 Property *prop; 1589 DeviceState *dev = DEVICE(obj); 1590 1591 /* 1592 * If misa_ext is not zero, set cfg properties now to 1593 * allow them to be read during riscv_cpu_realize() 1594 * later on. 1595 */ 1596 if (cpu->env.misa_ext != 0) { 1597 /* 1598 * We don't want to set the default riscv_cpu_extensions 1599 * in this case. 1600 */ 1601 return; 1602 } 1603 1604 riscv_cpu_add_misa_properties(obj); 1605 1606 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1607 qdev_property_add_static(dev, prop); 1608 } 1609 1610 #ifndef CONFIG_USER_ONLY 1611 riscv_add_satp_mode_properties(obj); 1612 #endif 1613 } 1614 1615 static Property riscv_cpu_properties[] = { 1616 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1617 1618 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1619 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1620 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1621 1622 #ifndef CONFIG_USER_ONLY 1623 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1624 #endif 1625 1626 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1627 1628 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1629 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1630 1631 /* 1632 * write_misa() is marked as experimental for now so mark 1633 * it with -x and default to 'false'. 1634 */ 1635 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1636 DEFINE_PROP_END_OF_LIST(), 1637 }; 1638 1639 static gchar *riscv_gdb_arch_name(CPUState *cs) 1640 { 1641 RISCVCPU *cpu = RISCV_CPU(cs); 1642 CPURISCVState *env = &cpu->env; 1643 1644 switch (riscv_cpu_mxl(env)) { 1645 case MXL_RV32: 1646 return g_strdup("riscv:rv32"); 1647 case MXL_RV64: 1648 case MXL_RV128: 1649 return g_strdup("riscv:rv64"); 1650 default: 1651 g_assert_not_reached(); 1652 } 1653 } 1654 1655 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1656 { 1657 RISCVCPU *cpu = RISCV_CPU(cs); 1658 1659 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1660 return cpu->dyn_csr_xml; 1661 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1662 return cpu->dyn_vreg_xml; 1663 } 1664 1665 return NULL; 1666 } 1667 1668 #ifndef CONFIG_USER_ONLY 1669 static int64_t riscv_get_arch_id(CPUState *cs) 1670 { 1671 RISCVCPU *cpu = RISCV_CPU(cs); 1672 1673 return cpu->env.mhartid; 1674 } 1675 1676 #include "hw/core/sysemu-cpu-ops.h" 1677 1678 static const struct SysemuCPUOps riscv_sysemu_ops = { 1679 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1680 .write_elf64_note = riscv_cpu_write_elf64_note, 1681 .write_elf32_note = riscv_cpu_write_elf32_note, 1682 .legacy_vmsd = &vmstate_riscv_cpu, 1683 }; 1684 #endif 1685 1686 #include "hw/core/tcg-cpu-ops.h" 1687 1688 static const struct TCGCPUOps riscv_tcg_ops = { 1689 .initialize = riscv_translate_init, 1690 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1691 .restore_state_to_opc = riscv_restore_state_to_opc, 1692 1693 #ifndef CONFIG_USER_ONLY 1694 .tlb_fill = riscv_cpu_tlb_fill, 1695 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1696 .do_interrupt = riscv_cpu_do_interrupt, 1697 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1698 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1699 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1700 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1701 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1702 #endif /* !CONFIG_USER_ONLY */ 1703 }; 1704 1705 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1706 { 1707 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1708 CPUClass *cc = CPU_CLASS(c); 1709 DeviceClass *dc = DEVICE_CLASS(c); 1710 ResettableClass *rc = RESETTABLE_CLASS(c); 1711 1712 device_class_set_parent_realize(dc, riscv_cpu_realize, 1713 &mcc->parent_realize); 1714 1715 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1716 &mcc->parent_phases); 1717 1718 cc->class_by_name = riscv_cpu_class_by_name; 1719 cc->has_work = riscv_cpu_has_work; 1720 cc->dump_state = riscv_cpu_dump_state; 1721 cc->set_pc = riscv_cpu_set_pc; 1722 cc->get_pc = riscv_cpu_get_pc; 1723 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1724 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1725 cc->gdb_num_core_regs = 33; 1726 cc->gdb_stop_before_watchpoint = true; 1727 cc->disas_set_info = riscv_cpu_disas_set_info; 1728 #ifndef CONFIG_USER_ONLY 1729 cc->sysemu_ops = &riscv_sysemu_ops; 1730 cc->get_arch_id = riscv_get_arch_id; 1731 #endif 1732 cc->gdb_arch_name = riscv_gdb_arch_name; 1733 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1734 cc->tcg_ops = &riscv_tcg_ops; 1735 1736 device_class_set_props(dc, riscv_cpu_properties); 1737 } 1738 1739 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, 1740 int max_str_len) 1741 { 1742 char *old = *isa_str; 1743 char *new = *isa_str; 1744 int i; 1745 1746 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1747 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1748 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1749 g_free(old); 1750 old = new; 1751 } 1752 } 1753 1754 *isa_str = new; 1755 } 1756 1757 char *riscv_isa_string(RISCVCPU *cpu) 1758 { 1759 int i; 1760 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1761 char *isa_str = g_new(char, maxlen); 1762 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1763 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1764 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1765 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1766 } 1767 } 1768 *p = '\0'; 1769 if (!cpu->cfg.short_isa_string) { 1770 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1771 } 1772 return isa_str; 1773 } 1774 1775 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1776 { 1777 ObjectClass *class_a = (ObjectClass *)a; 1778 ObjectClass *class_b = (ObjectClass *)b; 1779 const char *name_a, *name_b; 1780 1781 name_a = object_class_get_name(class_a); 1782 name_b = object_class_get_name(class_b); 1783 return strcmp(name_a, name_b); 1784 } 1785 1786 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1787 { 1788 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1789 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1790 1791 qemu_printf("%.*s\n", len, typename); 1792 } 1793 1794 void riscv_cpu_list(void) 1795 { 1796 GSList *list; 1797 1798 list = object_class_get_list(TYPE_RISCV_CPU, false); 1799 list = g_slist_sort(list, riscv_cpu_list_compare); 1800 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1801 g_slist_free(list); 1802 } 1803 1804 #define DEFINE_CPU(type_name, initfn) \ 1805 { \ 1806 .name = type_name, \ 1807 .parent = TYPE_RISCV_CPU, \ 1808 .instance_init = initfn \ 1809 } 1810 1811 static const TypeInfo riscv_cpu_type_infos[] = { 1812 { 1813 .name = TYPE_RISCV_CPU, 1814 .parent = TYPE_CPU, 1815 .instance_size = sizeof(RISCVCPU), 1816 .instance_align = __alignof__(RISCVCPU), 1817 .instance_init = riscv_cpu_init, 1818 .abstract = true, 1819 .class_size = sizeof(RISCVCPUClass), 1820 .class_init = riscv_cpu_class_init, 1821 }, 1822 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1823 #if defined(CONFIG_KVM) 1824 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1825 #endif 1826 #if defined(TARGET_RISCV32) 1827 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1828 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1829 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1830 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1831 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1832 #elif defined(TARGET_RISCV64) 1833 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1834 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1835 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1836 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1837 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1838 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1839 #endif 1840 }; 1841 1842 DEFINE_TYPES(riscv_cpu_type_infos) 1843