1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "qemu/error-report.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "fpu/softfloat-helpers.h" 36 #include "sysemu/kvm.h" 37 #include "kvm_riscv.h" 38 #include "tcg/tcg.h" 39 40 /* RISC-V CPU definitions */ 41 42 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 43 (QEMU_VERSION_MINOR << 8) | \ 44 (QEMU_VERSION_MICRO)) 45 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 46 47 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 48 49 struct isa_ext_data { 50 const char *name; 51 int min_version; 52 int ext_enable_offset; 53 }; 54 55 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ 56 {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 57 58 /* 59 * Here are the ordering rules of extension naming defined by RISC-V 60 * specification : 61 * 1. All extensions should be separated from other multi-letter extensions 62 * by an underscore. 63 * 2. The first letter following the 'Z' conventionally indicates the most 64 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 65 * If multiple 'Z' extensions are named, they should be ordered first 66 * by category, then alphabetically within a category. 67 * 3. Standard supervisor-level extensions (starts with 'S') should be 68 * listed after standard unprivileged extensions. If multiple 69 * supervisor-level extensions are listed, they should be ordered 70 * alphabetically. 71 * 4. Non-standard extensions (starts with 'X') must be listed after all 72 * standard extensions. They must be separated from other multi-letter 73 * extensions by an underscore. 74 * 75 * Single letter extensions are checked in riscv_cpu_validate_misa_priv() 76 * instead. 77 */ 78 static const struct isa_ext_data isa_edata_arr[] = { 79 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), 80 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), 81 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), 82 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), 83 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), 84 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), 85 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), 86 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), 87 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), 88 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), 89 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), 90 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), 91 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), 92 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), 93 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), 94 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), 95 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), 96 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), 97 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), 98 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), 99 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), 100 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), 101 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), 102 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), 103 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), 104 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), 105 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), 106 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), 107 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), 108 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), 109 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), 110 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), 111 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), 112 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), 113 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), 114 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), 115 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), 116 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), 117 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), 118 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), 119 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), 120 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), 121 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), 122 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), 123 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), 124 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), 125 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), 126 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), 127 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), 128 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), 129 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), 130 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), 131 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), 132 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), 133 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 134 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 135 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), 136 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), 137 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 138 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), 139 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), 140 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 141 }; 142 143 static bool isa_ext_is_enabled(RISCVCPU *cpu, 144 const struct isa_ext_data *edata) 145 { 146 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 147 148 return *ext_enabled; 149 } 150 151 static void isa_ext_update_enabled(RISCVCPU *cpu, 152 const struct isa_ext_data *edata, bool en) 153 { 154 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 155 156 *ext_enabled = en; 157 } 158 159 const char * const riscv_int_regnames[] = { 160 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 161 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 162 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 163 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 164 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 165 }; 166 167 const char * const riscv_int_regnamesh[] = { 168 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 169 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 170 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 171 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 172 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 173 "x30h/t5h", "x31h/t6h" 174 }; 175 176 const char * const riscv_fpr_regnames[] = { 177 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 178 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 179 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 180 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 181 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 182 "f30/ft10", "f31/ft11" 183 }; 184 185 static const char * const riscv_excp_names[] = { 186 "misaligned_fetch", 187 "fault_fetch", 188 "illegal_instruction", 189 "breakpoint", 190 "misaligned_load", 191 "fault_load", 192 "misaligned_store", 193 "fault_store", 194 "user_ecall", 195 "supervisor_ecall", 196 "hypervisor_ecall", 197 "machine_ecall", 198 "exec_page_fault", 199 "load_page_fault", 200 "reserved", 201 "store_page_fault", 202 "reserved", 203 "reserved", 204 "reserved", 205 "reserved", 206 "guest_exec_page_fault", 207 "guest_load_page_fault", 208 "reserved", 209 "guest_store_page_fault", 210 }; 211 212 static const char * const riscv_intr_names[] = { 213 "u_software", 214 "s_software", 215 "vs_software", 216 "m_software", 217 "u_timer", 218 "s_timer", 219 "vs_timer", 220 "m_timer", 221 "u_external", 222 "s_external", 223 "vs_external", 224 "m_external", 225 "reserved", 226 "reserved", 227 "reserved", 228 "reserved" 229 }; 230 231 static void register_cpu_props(Object *obj); 232 233 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 234 { 235 if (async) { 236 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 237 riscv_intr_names[cause] : "(unknown)"; 238 } else { 239 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 240 riscv_excp_names[cause] : "(unknown)"; 241 } 242 } 243 244 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 245 { 246 env->misa_mxl_max = env->misa_mxl = mxl; 247 env->misa_ext_mask = env->misa_ext = ext; 248 } 249 250 static void set_priv_version(CPURISCVState *env, int priv_ver) 251 { 252 env->priv_ver = priv_ver; 253 } 254 255 static void set_vext_version(CPURISCVState *env, int vext_ver) 256 { 257 env->vext_ver = vext_ver; 258 } 259 260 #ifndef CONFIG_USER_ONLY 261 static uint8_t satp_mode_from_str(const char *satp_mode_str) 262 { 263 if (!strncmp(satp_mode_str, "mbare", 5)) { 264 return VM_1_10_MBARE; 265 } 266 267 if (!strncmp(satp_mode_str, "sv32", 4)) { 268 return VM_1_10_SV32; 269 } 270 271 if (!strncmp(satp_mode_str, "sv39", 4)) { 272 return VM_1_10_SV39; 273 } 274 275 if (!strncmp(satp_mode_str, "sv48", 4)) { 276 return VM_1_10_SV48; 277 } 278 279 if (!strncmp(satp_mode_str, "sv57", 4)) { 280 return VM_1_10_SV57; 281 } 282 283 if (!strncmp(satp_mode_str, "sv64", 4)) { 284 return VM_1_10_SV64; 285 } 286 287 g_assert_not_reached(); 288 } 289 290 uint8_t satp_mode_max_from_map(uint32_t map) 291 { 292 /* map here has at least one bit set, so no problem with clz */ 293 return 31 - __builtin_clz(map); 294 } 295 296 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) 297 { 298 if (is_32_bit) { 299 switch (satp_mode) { 300 case VM_1_10_SV32: 301 return "sv32"; 302 case VM_1_10_MBARE: 303 return "none"; 304 } 305 } else { 306 switch (satp_mode) { 307 case VM_1_10_SV64: 308 return "sv64"; 309 case VM_1_10_SV57: 310 return "sv57"; 311 case VM_1_10_SV48: 312 return "sv48"; 313 case VM_1_10_SV39: 314 return "sv39"; 315 case VM_1_10_MBARE: 316 return "none"; 317 } 318 } 319 320 g_assert_not_reached(); 321 } 322 323 static void set_satp_mode_max_supported(RISCVCPU *cpu, 324 uint8_t satp_mode) 325 { 326 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 327 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; 328 329 for (int i = 0; i <= satp_mode; ++i) { 330 if (valid_vm[i]) { 331 cpu->cfg.satp_mode.supported |= (1 << i); 332 } 333 } 334 } 335 336 /* Set the satp mode to the max supported */ 337 static void set_satp_mode_default_map(RISCVCPU *cpu) 338 { 339 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; 340 } 341 #endif 342 343 static void riscv_any_cpu_init(Object *obj) 344 { 345 CPURISCVState *env = &RISCV_CPU(obj)->env; 346 #if defined(TARGET_RISCV32) 347 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 348 #elif defined(TARGET_RISCV64) 349 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 350 #endif 351 352 #ifndef CONFIG_USER_ONLY 353 set_satp_mode_max_supported(RISCV_CPU(obj), 354 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? 355 VM_1_10_SV32 : VM_1_10_SV57); 356 #endif 357 358 set_priv_version(env, PRIV_VERSION_1_12_0); 359 register_cpu_props(obj); 360 } 361 362 #if defined(TARGET_RISCV64) 363 static void rv64_base_cpu_init(Object *obj) 364 { 365 CPURISCVState *env = &RISCV_CPU(obj)->env; 366 /* We set this in the realise function */ 367 set_misa(env, MXL_RV64, 0); 368 register_cpu_props(obj); 369 /* Set latest version of privileged specification */ 370 set_priv_version(env, PRIV_VERSION_1_12_0); 371 #ifndef CONFIG_USER_ONLY 372 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 373 #endif 374 } 375 376 static void rv64_sifive_u_cpu_init(Object *obj) 377 { 378 CPURISCVState *env = &RISCV_CPU(obj)->env; 379 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 380 register_cpu_props(obj); 381 set_priv_version(env, PRIV_VERSION_1_10_0); 382 #ifndef CONFIG_USER_ONLY 383 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); 384 #endif 385 } 386 387 static void rv64_sifive_e_cpu_init(Object *obj) 388 { 389 CPURISCVState *env = &RISCV_CPU(obj)->env; 390 RISCVCPU *cpu = RISCV_CPU(obj); 391 392 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 393 register_cpu_props(obj); 394 set_priv_version(env, PRIV_VERSION_1_10_0); 395 cpu->cfg.mmu = false; 396 #ifndef CONFIG_USER_ONLY 397 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 398 #endif 399 } 400 401 static void rv64_thead_c906_cpu_init(Object *obj) 402 { 403 CPURISCVState *env = &RISCV_CPU(obj)->env; 404 RISCVCPU *cpu = RISCV_CPU(obj); 405 406 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 407 set_priv_version(env, PRIV_VERSION_1_11_0); 408 409 cpu->cfg.ext_g = true; 410 cpu->cfg.ext_c = true; 411 cpu->cfg.ext_u = true; 412 cpu->cfg.ext_s = true; 413 cpu->cfg.ext_icsr = true; 414 cpu->cfg.ext_zfh = true; 415 cpu->cfg.mmu = true; 416 cpu->cfg.ext_xtheadba = true; 417 cpu->cfg.ext_xtheadbb = true; 418 cpu->cfg.ext_xtheadbs = true; 419 cpu->cfg.ext_xtheadcmo = true; 420 cpu->cfg.ext_xtheadcondmov = true; 421 cpu->cfg.ext_xtheadfmemidx = true; 422 cpu->cfg.ext_xtheadmac = true; 423 cpu->cfg.ext_xtheadmemidx = true; 424 cpu->cfg.ext_xtheadmempair = true; 425 cpu->cfg.ext_xtheadsync = true; 426 427 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 428 #ifndef CONFIG_USER_ONLY 429 set_satp_mode_max_supported(cpu, VM_1_10_SV39); 430 #endif 431 } 432 433 static void rv128_base_cpu_init(Object *obj) 434 { 435 if (qemu_tcg_mttcg_enabled()) { 436 /* Missing 128-bit aligned atomics */ 437 error_report("128-bit RISC-V currently does not work with Multi " 438 "Threaded TCG. Please use: -accel tcg,thread=single"); 439 exit(EXIT_FAILURE); 440 } 441 CPURISCVState *env = &RISCV_CPU(obj)->env; 442 /* We set this in the realise function */ 443 set_misa(env, MXL_RV128, 0); 444 register_cpu_props(obj); 445 /* Set latest version of privileged specification */ 446 set_priv_version(env, PRIV_VERSION_1_12_0); 447 #ifndef CONFIG_USER_ONLY 448 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 449 #endif 450 } 451 #else 452 static void rv32_base_cpu_init(Object *obj) 453 { 454 CPURISCVState *env = &RISCV_CPU(obj)->env; 455 /* We set this in the realise function */ 456 set_misa(env, MXL_RV32, 0); 457 register_cpu_props(obj); 458 /* Set latest version of privileged specification */ 459 set_priv_version(env, PRIV_VERSION_1_12_0); 460 #ifndef CONFIG_USER_ONLY 461 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 462 #endif 463 } 464 465 static void rv32_sifive_u_cpu_init(Object *obj) 466 { 467 CPURISCVState *env = &RISCV_CPU(obj)->env; 468 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 469 register_cpu_props(obj); 470 set_priv_version(env, PRIV_VERSION_1_10_0); 471 #ifndef CONFIG_USER_ONLY 472 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 473 #endif 474 } 475 476 static void rv32_sifive_e_cpu_init(Object *obj) 477 { 478 CPURISCVState *env = &RISCV_CPU(obj)->env; 479 RISCVCPU *cpu = RISCV_CPU(obj); 480 481 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 482 register_cpu_props(obj); 483 set_priv_version(env, PRIV_VERSION_1_10_0); 484 cpu->cfg.mmu = false; 485 #ifndef CONFIG_USER_ONLY 486 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 487 #endif 488 } 489 490 static void rv32_ibex_cpu_init(Object *obj) 491 { 492 CPURISCVState *env = &RISCV_CPU(obj)->env; 493 RISCVCPU *cpu = RISCV_CPU(obj); 494 495 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 496 register_cpu_props(obj); 497 set_priv_version(env, PRIV_VERSION_1_11_0); 498 cpu->cfg.mmu = false; 499 #ifndef CONFIG_USER_ONLY 500 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 501 #endif 502 cpu->cfg.epmp = true; 503 } 504 505 static void rv32_imafcu_nommu_cpu_init(Object *obj) 506 { 507 CPURISCVState *env = &RISCV_CPU(obj)->env; 508 RISCVCPU *cpu = RISCV_CPU(obj); 509 510 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 511 register_cpu_props(obj); 512 set_priv_version(env, PRIV_VERSION_1_10_0); 513 cpu->cfg.mmu = false; 514 #ifndef CONFIG_USER_ONLY 515 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 516 #endif 517 } 518 #endif 519 520 #if defined(CONFIG_KVM) 521 static void riscv_host_cpu_init(Object *obj) 522 { 523 CPURISCVState *env = &RISCV_CPU(obj)->env; 524 #if defined(TARGET_RISCV32) 525 set_misa(env, MXL_RV32, 0); 526 #elif defined(TARGET_RISCV64) 527 set_misa(env, MXL_RV64, 0); 528 #endif 529 register_cpu_props(obj); 530 } 531 #endif 532 533 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 534 { 535 ObjectClass *oc; 536 char *typename; 537 char **cpuname; 538 539 cpuname = g_strsplit(cpu_model, ",", 1); 540 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 541 oc = object_class_by_name(typename); 542 g_strfreev(cpuname); 543 g_free(typename); 544 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 545 object_class_is_abstract(oc)) { 546 return NULL; 547 } 548 return oc; 549 } 550 551 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 552 { 553 RISCVCPU *cpu = RISCV_CPU(cs); 554 CPURISCVState *env = &cpu->env; 555 int i; 556 557 #if !defined(CONFIG_USER_ONLY) 558 if (riscv_has_ext(env, RVH)) { 559 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); 560 } 561 #endif 562 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 563 #ifndef CONFIG_USER_ONLY 564 { 565 static const int dump_csrs[] = { 566 CSR_MHARTID, 567 CSR_MSTATUS, 568 CSR_MSTATUSH, 569 /* 570 * CSR_SSTATUS is intentionally omitted here as its value 571 * can be figured out by looking at CSR_MSTATUS 572 */ 573 CSR_HSTATUS, 574 CSR_VSSTATUS, 575 CSR_MIP, 576 CSR_MIE, 577 CSR_MIDELEG, 578 CSR_HIDELEG, 579 CSR_MEDELEG, 580 CSR_HEDELEG, 581 CSR_MTVEC, 582 CSR_STVEC, 583 CSR_VSTVEC, 584 CSR_MEPC, 585 CSR_SEPC, 586 CSR_VSEPC, 587 CSR_MCAUSE, 588 CSR_SCAUSE, 589 CSR_VSCAUSE, 590 CSR_MTVAL, 591 CSR_STVAL, 592 CSR_HTVAL, 593 CSR_MTVAL2, 594 CSR_MSCRATCH, 595 CSR_SSCRATCH, 596 CSR_SATP, 597 CSR_MMTE, 598 CSR_UPMBASE, 599 CSR_UPMMASK, 600 CSR_SPMBASE, 601 CSR_SPMMASK, 602 CSR_MPMBASE, 603 CSR_MPMMASK, 604 }; 605 606 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 607 int csrno = dump_csrs[i]; 608 target_ulong val = 0; 609 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 610 611 /* 612 * Rely on the smode, hmode, etc, predicates within csr.c 613 * to do the filtering of the registers that are present. 614 */ 615 if (res == RISCV_EXCP_NONE) { 616 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 617 csr_ops[csrno].name, val); 618 } 619 } 620 } 621 #endif 622 623 for (i = 0; i < 32; i++) { 624 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 625 riscv_int_regnames[i], env->gpr[i]); 626 if ((i & 3) == 3) { 627 qemu_fprintf(f, "\n"); 628 } 629 } 630 if (flags & CPU_DUMP_FPU) { 631 for (i = 0; i < 32; i++) { 632 qemu_fprintf(f, " %-8s %016" PRIx64, 633 riscv_fpr_regnames[i], env->fpr[i]); 634 if ((i & 3) == 3) { 635 qemu_fprintf(f, "\n"); 636 } 637 } 638 } 639 } 640 641 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 642 { 643 RISCVCPU *cpu = RISCV_CPU(cs); 644 CPURISCVState *env = &cpu->env; 645 646 if (env->xl == MXL_RV32) { 647 env->pc = (int32_t)value; 648 } else { 649 env->pc = value; 650 } 651 } 652 653 static vaddr riscv_cpu_get_pc(CPUState *cs) 654 { 655 RISCVCPU *cpu = RISCV_CPU(cs); 656 CPURISCVState *env = &cpu->env; 657 658 /* Match cpu_get_tb_cpu_state. */ 659 if (env->xl == MXL_RV32) { 660 return env->pc & UINT32_MAX; 661 } 662 return env->pc; 663 } 664 665 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 666 const TranslationBlock *tb) 667 { 668 RISCVCPU *cpu = RISCV_CPU(cs); 669 CPURISCVState *env = &cpu->env; 670 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 671 672 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 673 674 if (xl == MXL_RV32) { 675 env->pc = (int32_t) tb->pc; 676 } else { 677 env->pc = tb->pc; 678 } 679 } 680 681 static bool riscv_cpu_has_work(CPUState *cs) 682 { 683 #ifndef CONFIG_USER_ONLY 684 RISCVCPU *cpu = RISCV_CPU(cs); 685 CPURISCVState *env = &cpu->env; 686 /* 687 * Definition of the WFI instruction requires it to ignore the privilege 688 * mode and delegation registers, but respect individual enables 689 */ 690 return riscv_cpu_all_pending(env) != 0; 691 #else 692 return true; 693 #endif 694 } 695 696 static void riscv_restore_state_to_opc(CPUState *cs, 697 const TranslationBlock *tb, 698 const uint64_t *data) 699 { 700 RISCVCPU *cpu = RISCV_CPU(cs); 701 CPURISCVState *env = &cpu->env; 702 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 703 704 if (xl == MXL_RV32) { 705 env->pc = (int32_t)data[0]; 706 } else { 707 env->pc = data[0]; 708 } 709 env->bins = data[1]; 710 } 711 712 static void riscv_cpu_reset_hold(Object *obj) 713 { 714 #ifndef CONFIG_USER_ONLY 715 uint8_t iprio; 716 int i, irq, rdzero; 717 #endif 718 CPUState *cs = CPU(obj); 719 RISCVCPU *cpu = RISCV_CPU(cs); 720 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 721 CPURISCVState *env = &cpu->env; 722 723 if (mcc->parent_phases.hold) { 724 mcc->parent_phases.hold(obj); 725 } 726 #ifndef CONFIG_USER_ONLY 727 env->misa_mxl = env->misa_mxl_max; 728 env->priv = PRV_M; 729 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 730 if (env->misa_mxl > MXL_RV32) { 731 /* 732 * The reset status of SXL/UXL is undefined, but mstatus is WARL 733 * and we must ensure that the value after init is valid for read. 734 */ 735 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 736 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 737 if (riscv_has_ext(env, RVH)) { 738 env->vsstatus = set_field(env->vsstatus, 739 MSTATUS64_SXL, env->misa_mxl); 740 env->vsstatus = set_field(env->vsstatus, 741 MSTATUS64_UXL, env->misa_mxl); 742 env->mstatus_hs = set_field(env->mstatus_hs, 743 MSTATUS64_SXL, env->misa_mxl); 744 env->mstatus_hs = set_field(env->mstatus_hs, 745 MSTATUS64_UXL, env->misa_mxl); 746 } 747 } 748 env->mcause = 0; 749 env->miclaim = MIP_SGEIP; 750 env->pc = env->resetvec; 751 env->bins = 0; 752 env->two_stage_lookup = false; 753 754 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | 755 (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); 756 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | 757 (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); 758 759 /* Initialized default priorities of local interrupts. */ 760 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 761 iprio = riscv_cpu_default_priority(i); 762 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 763 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 764 env->hviprio[i] = 0; 765 } 766 i = 0; 767 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 768 if (!rdzero) { 769 env->hviprio[irq] = env->miprio[irq]; 770 } 771 i++; 772 } 773 /* mmte is supposed to have pm.current hardwired to 1 */ 774 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 775 #endif 776 env->xl = riscv_cpu_mxl(env); 777 riscv_cpu_update_mask(env); 778 cs->exception_index = RISCV_EXCP_NONE; 779 env->load_res = -1; 780 set_default_nan_mode(1, &env->fp_status); 781 782 #ifndef CONFIG_USER_ONLY 783 if (cpu->cfg.debug) { 784 riscv_trigger_init(env); 785 } 786 787 if (kvm_enabled()) { 788 kvm_riscv_reset_vcpu(cpu); 789 } 790 #endif 791 } 792 793 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 794 { 795 RISCVCPU *cpu = RISCV_CPU(s); 796 797 switch (riscv_cpu_mxl(&cpu->env)) { 798 case MXL_RV32: 799 info->print_insn = print_insn_riscv32; 800 break; 801 case MXL_RV64: 802 info->print_insn = print_insn_riscv64; 803 break; 804 case MXL_RV128: 805 info->print_insn = print_insn_riscv128; 806 break; 807 default: 808 g_assert_not_reached(); 809 } 810 } 811 812 /* 813 * Check consistency between chosen extensions while setting 814 * cpu->cfg accordingly. 815 */ 816 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 817 { 818 CPURISCVState *env = &cpu->env; 819 820 /* Do some ISA extension error checking */ 821 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 822 riscv_has_ext(env, RVA) && 823 cpu->cfg.ext_f && cpu->cfg.ext_d && 824 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 825 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 826 cpu->cfg.ext_i = true; 827 cpu->cfg.ext_m = true; 828 cpu->cfg.ext_f = true; 829 cpu->cfg.ext_d = true; 830 cpu->cfg.ext_icsr = true; 831 cpu->cfg.ext_ifencei = true; 832 833 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; 834 env->misa_ext_mask = env->misa_ext; 835 } 836 837 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 838 error_setg(errp, 839 "I and E extensions are incompatible"); 840 return; 841 } 842 843 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 844 error_setg(errp, 845 "Either I or E extension must be set"); 846 return; 847 } 848 849 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 850 error_setg(errp, 851 "Setting S extension without U extension is illegal"); 852 return; 853 } 854 855 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { 856 error_setg(errp, 857 "H depends on an I base integer ISA with 32 x registers"); 858 return; 859 } 860 861 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 862 error_setg(errp, "H extension implicitly requires S-mode"); 863 return; 864 } 865 866 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 867 error_setg(errp, "F extension requires Zicsr"); 868 return; 869 } 870 871 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 872 error_setg(errp, "Zawrs extension requires A extension"); 873 return; 874 } 875 876 if (cpu->cfg.ext_zfh) { 877 cpu->cfg.ext_zfhmin = true; 878 } 879 880 if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { 881 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 882 return; 883 } 884 885 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 886 error_setg(errp, "D extension requires F extension"); 887 return; 888 } 889 890 /* The V vector extension depends on the Zve64d extension */ 891 if (cpu->cfg.ext_v) { 892 cpu->cfg.ext_zve64d = true; 893 } 894 895 /* The Zve64d extension depends on the Zve64f extension */ 896 if (cpu->cfg.ext_zve64d) { 897 cpu->cfg.ext_zve64f = true; 898 } 899 900 /* The Zve64f extension depends on the Zve32f extension */ 901 if (cpu->cfg.ext_zve64f) { 902 cpu->cfg.ext_zve32f = true; 903 } 904 905 if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { 906 error_setg(errp, "Zve64d/V extensions require D extension"); 907 return; 908 } 909 910 if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { 911 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 912 return; 913 } 914 915 if (cpu->cfg.ext_zvfh) { 916 cpu->cfg.ext_zvfhmin = true; 917 } 918 919 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 920 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 921 return; 922 } 923 924 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 925 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 926 return; 927 } 928 929 /* Set the ISA extensions, checks should have happened above */ 930 if (cpu->cfg.ext_zhinx) { 931 cpu->cfg.ext_zhinxmin = true; 932 } 933 934 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { 935 cpu->cfg.ext_zfinx = true; 936 } 937 938 if (cpu->cfg.ext_zfinx) { 939 if (!cpu->cfg.ext_icsr) { 940 error_setg(errp, "Zfinx extension requires Zicsr"); 941 return; 942 } 943 if (cpu->cfg.ext_f) { 944 error_setg(errp, 945 "Zfinx cannot be supported together with F extension"); 946 return; 947 } 948 } 949 950 if (cpu->cfg.ext_zce) { 951 cpu->cfg.ext_zca = true; 952 cpu->cfg.ext_zcb = true; 953 cpu->cfg.ext_zcmp = true; 954 cpu->cfg.ext_zcmt = true; 955 if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { 956 cpu->cfg.ext_zcf = true; 957 } 958 } 959 960 if (cpu->cfg.ext_c) { 961 cpu->cfg.ext_zca = true; 962 if (cpu->cfg.ext_f && env->misa_mxl_max == MXL_RV32) { 963 cpu->cfg.ext_zcf = true; 964 } 965 if (cpu->cfg.ext_d) { 966 cpu->cfg.ext_zcd = true; 967 } 968 } 969 970 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 971 error_setg(errp, "Zcf extension is only relevant to RV32"); 972 return; 973 } 974 975 if (!cpu->cfg.ext_f && cpu->cfg.ext_zcf) { 976 error_setg(errp, "Zcf extension requires F extension"); 977 return; 978 } 979 980 if (!cpu->cfg.ext_d && cpu->cfg.ext_zcd) { 981 error_setg(errp, "Zcd extension requires D extension"); 982 return; 983 } 984 985 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 986 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 987 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 988 "extension"); 989 return; 990 } 991 992 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 993 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 994 "Zcd extension"); 995 return; 996 } 997 998 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { 999 error_setg(errp, "Zcmt extension requires Zicsr extension"); 1000 return; 1001 } 1002 1003 if (cpu->cfg.ext_zk) { 1004 cpu->cfg.ext_zkn = true; 1005 cpu->cfg.ext_zkr = true; 1006 cpu->cfg.ext_zkt = true; 1007 } 1008 1009 if (cpu->cfg.ext_zkn) { 1010 cpu->cfg.ext_zbkb = true; 1011 cpu->cfg.ext_zbkc = true; 1012 cpu->cfg.ext_zbkx = true; 1013 cpu->cfg.ext_zkne = true; 1014 cpu->cfg.ext_zknd = true; 1015 cpu->cfg.ext_zknh = true; 1016 } 1017 1018 if (cpu->cfg.ext_zks) { 1019 cpu->cfg.ext_zbkb = true; 1020 cpu->cfg.ext_zbkc = true; 1021 cpu->cfg.ext_zbkx = true; 1022 cpu->cfg.ext_zksed = true; 1023 cpu->cfg.ext_zksh = true; 1024 } 1025 1026 if (cpu->cfg.ext_v) { 1027 int vext_version = VEXT_VERSION_1_00_0; 1028 if (!is_power_of_2(cpu->cfg.vlen)) { 1029 error_setg(errp, 1030 "Vector extension VLEN must be power of 2"); 1031 return; 1032 } 1033 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 1034 error_setg(errp, 1035 "Vector extension implementation only supports VLEN " 1036 "in the range [128, %d]", RV_VLEN_MAX); 1037 return; 1038 } 1039 if (!is_power_of_2(cpu->cfg.elen)) { 1040 error_setg(errp, 1041 "Vector extension ELEN must be power of 2"); 1042 return; 1043 } 1044 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 1045 error_setg(errp, 1046 "Vector extension implementation only supports ELEN " 1047 "in the range [8, 64]"); 1048 return; 1049 } 1050 if (cpu->cfg.vext_spec) { 1051 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 1052 vext_version = VEXT_VERSION_1_00_0; 1053 } else { 1054 error_setg(errp, 1055 "Unsupported vector spec version '%s'", 1056 cpu->cfg.vext_spec); 1057 return; 1058 } 1059 } else { 1060 qemu_log("vector version is not specified, " 1061 "use the default value v1.0\n"); 1062 } 1063 set_vext_version(env, vext_version); 1064 } 1065 } 1066 1067 #ifndef CONFIG_USER_ONLY 1068 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) 1069 { 1070 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 1071 uint8_t satp_mode_map_max; 1072 uint8_t satp_mode_supported_max = 1073 satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 1074 1075 if (cpu->cfg.satp_mode.map == 0) { 1076 if (cpu->cfg.satp_mode.init == 0) { 1077 /* If unset by the user, we fallback to the default satp mode. */ 1078 set_satp_mode_default_map(cpu); 1079 } else { 1080 /* 1081 * Find the lowest level that was disabled and then enable the 1082 * first valid level below which can be found in 1083 * valid_vm_1_10_32/64. 1084 */ 1085 for (int i = 1; i < 16; ++i) { 1086 if ((cpu->cfg.satp_mode.init & (1 << i)) && 1087 (cpu->cfg.satp_mode.supported & (1 << i))) { 1088 for (int j = i - 1; j >= 0; --j) { 1089 if (cpu->cfg.satp_mode.supported & (1 << j)) { 1090 cpu->cfg.satp_mode.map |= (1 << j); 1091 break; 1092 } 1093 } 1094 break; 1095 } 1096 } 1097 } 1098 } 1099 1100 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 1101 1102 /* Make sure the user asked for a supported configuration (HW and qemu) */ 1103 if (satp_mode_map_max > satp_mode_supported_max) { 1104 error_setg(errp, "satp_mode %s is higher than hw max capability %s", 1105 satp_mode_str(satp_mode_map_max, rv32), 1106 satp_mode_str(satp_mode_supported_max, rv32)); 1107 return; 1108 } 1109 1110 /* 1111 * Make sure the user did not ask for an invalid configuration as per 1112 * the specification. 1113 */ 1114 if (!rv32) { 1115 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1116 if (!(cpu->cfg.satp_mode.map & (1 << i)) && 1117 (cpu->cfg.satp_mode.init & (1 << i)) && 1118 (cpu->cfg.satp_mode.supported & (1 << i))) { 1119 error_setg(errp, "cannot disable %s satp mode if %s " 1120 "is enabled", satp_mode_str(i, false), 1121 satp_mode_str(satp_mode_map_max, false)); 1122 return; 1123 } 1124 } 1125 } 1126 1127 /* Finally expand the map so that all valid modes are set */ 1128 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1129 if (cpu->cfg.satp_mode.supported & (1 << i)) { 1130 cpu->cfg.satp_mode.map |= (1 << i); 1131 } 1132 } 1133 } 1134 #endif 1135 1136 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1137 { 1138 #ifndef CONFIG_USER_ONLY 1139 Error *local_err = NULL; 1140 1141 riscv_cpu_satp_mode_finalize(cpu, &local_err); 1142 if (local_err != NULL) { 1143 error_propagate(errp, local_err); 1144 return; 1145 } 1146 #endif 1147 } 1148 1149 static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) 1150 { 1151 uint32_t ext = 0; 1152 1153 if (riscv_cpu_cfg(env)->ext_i) { 1154 ext |= RVI; 1155 } 1156 if (riscv_cpu_cfg(env)->ext_e) { 1157 ext |= RVE; 1158 } 1159 if (riscv_cpu_cfg(env)->ext_m) { 1160 ext |= RVM; 1161 } 1162 if (riscv_has_ext(env, RVA)) { 1163 ext |= RVA; 1164 } 1165 if (riscv_cpu_cfg(env)->ext_f) { 1166 ext |= RVF; 1167 } 1168 if (riscv_cpu_cfg(env)->ext_d) { 1169 ext |= RVD; 1170 } 1171 if (riscv_cpu_cfg(env)->ext_c) { 1172 ext |= RVC; 1173 } 1174 if (riscv_cpu_cfg(env)->ext_s) { 1175 ext |= RVS; 1176 } 1177 if (riscv_cpu_cfg(env)->ext_u) { 1178 ext |= RVU; 1179 } 1180 if (riscv_cpu_cfg(env)->ext_h) { 1181 ext |= RVH; 1182 } 1183 if (riscv_cpu_cfg(env)->ext_v) { 1184 ext |= RVV; 1185 } 1186 if (riscv_cpu_cfg(env)->ext_j) { 1187 ext |= RVJ; 1188 } 1189 1190 env->misa_ext = env->misa_ext_mask = ext; 1191 } 1192 1193 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 1194 { 1195 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 1196 error_setg(errp, "H extension requires priv spec 1.12.0"); 1197 return; 1198 } 1199 } 1200 1201 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 1202 { 1203 CPUState *cs = CPU(dev); 1204 RISCVCPU *cpu = RISCV_CPU(dev); 1205 CPURISCVState *env = &cpu->env; 1206 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 1207 CPUClass *cc = CPU_CLASS(mcc); 1208 int i, priv_version = -1; 1209 Error *local_err = NULL; 1210 1211 cpu_exec_realizefn(cs, &local_err); 1212 if (local_err != NULL) { 1213 error_propagate(errp, local_err); 1214 return; 1215 } 1216 1217 if (cpu->cfg.priv_spec) { 1218 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 1219 priv_version = PRIV_VERSION_1_12_0; 1220 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 1221 priv_version = PRIV_VERSION_1_11_0; 1222 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 1223 priv_version = PRIV_VERSION_1_10_0; 1224 } else { 1225 error_setg(errp, 1226 "Unsupported privilege spec version '%s'", 1227 cpu->cfg.priv_spec); 1228 return; 1229 } 1230 } 1231 1232 if (priv_version >= PRIV_VERSION_1_10_0) { 1233 set_priv_version(env, priv_version); 1234 } 1235 1236 /* 1237 * We can't be sure of whether we set defaults during cpu_init() 1238 * or whether the user enabled/disabled some bits via cpu->cfg 1239 * flags. Sync env->misa_ext with cpu->cfg now to allow us to 1240 * use just env->misa_ext later. 1241 */ 1242 riscv_cpu_sync_misa_cfg(env); 1243 1244 riscv_cpu_validate_misa_priv(env, &local_err); 1245 if (local_err != NULL) { 1246 error_propagate(errp, local_err); 1247 return; 1248 } 1249 1250 /* Force disable extensions if priv spec version does not match */ 1251 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1252 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 1253 (env->priv_ver < isa_edata_arr[i].min_version)) { 1254 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 1255 #ifndef CONFIG_USER_ONLY 1256 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 1257 " because privilege spec version does not match", 1258 isa_edata_arr[i].name, env->mhartid); 1259 #else 1260 warn_report("disabling %s extension because " 1261 "privilege spec version does not match", 1262 isa_edata_arr[i].name); 1263 #endif 1264 } 1265 } 1266 1267 if (cpu->cfg.epmp && !cpu->cfg.pmp) { 1268 /* 1269 * Enhanced PMP should only be available 1270 * on harts with PMP support 1271 */ 1272 error_setg(errp, "Invalid configuration: EPMP requires PMP support"); 1273 return; 1274 } 1275 1276 1277 #ifndef CONFIG_USER_ONLY 1278 if (cpu->cfg.ext_sstc) { 1279 riscv_timer_init(cpu); 1280 } 1281 #endif /* CONFIG_USER_ONLY */ 1282 1283 /* Validate that MISA_MXL is set properly. */ 1284 switch (env->misa_mxl_max) { 1285 #ifdef TARGET_RISCV64 1286 case MXL_RV64: 1287 case MXL_RV128: 1288 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 1289 break; 1290 #endif 1291 case MXL_RV32: 1292 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 1293 break; 1294 default: 1295 g_assert_not_reached(); 1296 } 1297 assert(env->misa_mxl_max == env->misa_mxl); 1298 1299 riscv_cpu_validate_set_extensions(cpu, &local_err); 1300 if (local_err != NULL) { 1301 error_propagate(errp, local_err); 1302 return; 1303 } 1304 1305 #ifndef CONFIG_USER_ONLY 1306 if (cpu->cfg.pmu_num) { 1307 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 1308 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1309 riscv_pmu_timer_cb, cpu); 1310 } 1311 } 1312 #endif 1313 1314 riscv_cpu_finalize_features(cpu, &local_err); 1315 if (local_err != NULL) { 1316 error_propagate(errp, local_err); 1317 return; 1318 } 1319 1320 riscv_cpu_register_gdb_regs_for_features(cs); 1321 1322 qemu_init_vcpu(cs); 1323 cpu_reset(cs); 1324 1325 mcc->parent_realize(dev, errp); 1326 } 1327 1328 #ifndef CONFIG_USER_ONLY 1329 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, 1330 void *opaque, Error **errp) 1331 { 1332 RISCVSATPMap *satp_map = opaque; 1333 uint8_t satp = satp_mode_from_str(name); 1334 bool value; 1335 1336 value = satp_map->map & (1 << satp); 1337 1338 visit_type_bool(v, name, &value, errp); 1339 } 1340 1341 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, 1342 void *opaque, Error **errp) 1343 { 1344 RISCVSATPMap *satp_map = opaque; 1345 uint8_t satp = satp_mode_from_str(name); 1346 bool value; 1347 1348 if (!visit_type_bool(v, name, &value, errp)) { 1349 return; 1350 } 1351 1352 satp_map->map = deposit32(satp_map->map, satp, 1, value); 1353 satp_map->init |= 1 << satp; 1354 } 1355 1356 static void riscv_add_satp_mode_properties(Object *obj) 1357 { 1358 RISCVCPU *cpu = RISCV_CPU(obj); 1359 1360 if (cpu->env.misa_mxl == MXL_RV32) { 1361 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, 1362 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1363 } else { 1364 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, 1365 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1366 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, 1367 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1368 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, 1369 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1370 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, 1371 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1372 } 1373 } 1374 1375 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1376 { 1377 RISCVCPU *cpu = RISCV_CPU(opaque); 1378 CPURISCVState *env = &cpu->env; 1379 1380 if (irq < IRQ_LOCAL_MAX) { 1381 switch (irq) { 1382 case IRQ_U_SOFT: 1383 case IRQ_S_SOFT: 1384 case IRQ_VS_SOFT: 1385 case IRQ_M_SOFT: 1386 case IRQ_U_TIMER: 1387 case IRQ_S_TIMER: 1388 case IRQ_VS_TIMER: 1389 case IRQ_M_TIMER: 1390 case IRQ_U_EXT: 1391 case IRQ_VS_EXT: 1392 case IRQ_M_EXT: 1393 if (kvm_enabled()) { 1394 kvm_riscv_set_irq(cpu, irq, level); 1395 } else { 1396 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); 1397 } 1398 break; 1399 case IRQ_S_EXT: 1400 if (kvm_enabled()) { 1401 kvm_riscv_set_irq(cpu, irq, level); 1402 } else { 1403 env->external_seip = level; 1404 riscv_cpu_update_mip(env, 1 << irq, 1405 BOOL_TO_MASK(level | env->software_seip)); 1406 } 1407 break; 1408 default: 1409 g_assert_not_reached(); 1410 } 1411 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1412 /* Require H-extension for handling guest local interrupts */ 1413 if (!riscv_has_ext(env, RVH)) { 1414 g_assert_not_reached(); 1415 } 1416 1417 /* Compute bit position in HGEIP CSR */ 1418 irq = irq - IRQ_LOCAL_MAX + 1; 1419 if (env->geilen < irq) { 1420 g_assert_not_reached(); 1421 } 1422 1423 /* Update HGEIP CSR */ 1424 env->hgeip &= ~((target_ulong)1 << irq); 1425 if (level) { 1426 env->hgeip |= (target_ulong)1 << irq; 1427 } 1428 1429 /* Update mip.SGEIP bit */ 1430 riscv_cpu_update_mip(env, MIP_SGEIP, 1431 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1432 } else { 1433 g_assert_not_reached(); 1434 } 1435 } 1436 #endif /* CONFIG_USER_ONLY */ 1437 1438 static void riscv_cpu_init(Object *obj) 1439 { 1440 RISCVCPU *cpu = RISCV_CPU(obj); 1441 1442 cpu->cfg.ext_ifencei = true; 1443 cpu->cfg.ext_icsr = true; 1444 cpu->cfg.mmu = true; 1445 cpu->cfg.pmp = true; 1446 1447 cpu_set_cpustate_pointers(cpu); 1448 1449 #ifndef CONFIG_USER_ONLY 1450 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1451 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1452 #endif /* CONFIG_USER_ONLY */ 1453 } 1454 1455 typedef struct RISCVCPUMisaExtConfig { 1456 const char *name; 1457 const char *description; 1458 target_ulong misa_bit; 1459 bool enabled; 1460 } RISCVCPUMisaExtConfig; 1461 1462 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1463 void *opaque, Error **errp) 1464 { 1465 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1466 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1467 RISCVCPU *cpu = RISCV_CPU(obj); 1468 CPURISCVState *env = &cpu->env; 1469 bool value; 1470 1471 if (!visit_type_bool(v, name, &value, errp)) { 1472 return; 1473 } 1474 1475 if (value) { 1476 env->misa_ext |= misa_bit; 1477 env->misa_ext_mask |= misa_bit; 1478 } else { 1479 env->misa_ext &= ~misa_bit; 1480 env->misa_ext_mask &= ~misa_bit; 1481 } 1482 } 1483 1484 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1485 void *opaque, Error **errp) 1486 { 1487 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1488 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1489 RISCVCPU *cpu = RISCV_CPU(obj); 1490 CPURISCVState *env = &cpu->env; 1491 bool value; 1492 1493 value = env->misa_ext & misa_bit; 1494 1495 visit_type_bool(v, name, &value, errp); 1496 } 1497 1498 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1499 {.name = "a", .description = "Atomic instructions", 1500 .misa_bit = RVA, .enabled = true}, 1501 }; 1502 1503 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1504 { 1505 int i; 1506 1507 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1508 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1509 1510 object_property_add(cpu_obj, misa_cfg->name, "bool", 1511 cpu_get_misa_ext_cfg, 1512 cpu_set_misa_ext_cfg, 1513 NULL, (void *)misa_cfg); 1514 object_property_set_description(cpu_obj, misa_cfg->name, 1515 misa_cfg->description); 1516 object_property_set_bool(cpu_obj, misa_cfg->name, 1517 misa_cfg->enabled, NULL); 1518 } 1519 } 1520 1521 static Property riscv_cpu_extensions[] = { 1522 /* Defaults for standard extensions */ 1523 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 1524 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 1525 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1526 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 1527 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 1528 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 1529 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 1530 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 1531 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1532 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1533 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1534 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1535 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1536 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1537 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1538 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1539 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1540 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1541 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1542 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1543 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1544 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), 1545 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1546 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1547 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1548 1549 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1550 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1551 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1552 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1553 1554 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), 1555 1556 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1557 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1558 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1559 1560 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1561 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1562 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1563 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1564 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1565 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1566 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1567 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1568 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1569 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1570 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1571 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1572 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1573 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1574 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1575 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1576 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1577 1578 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1579 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1580 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1581 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1582 1583 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), 1584 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), 1585 DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), 1586 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), 1587 1588 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1589 1590 /* Vendor-specific custom extensions */ 1591 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1592 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1593 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1594 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1595 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1596 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1597 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1598 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1599 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1600 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1601 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1602 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1603 1604 /* These are experimental so mark with 'x-' */ 1605 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), 1606 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1607 1608 DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), 1609 DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), 1610 DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), 1611 DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), 1612 DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), 1613 DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), 1614 DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), 1615 1616 /* ePMP 0.9.3 */ 1617 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1618 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1619 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1620 1621 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), 1622 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), 1623 1624 DEFINE_PROP_END_OF_LIST(), 1625 }; 1626 1627 /* 1628 * Register CPU props based on env.misa_ext. If a non-zero 1629 * value was set, register only the required cpu->cfg.ext_* 1630 * properties and leave. env.misa_ext = 0 means that we want 1631 * all the default properties to be registered. 1632 */ 1633 static void register_cpu_props(Object *obj) 1634 { 1635 RISCVCPU *cpu = RISCV_CPU(obj); 1636 uint32_t misa_ext = cpu->env.misa_ext; 1637 Property *prop; 1638 DeviceState *dev = DEVICE(obj); 1639 1640 /* 1641 * If misa_ext is not zero, set cfg properties now to 1642 * allow them to be read during riscv_cpu_realize() 1643 * later on. 1644 */ 1645 if (cpu->env.misa_ext != 0) { 1646 cpu->cfg.ext_i = misa_ext & RVI; 1647 cpu->cfg.ext_e = misa_ext & RVE; 1648 cpu->cfg.ext_m = misa_ext & RVM; 1649 cpu->cfg.ext_f = misa_ext & RVF; 1650 cpu->cfg.ext_d = misa_ext & RVD; 1651 cpu->cfg.ext_v = misa_ext & RVV; 1652 cpu->cfg.ext_c = misa_ext & RVC; 1653 cpu->cfg.ext_s = misa_ext & RVS; 1654 cpu->cfg.ext_u = misa_ext & RVU; 1655 cpu->cfg.ext_h = misa_ext & RVH; 1656 cpu->cfg.ext_j = misa_ext & RVJ; 1657 1658 /* 1659 * We don't want to set the default riscv_cpu_extensions 1660 * in this case. 1661 */ 1662 return; 1663 } 1664 1665 riscv_cpu_add_misa_properties(obj); 1666 1667 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1668 qdev_property_add_static(dev, prop); 1669 } 1670 1671 #ifndef CONFIG_USER_ONLY 1672 riscv_add_satp_mode_properties(obj); 1673 #endif 1674 } 1675 1676 static Property riscv_cpu_properties[] = { 1677 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1678 1679 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1680 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1681 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1682 1683 #ifndef CONFIG_USER_ONLY 1684 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1685 #endif 1686 1687 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1688 1689 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1690 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1691 1692 /* 1693 * write_misa() is marked as experimental for now so mark 1694 * it with -x and default to 'false'. 1695 */ 1696 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1697 DEFINE_PROP_END_OF_LIST(), 1698 }; 1699 1700 static gchar *riscv_gdb_arch_name(CPUState *cs) 1701 { 1702 RISCVCPU *cpu = RISCV_CPU(cs); 1703 CPURISCVState *env = &cpu->env; 1704 1705 switch (riscv_cpu_mxl(env)) { 1706 case MXL_RV32: 1707 return g_strdup("riscv:rv32"); 1708 case MXL_RV64: 1709 case MXL_RV128: 1710 return g_strdup("riscv:rv64"); 1711 default: 1712 g_assert_not_reached(); 1713 } 1714 } 1715 1716 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1717 { 1718 RISCVCPU *cpu = RISCV_CPU(cs); 1719 1720 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1721 return cpu->dyn_csr_xml; 1722 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1723 return cpu->dyn_vreg_xml; 1724 } 1725 1726 return NULL; 1727 } 1728 1729 #ifndef CONFIG_USER_ONLY 1730 static int64_t riscv_get_arch_id(CPUState *cs) 1731 { 1732 RISCVCPU *cpu = RISCV_CPU(cs); 1733 1734 return cpu->env.mhartid; 1735 } 1736 1737 #include "hw/core/sysemu-cpu-ops.h" 1738 1739 static const struct SysemuCPUOps riscv_sysemu_ops = { 1740 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1741 .write_elf64_note = riscv_cpu_write_elf64_note, 1742 .write_elf32_note = riscv_cpu_write_elf32_note, 1743 .legacy_vmsd = &vmstate_riscv_cpu, 1744 }; 1745 #endif 1746 1747 #include "hw/core/tcg-cpu-ops.h" 1748 1749 static const struct TCGCPUOps riscv_tcg_ops = { 1750 .initialize = riscv_translate_init, 1751 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1752 .restore_state_to_opc = riscv_restore_state_to_opc, 1753 1754 #ifndef CONFIG_USER_ONLY 1755 .tlb_fill = riscv_cpu_tlb_fill, 1756 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1757 .do_interrupt = riscv_cpu_do_interrupt, 1758 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1759 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1760 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1761 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1762 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1763 #endif /* !CONFIG_USER_ONLY */ 1764 }; 1765 1766 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1767 { 1768 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1769 CPUClass *cc = CPU_CLASS(c); 1770 DeviceClass *dc = DEVICE_CLASS(c); 1771 ResettableClass *rc = RESETTABLE_CLASS(c); 1772 1773 device_class_set_parent_realize(dc, riscv_cpu_realize, 1774 &mcc->parent_realize); 1775 1776 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1777 &mcc->parent_phases); 1778 1779 cc->class_by_name = riscv_cpu_class_by_name; 1780 cc->has_work = riscv_cpu_has_work; 1781 cc->dump_state = riscv_cpu_dump_state; 1782 cc->set_pc = riscv_cpu_set_pc; 1783 cc->get_pc = riscv_cpu_get_pc; 1784 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1785 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1786 cc->gdb_num_core_regs = 33; 1787 cc->gdb_stop_before_watchpoint = true; 1788 cc->disas_set_info = riscv_cpu_disas_set_info; 1789 #ifndef CONFIG_USER_ONLY 1790 cc->sysemu_ops = &riscv_sysemu_ops; 1791 cc->get_arch_id = riscv_get_arch_id; 1792 #endif 1793 cc->gdb_arch_name = riscv_gdb_arch_name; 1794 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1795 cc->tcg_ops = &riscv_tcg_ops; 1796 1797 device_class_set_props(dc, riscv_cpu_properties); 1798 } 1799 1800 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, 1801 int max_str_len) 1802 { 1803 char *old = *isa_str; 1804 char *new = *isa_str; 1805 int i; 1806 1807 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1808 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1809 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1810 g_free(old); 1811 old = new; 1812 } 1813 } 1814 1815 *isa_str = new; 1816 } 1817 1818 char *riscv_isa_string(RISCVCPU *cpu) 1819 { 1820 int i; 1821 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1822 char *isa_str = g_new(char, maxlen); 1823 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1824 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1825 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1826 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1827 } 1828 } 1829 *p = '\0'; 1830 if (!cpu->cfg.short_isa_string) { 1831 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1832 } 1833 return isa_str; 1834 } 1835 1836 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1837 { 1838 ObjectClass *class_a = (ObjectClass *)a; 1839 ObjectClass *class_b = (ObjectClass *)b; 1840 const char *name_a, *name_b; 1841 1842 name_a = object_class_get_name(class_a); 1843 name_b = object_class_get_name(class_b); 1844 return strcmp(name_a, name_b); 1845 } 1846 1847 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1848 { 1849 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1850 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1851 1852 qemu_printf("%.*s\n", len, typename); 1853 } 1854 1855 void riscv_cpu_list(void) 1856 { 1857 GSList *list; 1858 1859 list = object_class_get_list(TYPE_RISCV_CPU, false); 1860 list = g_slist_sort(list, riscv_cpu_list_compare); 1861 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1862 g_slist_free(list); 1863 } 1864 1865 #define DEFINE_CPU(type_name, initfn) \ 1866 { \ 1867 .name = type_name, \ 1868 .parent = TYPE_RISCV_CPU, \ 1869 .instance_init = initfn \ 1870 } 1871 1872 static const TypeInfo riscv_cpu_type_infos[] = { 1873 { 1874 .name = TYPE_RISCV_CPU, 1875 .parent = TYPE_CPU, 1876 .instance_size = sizeof(RISCVCPU), 1877 .instance_align = __alignof__(RISCVCPU), 1878 .instance_init = riscv_cpu_init, 1879 .abstract = true, 1880 .class_size = sizeof(RISCVCPUClass), 1881 .class_init = riscv_cpu_class_init, 1882 }, 1883 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1884 #if defined(CONFIG_KVM) 1885 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1886 #endif 1887 #if defined(TARGET_RISCV32) 1888 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1889 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1890 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1891 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1892 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1893 #elif defined(TARGET_RISCV64) 1894 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1895 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1896 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1897 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1898 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1899 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1900 #endif 1901 }; 1902 1903 DEFINE_TYPES(riscv_cpu_type_infos) 1904