1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "pmu.h" 26 #include "internals.h" 27 #include "time_helper.h" 28 #include "exec/exec-all.h" 29 #include "qapi/error.h" 30 #include "qemu/error-report.h" 31 #include "hw/qdev-properties.h" 32 #include "migration/vmstate.h" 33 #include "fpu/softfloat-helpers.h" 34 #include "sysemu/kvm.h" 35 #include "kvm_riscv.h" 36 37 /* RISC-V CPU definitions */ 38 39 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 40 (QEMU_VERSION_MINOR << 8) | \ 41 (QEMU_VERSION_MICRO)) 42 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 43 44 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 45 46 struct isa_ext_data { 47 const char *name; 48 bool multi_letter; 49 int min_version; 50 int ext_enable_offset; 51 }; 52 53 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ 54 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 55 56 /** 57 * Here are the ordering rules of extension naming defined by RISC-V 58 * specification : 59 * 1. All extensions should be separated from other multi-letter extensions 60 * by an underscore. 61 * 2. The first letter following the 'Z' conventionally indicates the most 62 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 63 * If multiple 'Z' extensions are named, they should be ordered first 64 * by category, then alphabetically within a category. 65 * 3. Standard supervisor-level extensions (starts with 'S') should be 66 * listed after standard unprivileged extensions. If multiple 67 * supervisor-level extensions are listed, they should be ordered 68 * alphabetically. 69 * 4. Non-standard extensions (starts with 'X') must be listed after all 70 * standard extensions. They must be separated from other multi-letter 71 * extensions by an underscore. 72 */ 73 static const struct isa_ext_data isa_edata_arr[] = { 74 ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), 75 ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_12_0, ext_v), 76 ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), 77 ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), 78 ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), 79 ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), 80 ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_12_0, ext_zfh), 81 ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), 82 ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), 83 ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), 84 ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), 85 ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), 86 ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), 87 ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), 88 ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), 89 ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), 90 ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), 91 ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), 92 ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), 93 ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), 94 ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), 95 ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), 96 ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), 97 ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), 98 ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), 99 ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), 100 ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), 101 ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), 102 ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), 103 ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), 104 ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), 105 ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), 106 ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), 107 ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), 108 ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), 109 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), 110 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), 111 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), 112 ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), 113 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 114 }; 115 116 static bool isa_ext_is_enabled(RISCVCPU *cpu, 117 const struct isa_ext_data *edata) 118 { 119 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 120 121 return *ext_enabled; 122 } 123 124 static void isa_ext_update_enabled(RISCVCPU *cpu, 125 const struct isa_ext_data *edata, bool en) 126 { 127 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 128 129 *ext_enabled = en; 130 } 131 132 const char * const riscv_int_regnames[] = { 133 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 134 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 135 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 136 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 137 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 138 }; 139 140 const char * const riscv_int_regnamesh[] = { 141 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 142 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 143 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 144 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 145 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 146 "x30h/t5h", "x31h/t6h" 147 }; 148 149 const char * const riscv_fpr_regnames[] = { 150 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 151 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 152 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 153 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 154 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 155 "f30/ft10", "f31/ft11" 156 }; 157 158 static const char * const riscv_excp_names[] = { 159 "misaligned_fetch", 160 "fault_fetch", 161 "illegal_instruction", 162 "breakpoint", 163 "misaligned_load", 164 "fault_load", 165 "misaligned_store", 166 "fault_store", 167 "user_ecall", 168 "supervisor_ecall", 169 "hypervisor_ecall", 170 "machine_ecall", 171 "exec_page_fault", 172 "load_page_fault", 173 "reserved", 174 "store_page_fault", 175 "reserved", 176 "reserved", 177 "reserved", 178 "reserved", 179 "guest_exec_page_fault", 180 "guest_load_page_fault", 181 "reserved", 182 "guest_store_page_fault", 183 }; 184 185 static const char * const riscv_intr_names[] = { 186 "u_software", 187 "s_software", 188 "vs_software", 189 "m_software", 190 "u_timer", 191 "s_timer", 192 "vs_timer", 193 "m_timer", 194 "u_external", 195 "s_external", 196 "vs_external", 197 "m_external", 198 "reserved", 199 "reserved", 200 "reserved", 201 "reserved" 202 }; 203 204 static void register_cpu_props(DeviceState *dev); 205 206 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 207 { 208 if (async) { 209 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 210 riscv_intr_names[cause] : "(unknown)"; 211 } else { 212 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 213 riscv_excp_names[cause] : "(unknown)"; 214 } 215 } 216 217 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 218 { 219 env->misa_mxl_max = env->misa_mxl = mxl; 220 env->misa_ext_mask = env->misa_ext = ext; 221 } 222 223 static void set_priv_version(CPURISCVState *env, int priv_ver) 224 { 225 env->priv_ver = priv_ver; 226 } 227 228 static void set_vext_version(CPURISCVState *env, int vext_ver) 229 { 230 env->vext_ver = vext_ver; 231 } 232 233 static void riscv_any_cpu_init(Object *obj) 234 { 235 CPURISCVState *env = &RISCV_CPU(obj)->env; 236 #if defined(TARGET_RISCV32) 237 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 238 #elif defined(TARGET_RISCV64) 239 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 240 #endif 241 set_priv_version(env, PRIV_VERSION_1_12_0); 242 register_cpu_props(DEVICE(obj)); 243 } 244 245 #if defined(TARGET_RISCV64) 246 static void rv64_base_cpu_init(Object *obj) 247 { 248 CPURISCVState *env = &RISCV_CPU(obj)->env; 249 /* We set this in the realise function */ 250 set_misa(env, MXL_RV64, 0); 251 register_cpu_props(DEVICE(obj)); 252 /* Set latest version of privileged specification */ 253 set_priv_version(env, PRIV_VERSION_1_12_0); 254 } 255 256 static void rv64_sifive_u_cpu_init(Object *obj) 257 { 258 CPURISCVState *env = &RISCV_CPU(obj)->env; 259 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 260 register_cpu_props(DEVICE(obj)); 261 set_priv_version(env, PRIV_VERSION_1_10_0); 262 } 263 264 static void rv64_sifive_e_cpu_init(Object *obj) 265 { 266 CPURISCVState *env = &RISCV_CPU(obj)->env; 267 RISCVCPU *cpu = RISCV_CPU(obj); 268 269 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 270 register_cpu_props(DEVICE(obj)); 271 set_priv_version(env, PRIV_VERSION_1_10_0); 272 cpu->cfg.mmu = false; 273 } 274 275 static void rv128_base_cpu_init(Object *obj) 276 { 277 if (qemu_tcg_mttcg_enabled()) { 278 /* Missing 128-bit aligned atomics */ 279 error_report("128-bit RISC-V currently does not work with Multi " 280 "Threaded TCG. Please use: -accel tcg,thread=single"); 281 exit(EXIT_FAILURE); 282 } 283 CPURISCVState *env = &RISCV_CPU(obj)->env; 284 /* We set this in the realise function */ 285 set_misa(env, MXL_RV128, 0); 286 register_cpu_props(DEVICE(obj)); 287 /* Set latest version of privileged specification */ 288 set_priv_version(env, PRIV_VERSION_1_12_0); 289 } 290 #else 291 static void rv32_base_cpu_init(Object *obj) 292 { 293 CPURISCVState *env = &RISCV_CPU(obj)->env; 294 /* We set this in the realise function */ 295 set_misa(env, MXL_RV32, 0); 296 register_cpu_props(DEVICE(obj)); 297 /* Set latest version of privileged specification */ 298 set_priv_version(env, PRIV_VERSION_1_12_0); 299 } 300 301 static void rv32_sifive_u_cpu_init(Object *obj) 302 { 303 CPURISCVState *env = &RISCV_CPU(obj)->env; 304 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 305 register_cpu_props(DEVICE(obj)); 306 set_priv_version(env, PRIV_VERSION_1_10_0); 307 } 308 309 static void rv32_sifive_e_cpu_init(Object *obj) 310 { 311 CPURISCVState *env = &RISCV_CPU(obj)->env; 312 RISCVCPU *cpu = RISCV_CPU(obj); 313 314 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 315 register_cpu_props(DEVICE(obj)); 316 set_priv_version(env, PRIV_VERSION_1_10_0); 317 cpu->cfg.mmu = false; 318 } 319 320 static void rv32_ibex_cpu_init(Object *obj) 321 { 322 CPURISCVState *env = &RISCV_CPU(obj)->env; 323 RISCVCPU *cpu = RISCV_CPU(obj); 324 325 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 326 register_cpu_props(DEVICE(obj)); 327 set_priv_version(env, PRIV_VERSION_1_11_0); 328 cpu->cfg.mmu = false; 329 cpu->cfg.epmp = true; 330 } 331 332 static void rv32_imafcu_nommu_cpu_init(Object *obj) 333 { 334 CPURISCVState *env = &RISCV_CPU(obj)->env; 335 RISCVCPU *cpu = RISCV_CPU(obj); 336 337 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 338 register_cpu_props(DEVICE(obj)); 339 set_priv_version(env, PRIV_VERSION_1_10_0); 340 cpu->cfg.mmu = false; 341 } 342 #endif 343 344 #if defined(CONFIG_KVM) 345 static void riscv_host_cpu_init(Object *obj) 346 { 347 CPURISCVState *env = &RISCV_CPU(obj)->env; 348 #if defined(TARGET_RISCV32) 349 set_misa(env, MXL_RV32, 0); 350 #elif defined(TARGET_RISCV64) 351 set_misa(env, MXL_RV64, 0); 352 #endif 353 register_cpu_props(DEVICE(obj)); 354 } 355 #endif 356 357 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 358 { 359 ObjectClass *oc; 360 char *typename; 361 char **cpuname; 362 363 cpuname = g_strsplit(cpu_model, ",", 1); 364 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 365 oc = object_class_by_name(typename); 366 g_strfreev(cpuname); 367 g_free(typename); 368 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 369 object_class_is_abstract(oc)) { 370 return NULL; 371 } 372 return oc; 373 } 374 375 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 376 { 377 RISCVCPU *cpu = RISCV_CPU(cs); 378 CPURISCVState *env = &cpu->env; 379 int i; 380 381 #if !defined(CONFIG_USER_ONLY) 382 if (riscv_has_ext(env, RVH)) { 383 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 384 } 385 #endif 386 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 387 #ifndef CONFIG_USER_ONLY 388 { 389 static const int dump_csrs[] = { 390 CSR_MHARTID, 391 CSR_MSTATUS, 392 CSR_MSTATUSH, 393 /* 394 * CSR_SSTATUS is intentionally omitted here as its value 395 * can be figured out by looking at CSR_MSTATUS 396 */ 397 CSR_HSTATUS, 398 CSR_VSSTATUS, 399 CSR_MIP, 400 CSR_MIE, 401 CSR_MIDELEG, 402 CSR_HIDELEG, 403 CSR_MEDELEG, 404 CSR_HEDELEG, 405 CSR_MTVEC, 406 CSR_STVEC, 407 CSR_VSTVEC, 408 CSR_MEPC, 409 CSR_SEPC, 410 CSR_VSEPC, 411 CSR_MCAUSE, 412 CSR_SCAUSE, 413 CSR_VSCAUSE, 414 CSR_MTVAL, 415 CSR_STVAL, 416 CSR_HTVAL, 417 CSR_MTVAL2, 418 CSR_MSCRATCH, 419 CSR_SSCRATCH, 420 CSR_SATP, 421 CSR_MMTE, 422 CSR_UPMBASE, 423 CSR_UPMMASK, 424 CSR_SPMBASE, 425 CSR_SPMMASK, 426 CSR_MPMBASE, 427 CSR_MPMMASK, 428 }; 429 430 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 431 int csrno = dump_csrs[i]; 432 target_ulong val = 0; 433 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 434 435 /* 436 * Rely on the smode, hmode, etc, predicates within csr.c 437 * to do the filtering of the registers that are present. 438 */ 439 if (res == RISCV_EXCP_NONE) { 440 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 441 csr_ops[csrno].name, val); 442 } 443 } 444 } 445 #endif 446 447 for (i = 0; i < 32; i++) { 448 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 449 riscv_int_regnames[i], env->gpr[i]); 450 if ((i & 3) == 3) { 451 qemu_fprintf(f, "\n"); 452 } 453 } 454 if (flags & CPU_DUMP_FPU) { 455 for (i = 0; i < 32; i++) { 456 qemu_fprintf(f, " %-8s %016" PRIx64, 457 riscv_fpr_regnames[i], env->fpr[i]); 458 if ((i & 3) == 3) { 459 qemu_fprintf(f, "\n"); 460 } 461 } 462 } 463 } 464 465 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 466 { 467 RISCVCPU *cpu = RISCV_CPU(cs); 468 CPURISCVState *env = &cpu->env; 469 470 if (env->xl == MXL_RV32) { 471 env->pc = (int32_t)value; 472 } else { 473 env->pc = value; 474 } 475 } 476 477 static vaddr riscv_cpu_get_pc(CPUState *cs) 478 { 479 RISCVCPU *cpu = RISCV_CPU(cs); 480 CPURISCVState *env = &cpu->env; 481 482 /* Match cpu_get_tb_cpu_state. */ 483 if (env->xl == MXL_RV32) { 484 return env->pc & UINT32_MAX; 485 } 486 return env->pc; 487 } 488 489 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 490 const TranslationBlock *tb) 491 { 492 RISCVCPU *cpu = RISCV_CPU(cs); 493 CPURISCVState *env = &cpu->env; 494 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 495 496 if (xl == MXL_RV32) { 497 env->pc = (int32_t)tb_pc(tb); 498 } else { 499 env->pc = tb_pc(tb); 500 } 501 } 502 503 static bool riscv_cpu_has_work(CPUState *cs) 504 { 505 #ifndef CONFIG_USER_ONLY 506 RISCVCPU *cpu = RISCV_CPU(cs); 507 CPURISCVState *env = &cpu->env; 508 /* 509 * Definition of the WFI instruction requires it to ignore the privilege 510 * mode and delegation registers, but respect individual enables 511 */ 512 return riscv_cpu_all_pending(env) != 0; 513 #else 514 return true; 515 #endif 516 } 517 518 static void riscv_restore_state_to_opc(CPUState *cs, 519 const TranslationBlock *tb, 520 const uint64_t *data) 521 { 522 RISCVCPU *cpu = RISCV_CPU(cs); 523 CPURISCVState *env = &cpu->env; 524 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 525 526 if (xl == MXL_RV32) { 527 env->pc = (int32_t)data[0]; 528 } else { 529 env->pc = data[0]; 530 } 531 env->bins = data[1]; 532 } 533 534 static void riscv_cpu_reset_hold(Object *obj) 535 { 536 #ifndef CONFIG_USER_ONLY 537 uint8_t iprio; 538 int i, irq, rdzero; 539 #endif 540 CPUState *cs = CPU(obj); 541 RISCVCPU *cpu = RISCV_CPU(cs); 542 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 543 CPURISCVState *env = &cpu->env; 544 545 if (mcc->parent_phases.hold) { 546 mcc->parent_phases.hold(obj); 547 } 548 #ifndef CONFIG_USER_ONLY 549 env->misa_mxl = env->misa_mxl_max; 550 env->priv = PRV_M; 551 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 552 if (env->misa_mxl > MXL_RV32) { 553 /* 554 * The reset status of SXL/UXL is undefined, but mstatus is WARL 555 * and we must ensure that the value after init is valid for read. 556 */ 557 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 558 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 559 if (riscv_has_ext(env, RVH)) { 560 env->vsstatus = set_field(env->vsstatus, 561 MSTATUS64_SXL, env->misa_mxl); 562 env->vsstatus = set_field(env->vsstatus, 563 MSTATUS64_UXL, env->misa_mxl); 564 env->mstatus_hs = set_field(env->mstatus_hs, 565 MSTATUS64_SXL, env->misa_mxl); 566 env->mstatus_hs = set_field(env->mstatus_hs, 567 MSTATUS64_UXL, env->misa_mxl); 568 } 569 } 570 env->mcause = 0; 571 env->miclaim = MIP_SGEIP; 572 env->pc = env->resetvec; 573 env->bins = 0; 574 env->two_stage_lookup = false; 575 576 /* Initialized default priorities of local interrupts. */ 577 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 578 iprio = riscv_cpu_default_priority(i); 579 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 580 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 581 env->hviprio[i] = 0; 582 } 583 i = 0; 584 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 585 if (!rdzero) { 586 env->hviprio[irq] = env->miprio[irq]; 587 } 588 i++; 589 } 590 /* mmte is supposed to have pm.current hardwired to 1 */ 591 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 592 #endif 593 env->xl = riscv_cpu_mxl(env); 594 riscv_cpu_update_mask(env); 595 cs->exception_index = RISCV_EXCP_NONE; 596 env->load_res = -1; 597 set_default_nan_mode(1, &env->fp_status); 598 599 #ifndef CONFIG_USER_ONLY 600 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 601 riscv_trigger_init(env); 602 } 603 604 if (kvm_enabled()) { 605 kvm_riscv_reset_vcpu(cpu); 606 } 607 #endif 608 } 609 610 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 611 { 612 RISCVCPU *cpu = RISCV_CPU(s); 613 614 switch (riscv_cpu_mxl(&cpu->env)) { 615 case MXL_RV32: 616 info->print_insn = print_insn_riscv32; 617 break; 618 case MXL_RV64: 619 info->print_insn = print_insn_riscv64; 620 break; 621 case MXL_RV128: 622 info->print_insn = print_insn_riscv128; 623 break; 624 default: 625 g_assert_not_reached(); 626 } 627 } 628 629 /* 630 * Check consistency between chosen extensions while setting 631 * cpu->cfg accordingly, doing a set_misa() in the end. 632 */ 633 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 634 { 635 CPURISCVState *env = &cpu->env; 636 uint32_t ext = 0; 637 638 /* Do some ISA extension error checking */ 639 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 640 cpu->cfg.ext_a && cpu->cfg.ext_f && 641 cpu->cfg.ext_d && 642 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 643 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 644 cpu->cfg.ext_i = true; 645 cpu->cfg.ext_m = true; 646 cpu->cfg.ext_a = true; 647 cpu->cfg.ext_f = true; 648 cpu->cfg.ext_d = true; 649 cpu->cfg.ext_icsr = true; 650 cpu->cfg.ext_ifencei = true; 651 } 652 653 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 654 error_setg(errp, 655 "I and E extensions are incompatible"); 656 return; 657 } 658 659 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 660 error_setg(errp, 661 "Either I or E extension must be set"); 662 return; 663 } 664 665 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 666 error_setg(errp, 667 "Setting S extension without U extension is illegal"); 668 return; 669 } 670 671 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { 672 error_setg(errp, 673 "H depends on an I base integer ISA with 32 x registers"); 674 return; 675 } 676 677 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 678 error_setg(errp, "H extension implicitly requires S-mode"); 679 return; 680 } 681 682 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 683 error_setg(errp, "F extension requires Zicsr"); 684 return; 685 } 686 687 if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { 688 error_setg(errp, "Zawrs extension requires A extension"); 689 return; 690 } 691 692 if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { 693 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 694 return; 695 } 696 697 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 698 error_setg(errp, "D extension requires F extension"); 699 return; 700 } 701 702 if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { 703 error_setg(errp, "V extension requires D extension"); 704 return; 705 } 706 707 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 708 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 709 return; 710 } 711 712 /* Set the ISA extensions, checks should have happened above */ 713 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || 714 cpu->cfg.ext_zhinxmin) { 715 cpu->cfg.ext_zfinx = true; 716 } 717 718 if (cpu->cfg.ext_zfinx) { 719 if (!cpu->cfg.ext_icsr) { 720 error_setg(errp, "Zfinx extension requires Zicsr"); 721 return; 722 } 723 if (cpu->cfg.ext_f) { 724 error_setg(errp, 725 "Zfinx cannot be supported together with F extension"); 726 return; 727 } 728 } 729 730 if (cpu->cfg.ext_zk) { 731 cpu->cfg.ext_zkn = true; 732 cpu->cfg.ext_zkr = true; 733 cpu->cfg.ext_zkt = true; 734 } 735 736 if (cpu->cfg.ext_zkn) { 737 cpu->cfg.ext_zbkb = true; 738 cpu->cfg.ext_zbkc = true; 739 cpu->cfg.ext_zbkx = true; 740 cpu->cfg.ext_zkne = true; 741 cpu->cfg.ext_zknd = true; 742 cpu->cfg.ext_zknh = true; 743 } 744 745 if (cpu->cfg.ext_zks) { 746 cpu->cfg.ext_zbkb = true; 747 cpu->cfg.ext_zbkc = true; 748 cpu->cfg.ext_zbkx = true; 749 cpu->cfg.ext_zksed = true; 750 cpu->cfg.ext_zksh = true; 751 } 752 753 if (cpu->cfg.ext_i) { 754 ext |= RVI; 755 } 756 if (cpu->cfg.ext_e) { 757 ext |= RVE; 758 } 759 if (cpu->cfg.ext_m) { 760 ext |= RVM; 761 } 762 if (cpu->cfg.ext_a) { 763 ext |= RVA; 764 } 765 if (cpu->cfg.ext_f) { 766 ext |= RVF; 767 } 768 if (cpu->cfg.ext_d) { 769 ext |= RVD; 770 } 771 if (cpu->cfg.ext_c) { 772 ext |= RVC; 773 } 774 if (cpu->cfg.ext_s) { 775 ext |= RVS; 776 } 777 if (cpu->cfg.ext_u) { 778 ext |= RVU; 779 } 780 if (cpu->cfg.ext_h) { 781 ext |= RVH; 782 } 783 if (cpu->cfg.ext_v) { 784 int vext_version = VEXT_VERSION_1_00_0; 785 ext |= RVV; 786 if (!is_power_of_2(cpu->cfg.vlen)) { 787 error_setg(errp, 788 "Vector extension VLEN must be power of 2"); 789 return; 790 } 791 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 792 error_setg(errp, 793 "Vector extension implementation only supports VLEN " 794 "in the range [128, %d]", RV_VLEN_MAX); 795 return; 796 } 797 if (!is_power_of_2(cpu->cfg.elen)) { 798 error_setg(errp, 799 "Vector extension ELEN must be power of 2"); 800 return; 801 } 802 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 803 error_setg(errp, 804 "Vector extension implementation only supports ELEN " 805 "in the range [8, 64]"); 806 return; 807 } 808 if (cpu->cfg.vext_spec) { 809 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 810 vext_version = VEXT_VERSION_1_00_0; 811 } else { 812 error_setg(errp, 813 "Unsupported vector spec version '%s'", 814 cpu->cfg.vext_spec); 815 return; 816 } 817 } else { 818 qemu_log("vector version is not specified, " 819 "use the default value v1.0\n"); 820 } 821 set_vext_version(env, vext_version); 822 } 823 if (cpu->cfg.ext_j) { 824 ext |= RVJ; 825 } 826 827 set_misa(env, env->misa_mxl, ext); 828 } 829 830 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 831 { 832 CPUState *cs = CPU(dev); 833 RISCVCPU *cpu = RISCV_CPU(dev); 834 CPURISCVState *env = &cpu->env; 835 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 836 CPUClass *cc = CPU_CLASS(mcc); 837 int i, priv_version = -1; 838 Error *local_err = NULL; 839 840 cpu_exec_realizefn(cs, &local_err); 841 if (local_err != NULL) { 842 error_propagate(errp, local_err); 843 return; 844 } 845 846 if (cpu->cfg.priv_spec) { 847 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 848 priv_version = PRIV_VERSION_1_12_0; 849 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 850 priv_version = PRIV_VERSION_1_11_0; 851 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 852 priv_version = PRIV_VERSION_1_10_0; 853 } else { 854 error_setg(errp, 855 "Unsupported privilege spec version '%s'", 856 cpu->cfg.priv_spec); 857 return; 858 } 859 } 860 861 if (priv_version >= PRIV_VERSION_1_10_0) { 862 set_priv_version(env, priv_version); 863 } 864 865 /* Force disable extensions if priv spec version does not match */ 866 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 867 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 868 (env->priv_ver < isa_edata_arr[i].min_version)) { 869 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 870 #ifndef CONFIG_USER_ONLY 871 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 872 " because privilege spec version does not match", 873 isa_edata_arr[i].name, env->mhartid); 874 #else 875 warn_report("disabling %s extension because " 876 "privilege spec version does not match", 877 isa_edata_arr[i].name); 878 #endif 879 } 880 } 881 882 if (cpu->cfg.mmu) { 883 riscv_set_feature(env, RISCV_FEATURE_MMU); 884 } 885 886 if (cpu->cfg.pmp) { 887 riscv_set_feature(env, RISCV_FEATURE_PMP); 888 889 /* 890 * Enhanced PMP should only be available 891 * on harts with PMP support 892 */ 893 if (cpu->cfg.epmp) { 894 riscv_set_feature(env, RISCV_FEATURE_EPMP); 895 } 896 } 897 898 if (cpu->cfg.debug) { 899 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 900 } 901 902 903 #ifndef CONFIG_USER_ONLY 904 if (cpu->cfg.ext_sstc) { 905 riscv_timer_init(cpu); 906 } 907 #endif /* CONFIG_USER_ONLY */ 908 909 /* Validate that MISA_MXL is set properly. */ 910 switch (env->misa_mxl_max) { 911 #ifdef TARGET_RISCV64 912 case MXL_RV64: 913 case MXL_RV128: 914 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 915 break; 916 #endif 917 case MXL_RV32: 918 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 919 break; 920 default: 921 g_assert_not_reached(); 922 } 923 assert(env->misa_mxl_max == env->misa_mxl); 924 925 riscv_cpu_validate_set_extensions(cpu, &local_err); 926 if (local_err != NULL) { 927 error_propagate(errp, local_err); 928 return; 929 } 930 931 #ifndef CONFIG_USER_ONLY 932 if (cpu->cfg.pmu_num) { 933 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 934 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 935 riscv_pmu_timer_cb, cpu); 936 } 937 } 938 #endif 939 940 riscv_cpu_register_gdb_regs_for_features(cs); 941 942 qemu_init_vcpu(cs); 943 cpu_reset(cs); 944 945 mcc->parent_realize(dev, errp); 946 } 947 948 #ifndef CONFIG_USER_ONLY 949 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 950 { 951 RISCVCPU *cpu = RISCV_CPU(opaque); 952 CPURISCVState *env = &cpu->env; 953 954 if (irq < IRQ_LOCAL_MAX) { 955 switch (irq) { 956 case IRQ_U_SOFT: 957 case IRQ_S_SOFT: 958 case IRQ_VS_SOFT: 959 case IRQ_M_SOFT: 960 case IRQ_U_TIMER: 961 case IRQ_S_TIMER: 962 case IRQ_VS_TIMER: 963 case IRQ_M_TIMER: 964 case IRQ_U_EXT: 965 case IRQ_VS_EXT: 966 case IRQ_M_EXT: 967 if (kvm_enabled()) { 968 kvm_riscv_set_irq(cpu, irq, level); 969 } else { 970 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 971 } 972 break; 973 case IRQ_S_EXT: 974 if (kvm_enabled()) { 975 kvm_riscv_set_irq(cpu, irq, level); 976 } else { 977 env->external_seip = level; 978 riscv_cpu_update_mip(cpu, 1 << irq, 979 BOOL_TO_MASK(level | env->software_seip)); 980 } 981 break; 982 default: 983 g_assert_not_reached(); 984 } 985 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 986 /* Require H-extension for handling guest local interrupts */ 987 if (!riscv_has_ext(env, RVH)) { 988 g_assert_not_reached(); 989 } 990 991 /* Compute bit position in HGEIP CSR */ 992 irq = irq - IRQ_LOCAL_MAX + 1; 993 if (env->geilen < irq) { 994 g_assert_not_reached(); 995 } 996 997 /* Update HGEIP CSR */ 998 env->hgeip &= ~((target_ulong)1 << irq); 999 if (level) { 1000 env->hgeip |= (target_ulong)1 << irq; 1001 } 1002 1003 /* Update mip.SGEIP bit */ 1004 riscv_cpu_update_mip(cpu, MIP_SGEIP, 1005 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1006 } else { 1007 g_assert_not_reached(); 1008 } 1009 } 1010 #endif /* CONFIG_USER_ONLY */ 1011 1012 static void riscv_cpu_init(Object *obj) 1013 { 1014 RISCVCPU *cpu = RISCV_CPU(obj); 1015 1016 cpu->cfg.ext_ifencei = true; 1017 cpu->cfg.ext_icsr = true; 1018 cpu->cfg.mmu = true; 1019 cpu->cfg.pmp = true; 1020 1021 cpu_set_cpustate_pointers(cpu); 1022 1023 #ifndef CONFIG_USER_ONLY 1024 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1025 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1026 #endif /* CONFIG_USER_ONLY */ 1027 } 1028 1029 static Property riscv_cpu_extensions[] = { 1030 /* Defaults for standard extensions */ 1031 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 1032 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 1033 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1034 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 1035 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 1036 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 1037 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 1038 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 1039 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 1040 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1041 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1042 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1043 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1044 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1045 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1046 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1047 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1048 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1049 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1050 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1051 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1052 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1053 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1054 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1055 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1056 1057 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1058 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1059 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1060 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1061 1062 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1063 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1064 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1065 1066 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1067 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1068 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1069 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1070 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1071 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1072 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1073 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1074 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1075 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1076 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1077 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1078 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1079 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1080 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1081 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1082 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1083 1084 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1085 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1086 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1087 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1088 1089 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1090 1091 /* Vendor-specific custom extensions */ 1092 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1093 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1094 1095 /* These are experimental so mark with 'x-' */ 1096 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1097 /* ePMP 0.9.3 */ 1098 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1099 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1100 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1101 1102 DEFINE_PROP_END_OF_LIST(), 1103 }; 1104 1105 /* 1106 * Register CPU props based on env.misa_ext. If a non-zero 1107 * value was set, register only the required cpu->cfg.ext_* 1108 * properties and leave. env.misa_ext = 0 means that we want 1109 * all the default properties to be registered. 1110 */ 1111 static void register_cpu_props(DeviceState *dev) 1112 { 1113 RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); 1114 uint32_t misa_ext = cpu->env.misa_ext; 1115 Property *prop; 1116 1117 /* 1118 * If misa_ext is not zero, set cfg properties now to 1119 * allow them to be read during riscv_cpu_realize() 1120 * later on. 1121 */ 1122 if (cpu->env.misa_ext != 0) { 1123 cpu->cfg.ext_i = misa_ext & RVI; 1124 cpu->cfg.ext_e = misa_ext & RVE; 1125 cpu->cfg.ext_m = misa_ext & RVM; 1126 cpu->cfg.ext_a = misa_ext & RVA; 1127 cpu->cfg.ext_f = misa_ext & RVF; 1128 cpu->cfg.ext_d = misa_ext & RVD; 1129 cpu->cfg.ext_v = misa_ext & RVV; 1130 cpu->cfg.ext_c = misa_ext & RVC; 1131 cpu->cfg.ext_s = misa_ext & RVS; 1132 cpu->cfg.ext_u = misa_ext & RVU; 1133 cpu->cfg.ext_h = misa_ext & RVH; 1134 cpu->cfg.ext_j = misa_ext & RVJ; 1135 1136 /* 1137 * We don't want to set the default riscv_cpu_extensions 1138 * in this case. 1139 */ 1140 return; 1141 } 1142 1143 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1144 qdev_property_add_static(dev, prop); 1145 } 1146 } 1147 1148 static Property riscv_cpu_properties[] = { 1149 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1150 1151 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1152 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1153 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1154 1155 #ifndef CONFIG_USER_ONLY 1156 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1157 #endif 1158 1159 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1160 1161 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1162 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1163 DEFINE_PROP_END_OF_LIST(), 1164 }; 1165 1166 static gchar *riscv_gdb_arch_name(CPUState *cs) 1167 { 1168 RISCVCPU *cpu = RISCV_CPU(cs); 1169 CPURISCVState *env = &cpu->env; 1170 1171 switch (riscv_cpu_mxl(env)) { 1172 case MXL_RV32: 1173 return g_strdup("riscv:rv32"); 1174 case MXL_RV64: 1175 case MXL_RV128: 1176 return g_strdup("riscv:rv64"); 1177 default: 1178 g_assert_not_reached(); 1179 } 1180 } 1181 1182 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1183 { 1184 RISCVCPU *cpu = RISCV_CPU(cs); 1185 1186 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1187 return cpu->dyn_csr_xml; 1188 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1189 return cpu->dyn_vreg_xml; 1190 } 1191 1192 return NULL; 1193 } 1194 1195 #ifndef CONFIG_USER_ONLY 1196 #include "hw/core/sysemu-cpu-ops.h" 1197 1198 static const struct SysemuCPUOps riscv_sysemu_ops = { 1199 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1200 .write_elf64_note = riscv_cpu_write_elf64_note, 1201 .write_elf32_note = riscv_cpu_write_elf32_note, 1202 .legacy_vmsd = &vmstate_riscv_cpu, 1203 }; 1204 #endif 1205 1206 #include "hw/core/tcg-cpu-ops.h" 1207 1208 static const struct TCGCPUOps riscv_tcg_ops = { 1209 .initialize = riscv_translate_init, 1210 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1211 .restore_state_to_opc = riscv_restore_state_to_opc, 1212 1213 #ifndef CONFIG_USER_ONLY 1214 .tlb_fill = riscv_cpu_tlb_fill, 1215 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1216 .do_interrupt = riscv_cpu_do_interrupt, 1217 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1218 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1219 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1220 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1221 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1222 #endif /* !CONFIG_USER_ONLY */ 1223 }; 1224 1225 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1226 { 1227 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1228 CPUClass *cc = CPU_CLASS(c); 1229 DeviceClass *dc = DEVICE_CLASS(c); 1230 ResettableClass *rc = RESETTABLE_CLASS(c); 1231 1232 device_class_set_parent_realize(dc, riscv_cpu_realize, 1233 &mcc->parent_realize); 1234 1235 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1236 &mcc->parent_phases); 1237 1238 cc->class_by_name = riscv_cpu_class_by_name; 1239 cc->has_work = riscv_cpu_has_work; 1240 cc->dump_state = riscv_cpu_dump_state; 1241 cc->set_pc = riscv_cpu_set_pc; 1242 cc->get_pc = riscv_cpu_get_pc; 1243 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1244 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1245 cc->gdb_num_core_regs = 33; 1246 cc->gdb_stop_before_watchpoint = true; 1247 cc->disas_set_info = riscv_cpu_disas_set_info; 1248 #ifndef CONFIG_USER_ONLY 1249 cc->sysemu_ops = &riscv_sysemu_ops; 1250 #endif 1251 cc->gdb_arch_name = riscv_gdb_arch_name; 1252 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1253 cc->tcg_ops = &riscv_tcg_ops; 1254 1255 device_class_set_props(dc, riscv_cpu_properties); 1256 } 1257 1258 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1259 { 1260 char *old = *isa_str; 1261 char *new = *isa_str; 1262 int i; 1263 1264 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1265 if (isa_edata_arr[i].multi_letter && 1266 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1267 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1268 g_free(old); 1269 old = new; 1270 } 1271 } 1272 1273 *isa_str = new; 1274 } 1275 1276 char *riscv_isa_string(RISCVCPU *cpu) 1277 { 1278 int i; 1279 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1280 char *isa_str = g_new(char, maxlen); 1281 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1282 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1283 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1284 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1285 } 1286 } 1287 *p = '\0'; 1288 if (!cpu->cfg.short_isa_string) { 1289 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1290 } 1291 return isa_str; 1292 } 1293 1294 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1295 { 1296 ObjectClass *class_a = (ObjectClass *)a; 1297 ObjectClass *class_b = (ObjectClass *)b; 1298 const char *name_a, *name_b; 1299 1300 name_a = object_class_get_name(class_a); 1301 name_b = object_class_get_name(class_b); 1302 return strcmp(name_a, name_b); 1303 } 1304 1305 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1306 { 1307 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1308 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1309 1310 qemu_printf("%.*s\n", len, typename); 1311 } 1312 1313 void riscv_cpu_list(void) 1314 { 1315 GSList *list; 1316 1317 list = object_class_get_list(TYPE_RISCV_CPU, false); 1318 list = g_slist_sort(list, riscv_cpu_list_compare); 1319 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1320 g_slist_free(list); 1321 } 1322 1323 #define DEFINE_CPU(type_name, initfn) \ 1324 { \ 1325 .name = type_name, \ 1326 .parent = TYPE_RISCV_CPU, \ 1327 .instance_init = initfn \ 1328 } 1329 1330 static const TypeInfo riscv_cpu_type_infos[] = { 1331 { 1332 .name = TYPE_RISCV_CPU, 1333 .parent = TYPE_CPU, 1334 .instance_size = sizeof(RISCVCPU), 1335 .instance_align = __alignof__(RISCVCPU), 1336 .instance_init = riscv_cpu_init, 1337 .abstract = true, 1338 .class_size = sizeof(RISCVCPUClass), 1339 .class_init = riscv_cpu_class_init, 1340 }, 1341 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1342 #if defined(CONFIG_KVM) 1343 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1344 #endif 1345 #if defined(TARGET_RISCV32) 1346 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1347 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1348 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1349 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1350 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1351 #elif defined(TARGET_RISCV64) 1352 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1353 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1354 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1355 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1356 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1357 #endif 1358 }; 1359 1360 DEFINE_TYPES(riscv_cpu_type_infos) 1361