1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "exec/exec-all.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "fpu/softfloat-helpers.h" 32 #include "sysemu/kvm.h" 33 #include "kvm_riscv.h" 34 35 /* RISC-V CPU definitions */ 36 37 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 38 (QEMU_VERSION_MINOR << 8) | \ 39 (QEMU_VERSION_MICRO)) 40 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 41 42 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 43 44 struct isa_ext_data { 45 const char *name; 46 bool enabled; 47 }; 48 49 const char * const riscv_int_regnames[] = { 50 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 51 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 52 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 53 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 54 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 55 }; 56 57 const char * const riscv_int_regnamesh[] = { 58 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 59 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 60 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 61 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 62 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 63 "x30h/t5h", "x31h/t6h" 64 }; 65 66 const char * const riscv_fpr_regnames[] = { 67 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 68 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 69 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 70 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 71 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 72 "f30/ft10", "f31/ft11" 73 }; 74 75 static const char * const riscv_excp_names[] = { 76 "misaligned_fetch", 77 "fault_fetch", 78 "illegal_instruction", 79 "breakpoint", 80 "misaligned_load", 81 "fault_load", 82 "misaligned_store", 83 "fault_store", 84 "user_ecall", 85 "supervisor_ecall", 86 "hypervisor_ecall", 87 "machine_ecall", 88 "exec_page_fault", 89 "load_page_fault", 90 "reserved", 91 "store_page_fault", 92 "reserved", 93 "reserved", 94 "reserved", 95 "reserved", 96 "guest_exec_page_fault", 97 "guest_load_page_fault", 98 "reserved", 99 "guest_store_page_fault", 100 }; 101 102 static const char * const riscv_intr_names[] = { 103 "u_software", 104 "s_software", 105 "vs_software", 106 "m_software", 107 "u_timer", 108 "s_timer", 109 "vs_timer", 110 "m_timer", 111 "u_external", 112 "s_external", 113 "vs_external", 114 "m_external", 115 "reserved", 116 "reserved", 117 "reserved", 118 "reserved" 119 }; 120 121 static void register_cpu_props(DeviceState *dev); 122 123 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 124 { 125 if (async) { 126 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 127 riscv_intr_names[cause] : "(unknown)"; 128 } else { 129 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 130 riscv_excp_names[cause] : "(unknown)"; 131 } 132 } 133 134 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 135 { 136 env->misa_mxl_max = env->misa_mxl = mxl; 137 env->misa_ext_mask = env->misa_ext = ext; 138 } 139 140 static void set_priv_version(CPURISCVState *env, int priv_ver) 141 { 142 env->priv_ver = priv_ver; 143 } 144 145 static void set_vext_version(CPURISCVState *env, int vext_ver) 146 { 147 env->vext_ver = vext_ver; 148 } 149 150 static void set_resetvec(CPURISCVState *env, target_ulong resetvec) 151 { 152 #ifndef CONFIG_USER_ONLY 153 env->resetvec = resetvec; 154 #endif 155 } 156 157 static void riscv_any_cpu_init(Object *obj) 158 { 159 CPURISCVState *env = &RISCV_CPU(obj)->env; 160 #if defined(TARGET_RISCV32) 161 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 162 #elif defined(TARGET_RISCV64) 163 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 164 #endif 165 set_priv_version(env, PRIV_VERSION_1_12_0); 166 register_cpu_props(DEVICE(obj)); 167 } 168 169 #if defined(TARGET_RISCV64) 170 static void rv64_base_cpu_init(Object *obj) 171 { 172 CPURISCVState *env = &RISCV_CPU(obj)->env; 173 /* We set this in the realise function */ 174 set_misa(env, MXL_RV64, 0); 175 register_cpu_props(DEVICE(obj)); 176 /* Set latest version of privileged specification */ 177 set_priv_version(env, PRIV_VERSION_1_12_0); 178 } 179 180 static void rv64_sifive_u_cpu_init(Object *obj) 181 { 182 CPURISCVState *env = &RISCV_CPU(obj)->env; 183 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 184 set_priv_version(env, PRIV_VERSION_1_10_0); 185 } 186 187 static void rv64_sifive_e_cpu_init(Object *obj) 188 { 189 CPURISCVState *env = &RISCV_CPU(obj)->env; 190 RISCVCPU *cpu = RISCV_CPU(obj); 191 192 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 193 set_priv_version(env, PRIV_VERSION_1_10_0); 194 cpu->cfg.mmu = false; 195 } 196 197 static void rv128_base_cpu_init(Object *obj) 198 { 199 if (qemu_tcg_mttcg_enabled()) { 200 /* Missing 128-bit aligned atomics */ 201 error_report("128-bit RISC-V currently does not work with Multi " 202 "Threaded TCG. Please use: -accel tcg,thread=single"); 203 exit(EXIT_FAILURE); 204 } 205 CPURISCVState *env = &RISCV_CPU(obj)->env; 206 /* We set this in the realise function */ 207 set_misa(env, MXL_RV128, 0); 208 register_cpu_props(DEVICE(obj)); 209 /* Set latest version of privileged specification */ 210 set_priv_version(env, PRIV_VERSION_1_12_0); 211 } 212 #else 213 static void rv32_base_cpu_init(Object *obj) 214 { 215 CPURISCVState *env = &RISCV_CPU(obj)->env; 216 /* We set this in the realise function */ 217 set_misa(env, MXL_RV32, 0); 218 register_cpu_props(DEVICE(obj)); 219 /* Set latest version of privileged specification */ 220 set_priv_version(env, PRIV_VERSION_1_12_0); 221 } 222 223 static void rv32_sifive_u_cpu_init(Object *obj) 224 { 225 CPURISCVState *env = &RISCV_CPU(obj)->env; 226 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 227 set_priv_version(env, PRIV_VERSION_1_10_0); 228 } 229 230 static void rv32_sifive_e_cpu_init(Object *obj) 231 { 232 CPURISCVState *env = &RISCV_CPU(obj)->env; 233 RISCVCPU *cpu = RISCV_CPU(obj); 234 235 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 236 set_priv_version(env, PRIV_VERSION_1_10_0); 237 cpu->cfg.mmu = false; 238 } 239 240 static void rv32_ibex_cpu_init(Object *obj) 241 { 242 CPURISCVState *env = &RISCV_CPU(obj)->env; 243 RISCVCPU *cpu = RISCV_CPU(obj); 244 245 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 246 set_priv_version(env, PRIV_VERSION_1_11_0); 247 cpu->cfg.mmu = false; 248 cpu->cfg.epmp = true; 249 } 250 251 static void rv32_imafcu_nommu_cpu_init(Object *obj) 252 { 253 CPURISCVState *env = &RISCV_CPU(obj)->env; 254 RISCVCPU *cpu = RISCV_CPU(obj); 255 256 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 257 set_priv_version(env, PRIV_VERSION_1_10_0); 258 set_resetvec(env, DEFAULT_RSTVEC); 259 cpu->cfg.mmu = false; 260 } 261 #endif 262 263 #if defined(CONFIG_KVM) 264 static void riscv_host_cpu_init(Object *obj) 265 { 266 CPURISCVState *env = &RISCV_CPU(obj)->env; 267 #if defined(TARGET_RISCV32) 268 set_misa(env, MXL_RV32, 0); 269 #elif defined(TARGET_RISCV64) 270 set_misa(env, MXL_RV64, 0); 271 #endif 272 register_cpu_props(DEVICE(obj)); 273 } 274 #endif 275 276 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 277 { 278 ObjectClass *oc; 279 char *typename; 280 char **cpuname; 281 282 cpuname = g_strsplit(cpu_model, ",", 1); 283 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 284 oc = object_class_by_name(typename); 285 g_strfreev(cpuname); 286 g_free(typename); 287 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 288 object_class_is_abstract(oc)) { 289 return NULL; 290 } 291 return oc; 292 } 293 294 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 295 { 296 RISCVCPU *cpu = RISCV_CPU(cs); 297 CPURISCVState *env = &cpu->env; 298 int i; 299 300 #if !defined(CONFIG_USER_ONLY) 301 if (riscv_has_ext(env, RVH)) { 302 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 303 } 304 #endif 305 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 306 #ifndef CONFIG_USER_ONLY 307 { 308 static const int dump_csrs[] = { 309 CSR_MHARTID, 310 CSR_MSTATUS, 311 CSR_MSTATUSH, 312 CSR_HSTATUS, 313 CSR_VSSTATUS, 314 CSR_MIP, 315 CSR_MIE, 316 CSR_MIDELEG, 317 CSR_HIDELEG, 318 CSR_MEDELEG, 319 CSR_HEDELEG, 320 CSR_MTVEC, 321 CSR_STVEC, 322 CSR_VSTVEC, 323 CSR_MEPC, 324 CSR_SEPC, 325 CSR_VSEPC, 326 CSR_MCAUSE, 327 CSR_SCAUSE, 328 CSR_VSCAUSE, 329 CSR_MTVAL, 330 CSR_STVAL, 331 CSR_HTVAL, 332 CSR_MTVAL2, 333 CSR_MSCRATCH, 334 CSR_SSCRATCH, 335 CSR_SATP, 336 CSR_MMTE, 337 CSR_UPMBASE, 338 CSR_UPMMASK, 339 CSR_SPMBASE, 340 CSR_SPMMASK, 341 CSR_MPMBASE, 342 CSR_MPMMASK, 343 }; 344 345 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 346 int csrno = dump_csrs[i]; 347 target_ulong val = 0; 348 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 349 350 /* 351 * Rely on the smode, hmode, etc, predicates within csr.c 352 * to do the filtering of the registers that are present. 353 */ 354 if (res == RISCV_EXCP_NONE) { 355 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 356 csr_ops[csrno].name, val); 357 } 358 } 359 } 360 #endif 361 362 for (i = 0; i < 32; i++) { 363 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 364 riscv_int_regnames[i], env->gpr[i]); 365 if ((i & 3) == 3) { 366 qemu_fprintf(f, "\n"); 367 } 368 } 369 if (flags & CPU_DUMP_FPU) { 370 for (i = 0; i < 32; i++) { 371 qemu_fprintf(f, " %-8s %016" PRIx64, 372 riscv_fpr_regnames[i], env->fpr[i]); 373 if ((i & 3) == 3) { 374 qemu_fprintf(f, "\n"); 375 } 376 } 377 } 378 } 379 380 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 381 { 382 RISCVCPU *cpu = RISCV_CPU(cs); 383 CPURISCVState *env = &cpu->env; 384 385 if (env->xl == MXL_RV32) { 386 env->pc = (int32_t)value; 387 } else { 388 env->pc = value; 389 } 390 } 391 392 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 393 const TranslationBlock *tb) 394 { 395 RISCVCPU *cpu = RISCV_CPU(cs); 396 CPURISCVState *env = &cpu->env; 397 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 398 399 if (xl == MXL_RV32) { 400 env->pc = (int32_t)tb->pc; 401 } else { 402 env->pc = tb->pc; 403 } 404 } 405 406 static bool riscv_cpu_has_work(CPUState *cs) 407 { 408 #ifndef CONFIG_USER_ONLY 409 RISCVCPU *cpu = RISCV_CPU(cs); 410 CPURISCVState *env = &cpu->env; 411 /* 412 * Definition of the WFI instruction requires it to ignore the privilege 413 * mode and delegation registers, but respect individual enables 414 */ 415 return riscv_cpu_all_pending(env) != 0; 416 #else 417 return true; 418 #endif 419 } 420 421 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 422 target_ulong *data) 423 { 424 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 425 if (xl == MXL_RV32) { 426 env->pc = (int32_t)data[0]; 427 } else { 428 env->pc = data[0]; 429 } 430 env->bins = data[1]; 431 } 432 433 static void riscv_cpu_reset(DeviceState *dev) 434 { 435 #ifndef CONFIG_USER_ONLY 436 uint8_t iprio; 437 int i, irq, rdzero; 438 #endif 439 CPUState *cs = CPU(dev); 440 RISCVCPU *cpu = RISCV_CPU(cs); 441 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 442 CPURISCVState *env = &cpu->env; 443 444 mcc->parent_reset(dev); 445 #ifndef CONFIG_USER_ONLY 446 env->misa_mxl = env->misa_mxl_max; 447 env->priv = PRV_M; 448 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 449 if (env->misa_mxl > MXL_RV32) { 450 /* 451 * The reset status of SXL/UXL is undefined, but mstatus is WARL 452 * and we must ensure that the value after init is valid for read. 453 */ 454 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 455 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 456 if (riscv_has_ext(env, RVH)) { 457 env->vsstatus = set_field(env->vsstatus, 458 MSTATUS64_SXL, env->misa_mxl); 459 env->vsstatus = set_field(env->vsstatus, 460 MSTATUS64_UXL, env->misa_mxl); 461 env->mstatus_hs = set_field(env->mstatus_hs, 462 MSTATUS64_SXL, env->misa_mxl); 463 env->mstatus_hs = set_field(env->mstatus_hs, 464 MSTATUS64_UXL, env->misa_mxl); 465 } 466 } 467 env->mcause = 0; 468 env->miclaim = MIP_SGEIP; 469 env->pc = env->resetvec; 470 env->bins = 0; 471 env->two_stage_lookup = false; 472 473 /* Initialized default priorities of local interrupts. */ 474 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 475 iprio = riscv_cpu_default_priority(i); 476 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 477 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 478 env->hviprio[i] = 0; 479 } 480 i = 0; 481 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 482 if (!rdzero) { 483 env->hviprio[irq] = env->miprio[irq]; 484 } 485 i++; 486 } 487 /* mmte is supposed to have pm.current hardwired to 1 */ 488 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 489 #endif 490 env->xl = riscv_cpu_mxl(env); 491 riscv_cpu_update_mask(env); 492 cs->exception_index = RISCV_EXCP_NONE; 493 env->load_res = -1; 494 set_default_nan_mode(1, &env->fp_status); 495 496 #ifndef CONFIG_USER_ONLY 497 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 498 riscv_trigger_init(env); 499 } 500 501 if (kvm_enabled()) { 502 kvm_riscv_reset_vcpu(cpu); 503 } 504 #endif 505 } 506 507 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 508 { 509 RISCVCPU *cpu = RISCV_CPU(s); 510 511 switch (riscv_cpu_mxl(&cpu->env)) { 512 case MXL_RV32: 513 info->print_insn = print_insn_riscv32; 514 break; 515 case MXL_RV64: 516 info->print_insn = print_insn_riscv64; 517 break; 518 case MXL_RV128: 519 info->print_insn = print_insn_riscv128; 520 break; 521 default: 522 g_assert_not_reached(); 523 } 524 } 525 526 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 527 { 528 CPUState *cs = CPU(dev); 529 RISCVCPU *cpu = RISCV_CPU(dev); 530 CPURISCVState *env = &cpu->env; 531 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 532 CPUClass *cc = CPU_CLASS(mcc); 533 int priv_version = -1; 534 Error *local_err = NULL; 535 536 cpu_exec_realizefn(cs, &local_err); 537 if (local_err != NULL) { 538 error_propagate(errp, local_err); 539 return; 540 } 541 542 if (cpu->cfg.priv_spec) { 543 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 544 priv_version = PRIV_VERSION_1_12_0; 545 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 546 priv_version = PRIV_VERSION_1_11_0; 547 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 548 priv_version = PRIV_VERSION_1_10_0; 549 } else { 550 error_setg(errp, 551 "Unsupported privilege spec version '%s'", 552 cpu->cfg.priv_spec); 553 return; 554 } 555 } 556 557 if (priv_version >= PRIV_VERSION_1_10_0) { 558 set_priv_version(env, priv_version); 559 } 560 561 if (cpu->cfg.mmu) { 562 riscv_set_feature(env, RISCV_FEATURE_MMU); 563 } 564 565 if (cpu->cfg.pmp) { 566 riscv_set_feature(env, RISCV_FEATURE_PMP); 567 568 /* 569 * Enhanced PMP should only be available 570 * on harts with PMP support 571 */ 572 if (cpu->cfg.epmp) { 573 riscv_set_feature(env, RISCV_FEATURE_EPMP); 574 } 575 } 576 577 if (cpu->cfg.aia) { 578 riscv_set_feature(env, RISCV_FEATURE_AIA); 579 } 580 581 if (cpu->cfg.debug) { 582 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 583 } 584 585 set_resetvec(env, cpu->cfg.resetvec); 586 587 /* Validate that MISA_MXL is set properly. */ 588 switch (env->misa_mxl_max) { 589 #ifdef TARGET_RISCV64 590 case MXL_RV64: 591 case MXL_RV128: 592 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 593 break; 594 #endif 595 case MXL_RV32: 596 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 597 break; 598 default: 599 g_assert_not_reached(); 600 } 601 assert(env->misa_mxl_max == env->misa_mxl); 602 603 /* If only MISA_EXT is unset for misa, then set it from properties */ 604 if (env->misa_ext == 0) { 605 uint32_t ext = 0; 606 607 /* Do some ISA extension error checking */ 608 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 609 cpu->cfg.ext_a && cpu->cfg.ext_f && 610 cpu->cfg.ext_d && 611 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 612 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 613 cpu->cfg.ext_i = true; 614 cpu->cfg.ext_m = true; 615 cpu->cfg.ext_a = true; 616 cpu->cfg.ext_f = true; 617 cpu->cfg.ext_d = true; 618 cpu->cfg.ext_icsr = true; 619 cpu->cfg.ext_ifencei = true; 620 } 621 622 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 623 error_setg(errp, 624 "I and E extensions are incompatible"); 625 return; 626 } 627 628 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 629 error_setg(errp, 630 "Either I or E extension must be set"); 631 return; 632 } 633 634 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 635 error_setg(errp, "F extension requires Zicsr"); 636 return; 637 } 638 639 if ((cpu->cfg.ext_zfh || cpu->cfg.ext_zfhmin) && !cpu->cfg.ext_f) { 640 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 641 return; 642 } 643 644 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 645 error_setg(errp, "D extension requires F extension"); 646 return; 647 } 648 649 if (cpu->cfg.ext_v && !cpu->cfg.ext_d) { 650 error_setg(errp, "V extension requires D extension"); 651 return; 652 } 653 654 if ((cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) && !cpu->cfg.ext_f) { 655 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 656 return; 657 } 658 659 /* Set the ISA extensions, checks should have happened above */ 660 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || 661 cpu->cfg.ext_zhinxmin) { 662 cpu->cfg.ext_zfinx = true; 663 } 664 665 if (cpu->cfg.ext_zfinx) { 666 if (!cpu->cfg.ext_icsr) { 667 error_setg(errp, "Zfinx extension requires Zicsr"); 668 return; 669 } 670 if (cpu->cfg.ext_f) { 671 error_setg(errp, 672 "Zfinx cannot be supported together with F extension"); 673 return; 674 } 675 } 676 677 if (cpu->cfg.ext_zk) { 678 cpu->cfg.ext_zkn = true; 679 cpu->cfg.ext_zkr = true; 680 cpu->cfg.ext_zkt = true; 681 } 682 683 if (cpu->cfg.ext_zkn) { 684 cpu->cfg.ext_zbkb = true; 685 cpu->cfg.ext_zbkc = true; 686 cpu->cfg.ext_zbkx = true; 687 cpu->cfg.ext_zkne = true; 688 cpu->cfg.ext_zknd = true; 689 cpu->cfg.ext_zknh = true; 690 } 691 692 if (cpu->cfg.ext_zks) { 693 cpu->cfg.ext_zbkb = true; 694 cpu->cfg.ext_zbkc = true; 695 cpu->cfg.ext_zbkx = true; 696 cpu->cfg.ext_zksed = true; 697 cpu->cfg.ext_zksh = true; 698 } 699 700 if (cpu->cfg.ext_i) { 701 ext |= RVI; 702 } 703 if (cpu->cfg.ext_e) { 704 ext |= RVE; 705 } 706 if (cpu->cfg.ext_m) { 707 ext |= RVM; 708 } 709 if (cpu->cfg.ext_a) { 710 ext |= RVA; 711 } 712 if (cpu->cfg.ext_f) { 713 ext |= RVF; 714 } 715 if (cpu->cfg.ext_d) { 716 ext |= RVD; 717 } 718 if (cpu->cfg.ext_c) { 719 ext |= RVC; 720 } 721 if (cpu->cfg.ext_s) { 722 ext |= RVS; 723 } 724 if (cpu->cfg.ext_u) { 725 ext |= RVU; 726 } 727 if (cpu->cfg.ext_h) { 728 ext |= RVH; 729 } 730 if (cpu->cfg.ext_v) { 731 int vext_version = VEXT_VERSION_1_00_0; 732 ext |= RVV; 733 if (!is_power_of_2(cpu->cfg.vlen)) { 734 error_setg(errp, 735 "Vector extension VLEN must be power of 2"); 736 return; 737 } 738 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 739 error_setg(errp, 740 "Vector extension implementation only supports VLEN " 741 "in the range [128, %d]", RV_VLEN_MAX); 742 return; 743 } 744 if (!is_power_of_2(cpu->cfg.elen)) { 745 error_setg(errp, 746 "Vector extension ELEN must be power of 2"); 747 return; 748 } 749 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 750 error_setg(errp, 751 "Vector extension implementation only supports ELEN " 752 "in the range [8, 64]"); 753 return; 754 } 755 if (cpu->cfg.vext_spec) { 756 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 757 vext_version = VEXT_VERSION_1_00_0; 758 } else { 759 error_setg(errp, 760 "Unsupported vector spec version '%s'", 761 cpu->cfg.vext_spec); 762 return; 763 } 764 } else { 765 qemu_log("vector version is not specified, " 766 "use the default value v1.0\n"); 767 } 768 set_vext_version(env, vext_version); 769 } 770 if (cpu->cfg.ext_j) { 771 ext |= RVJ; 772 } 773 774 set_misa(env, env->misa_mxl, ext); 775 } 776 777 riscv_cpu_register_gdb_regs_for_features(cs); 778 779 qemu_init_vcpu(cs); 780 cpu_reset(cs); 781 782 mcc->parent_realize(dev, errp); 783 } 784 785 #ifndef CONFIG_USER_ONLY 786 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 787 { 788 RISCVCPU *cpu = RISCV_CPU(opaque); 789 CPURISCVState *env = &cpu->env; 790 791 if (irq < IRQ_LOCAL_MAX) { 792 switch (irq) { 793 case IRQ_U_SOFT: 794 case IRQ_S_SOFT: 795 case IRQ_VS_SOFT: 796 case IRQ_M_SOFT: 797 case IRQ_U_TIMER: 798 case IRQ_S_TIMER: 799 case IRQ_VS_TIMER: 800 case IRQ_M_TIMER: 801 case IRQ_U_EXT: 802 case IRQ_VS_EXT: 803 case IRQ_M_EXT: 804 if (kvm_enabled()) { 805 kvm_riscv_set_irq(cpu, irq, level); 806 } else { 807 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 808 } 809 break; 810 case IRQ_S_EXT: 811 if (kvm_enabled()) { 812 kvm_riscv_set_irq(cpu, irq, level); 813 } else { 814 env->external_seip = level; 815 riscv_cpu_update_mip(cpu, 1 << irq, 816 BOOL_TO_MASK(level | env->software_seip)); 817 } 818 break; 819 default: 820 g_assert_not_reached(); 821 } 822 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 823 /* Require H-extension for handling guest local interrupts */ 824 if (!riscv_has_ext(env, RVH)) { 825 g_assert_not_reached(); 826 } 827 828 /* Compute bit position in HGEIP CSR */ 829 irq = irq - IRQ_LOCAL_MAX + 1; 830 if (env->geilen < irq) { 831 g_assert_not_reached(); 832 } 833 834 /* Update HGEIP CSR */ 835 env->hgeip &= ~((target_ulong)1 << irq); 836 if (level) { 837 env->hgeip |= (target_ulong)1 << irq; 838 } 839 840 /* Update mip.SGEIP bit */ 841 riscv_cpu_update_mip(cpu, MIP_SGEIP, 842 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 843 } else { 844 g_assert_not_reached(); 845 } 846 } 847 #endif /* CONFIG_USER_ONLY */ 848 849 static void riscv_cpu_init(Object *obj) 850 { 851 RISCVCPU *cpu = RISCV_CPU(obj); 852 853 cpu->cfg.ext_ifencei = true; 854 cpu->cfg.ext_icsr = true; 855 cpu->cfg.mmu = true; 856 cpu->cfg.pmp = true; 857 858 cpu_set_cpustate_pointers(cpu); 859 860 #ifndef CONFIG_USER_ONLY 861 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 862 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 863 #endif /* CONFIG_USER_ONLY */ 864 } 865 866 static Property riscv_cpu_extensions[] = { 867 /* Defaults for standard extensions */ 868 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 869 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 870 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 871 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 872 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 873 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 874 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 875 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 876 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 877 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 878 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 879 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 880 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 881 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 882 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 883 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 884 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 885 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 886 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 887 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 888 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 889 890 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 891 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 892 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 893 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 894 895 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 896 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 897 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 898 899 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 900 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 901 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 902 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 903 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 904 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 905 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 906 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 907 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 908 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 909 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 910 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 911 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 912 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 913 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 914 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 915 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 916 917 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 918 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 919 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 920 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 921 922 /* Vendor-specific custom extensions */ 923 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 924 925 /* These are experimental so mark with 'x-' */ 926 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 927 DEFINE_PROP_BOOL("x-zmmul", RISCVCPU, cfg.ext_zmmul, false), 928 /* ePMP 0.9.3 */ 929 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 930 DEFINE_PROP_BOOL("x-aia", RISCVCPU, cfg.aia, false), 931 932 DEFINE_PROP_END_OF_LIST(), 933 }; 934 935 static void register_cpu_props(DeviceState *dev) 936 { 937 Property *prop; 938 939 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 940 qdev_property_add_static(dev, prop); 941 } 942 } 943 944 static Property riscv_cpu_properties[] = { 945 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 946 947 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 948 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 949 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 950 951 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 952 953 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 954 955 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 956 DEFINE_PROP_END_OF_LIST(), 957 }; 958 959 static gchar *riscv_gdb_arch_name(CPUState *cs) 960 { 961 RISCVCPU *cpu = RISCV_CPU(cs); 962 CPURISCVState *env = &cpu->env; 963 964 switch (riscv_cpu_mxl(env)) { 965 case MXL_RV32: 966 return g_strdup("riscv:rv32"); 967 case MXL_RV64: 968 case MXL_RV128: 969 return g_strdup("riscv:rv64"); 970 default: 971 g_assert_not_reached(); 972 } 973 } 974 975 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 976 { 977 RISCVCPU *cpu = RISCV_CPU(cs); 978 979 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 980 return cpu->dyn_csr_xml; 981 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 982 return cpu->dyn_vreg_xml; 983 } 984 985 return NULL; 986 } 987 988 #ifndef CONFIG_USER_ONLY 989 #include "hw/core/sysemu-cpu-ops.h" 990 991 static const struct SysemuCPUOps riscv_sysemu_ops = { 992 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 993 .write_elf64_note = riscv_cpu_write_elf64_note, 994 .write_elf32_note = riscv_cpu_write_elf32_note, 995 .legacy_vmsd = &vmstate_riscv_cpu, 996 }; 997 #endif 998 999 #include "hw/core/tcg-cpu-ops.h" 1000 1001 static const struct TCGCPUOps riscv_tcg_ops = { 1002 .initialize = riscv_translate_init, 1003 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1004 1005 #ifndef CONFIG_USER_ONLY 1006 .tlb_fill = riscv_cpu_tlb_fill, 1007 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1008 .do_interrupt = riscv_cpu_do_interrupt, 1009 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1010 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1011 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1012 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1013 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1014 #endif /* !CONFIG_USER_ONLY */ 1015 }; 1016 1017 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1018 { 1019 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1020 CPUClass *cc = CPU_CLASS(c); 1021 DeviceClass *dc = DEVICE_CLASS(c); 1022 1023 device_class_set_parent_realize(dc, riscv_cpu_realize, 1024 &mcc->parent_realize); 1025 1026 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 1027 1028 cc->class_by_name = riscv_cpu_class_by_name; 1029 cc->has_work = riscv_cpu_has_work; 1030 cc->dump_state = riscv_cpu_dump_state; 1031 cc->set_pc = riscv_cpu_set_pc; 1032 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1033 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1034 cc->gdb_num_core_regs = 33; 1035 cc->gdb_stop_before_watchpoint = true; 1036 cc->disas_set_info = riscv_cpu_disas_set_info; 1037 #ifndef CONFIG_USER_ONLY 1038 cc->sysemu_ops = &riscv_sysemu_ops; 1039 #endif 1040 cc->gdb_arch_name = riscv_gdb_arch_name; 1041 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1042 cc->tcg_ops = &riscv_tcg_ops; 1043 1044 device_class_set_props(dc, riscv_cpu_properties); 1045 } 1046 1047 #define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop} 1048 1049 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1050 { 1051 char *old = *isa_str; 1052 char *new = *isa_str; 1053 int i; 1054 1055 /** 1056 * Here are the ordering rules of extension naming defined by RISC-V 1057 * specification : 1058 * 1. All extensions should be separated from other multi-letter extensions 1059 * by an underscore. 1060 * 2. The first letter following the 'Z' conventionally indicates the most 1061 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 1062 * If multiple 'Z' extensions are named, they should be ordered first 1063 * by category, then alphabetically within a category. 1064 * 3. Standard supervisor-level extensions (starts with 'S') should be 1065 * listed after standard unprivileged extensions. If multiple 1066 * supervisor-level extensions are listed, they should be ordered 1067 * alphabetically. 1068 * 4. Non-standard extensions (starts with 'X') must be listed after all 1069 * standard extensions. They must be separated from other multi-letter 1070 * extensions by an underscore. 1071 */ 1072 struct isa_ext_data isa_edata_arr[] = { 1073 ISA_EDATA_ENTRY(zicsr, ext_icsr), 1074 ISA_EDATA_ENTRY(zifencei, ext_ifencei), 1075 ISA_EDATA_ENTRY(zmmul, ext_zmmul), 1076 ISA_EDATA_ENTRY(zfh, ext_zfh), 1077 ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), 1078 ISA_EDATA_ENTRY(zfinx, ext_zfinx), 1079 ISA_EDATA_ENTRY(zdinx, ext_zdinx), 1080 ISA_EDATA_ENTRY(zba, ext_zba), 1081 ISA_EDATA_ENTRY(zbb, ext_zbb), 1082 ISA_EDATA_ENTRY(zbc, ext_zbc), 1083 ISA_EDATA_ENTRY(zbkb, ext_zbkb), 1084 ISA_EDATA_ENTRY(zbkc, ext_zbkc), 1085 ISA_EDATA_ENTRY(zbkx, ext_zbkx), 1086 ISA_EDATA_ENTRY(zbs, ext_zbs), 1087 ISA_EDATA_ENTRY(zk, ext_zk), 1088 ISA_EDATA_ENTRY(zkn, ext_zkn), 1089 ISA_EDATA_ENTRY(zknd, ext_zknd), 1090 ISA_EDATA_ENTRY(zkne, ext_zkne), 1091 ISA_EDATA_ENTRY(zknh, ext_zknh), 1092 ISA_EDATA_ENTRY(zkr, ext_zkr), 1093 ISA_EDATA_ENTRY(zks, ext_zks), 1094 ISA_EDATA_ENTRY(zksed, ext_zksed), 1095 ISA_EDATA_ENTRY(zksh, ext_zksh), 1096 ISA_EDATA_ENTRY(zkt, ext_zkt), 1097 ISA_EDATA_ENTRY(zve32f, ext_zve32f), 1098 ISA_EDATA_ENTRY(zve64f, ext_zve64f), 1099 ISA_EDATA_ENTRY(zhinx, ext_zhinx), 1100 ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), 1101 ISA_EDATA_ENTRY(svinval, ext_svinval), 1102 ISA_EDATA_ENTRY(svnapot, ext_svnapot), 1103 ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), 1104 }; 1105 1106 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1107 if (isa_edata_arr[i].enabled) { 1108 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1109 g_free(old); 1110 old = new; 1111 } 1112 } 1113 1114 *isa_str = new; 1115 } 1116 1117 char *riscv_isa_string(RISCVCPU *cpu) 1118 { 1119 int i; 1120 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1121 char *isa_str = g_new(char, maxlen); 1122 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1123 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1124 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1125 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1126 } 1127 } 1128 *p = '\0'; 1129 if (!cpu->cfg.short_isa_string) { 1130 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1131 } 1132 return isa_str; 1133 } 1134 1135 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1136 { 1137 ObjectClass *class_a = (ObjectClass *)a; 1138 ObjectClass *class_b = (ObjectClass *)b; 1139 const char *name_a, *name_b; 1140 1141 name_a = object_class_get_name(class_a); 1142 name_b = object_class_get_name(class_b); 1143 return strcmp(name_a, name_b); 1144 } 1145 1146 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1147 { 1148 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1149 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1150 1151 qemu_printf("%.*s\n", len, typename); 1152 } 1153 1154 void riscv_cpu_list(void) 1155 { 1156 GSList *list; 1157 1158 list = object_class_get_list(TYPE_RISCV_CPU, false); 1159 list = g_slist_sort(list, riscv_cpu_list_compare); 1160 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1161 g_slist_free(list); 1162 } 1163 1164 #define DEFINE_CPU(type_name, initfn) \ 1165 { \ 1166 .name = type_name, \ 1167 .parent = TYPE_RISCV_CPU, \ 1168 .instance_init = initfn \ 1169 } 1170 1171 static const TypeInfo riscv_cpu_type_infos[] = { 1172 { 1173 .name = TYPE_RISCV_CPU, 1174 .parent = TYPE_CPU, 1175 .instance_size = sizeof(RISCVCPU), 1176 .instance_align = __alignof__(RISCVCPU), 1177 .instance_init = riscv_cpu_init, 1178 .abstract = true, 1179 .class_size = sizeof(RISCVCPUClass), 1180 .class_init = riscv_cpu_class_init, 1181 }, 1182 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1183 #if defined(CONFIG_KVM) 1184 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1185 #endif 1186 #if defined(TARGET_RISCV32) 1187 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1188 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1189 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1190 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1191 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1192 #elif defined(TARGET_RISCV64) 1193 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1194 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1195 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1196 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1197 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1198 #endif 1199 }; 1200 1201 DEFINE_TYPES(riscv_cpu_type_infos) 1202