1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "qemu/error-report.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "fpu/softfloat-helpers.h" 36 #include "sysemu/kvm.h" 37 #include "kvm_riscv.h" 38 #include "tcg/tcg.h" 39 40 /* RISC-V CPU definitions */ 41 42 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 43 (QEMU_VERSION_MINOR << 8) | \ 44 (QEMU_VERSION_MICRO)) 45 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 46 47 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 48 49 struct isa_ext_data { 50 const char *name; 51 int min_version; 52 int ext_enable_offset; 53 }; 54 55 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ 56 {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 57 58 /* 59 * Here are the ordering rules of extension naming defined by RISC-V 60 * specification : 61 * 1. All extensions should be separated from other multi-letter extensions 62 * by an underscore. 63 * 2. The first letter following the 'Z' conventionally indicates the most 64 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 65 * If multiple 'Z' extensions are named, they should be ordered first 66 * by category, then alphabetically within a category. 67 * 3. Standard supervisor-level extensions (starts with 'S') should be 68 * listed after standard unprivileged extensions. If multiple 69 * supervisor-level extensions are listed, they should be ordered 70 * alphabetically. 71 * 4. Non-standard extensions (starts with 'X') must be listed after all 72 * standard extensions. They must be separated from other multi-letter 73 * extensions by an underscore. 74 * 75 * Single letter extensions are checked in riscv_cpu_validate_misa_priv() 76 * instead. 77 */ 78 static const struct isa_ext_data isa_edata_arr[] = { 79 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), 80 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), 81 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), 82 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), 83 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), 84 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), 85 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), 86 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), 87 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), 88 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), 89 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), 90 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), 91 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), 92 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), 93 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), 94 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), 95 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), 96 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), 97 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), 98 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), 99 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), 100 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), 101 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), 102 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), 103 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), 104 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), 105 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), 106 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), 107 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), 108 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), 109 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), 110 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), 111 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), 112 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), 113 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), 114 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), 115 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), 116 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), 117 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), 118 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), 119 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), 120 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), 121 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), 122 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), 123 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), 124 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), 125 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), 126 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), 127 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), 128 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), 129 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), 130 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), 131 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), 132 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), 133 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 134 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 135 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), 136 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), 137 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 138 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), 139 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), 140 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 141 }; 142 143 static bool isa_ext_is_enabled(RISCVCPU *cpu, 144 const struct isa_ext_data *edata) 145 { 146 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 147 148 return *ext_enabled; 149 } 150 151 static void isa_ext_update_enabled(RISCVCPU *cpu, 152 const struct isa_ext_data *edata, bool en) 153 { 154 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 155 156 *ext_enabled = en; 157 } 158 159 const char * const riscv_int_regnames[] = { 160 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 161 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 162 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 163 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 164 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 165 }; 166 167 const char * const riscv_int_regnamesh[] = { 168 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 169 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 170 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 171 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 172 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 173 "x30h/t5h", "x31h/t6h" 174 }; 175 176 const char * const riscv_fpr_regnames[] = { 177 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 178 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 179 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 180 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 181 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 182 "f30/ft10", "f31/ft11" 183 }; 184 185 static const char * const riscv_excp_names[] = { 186 "misaligned_fetch", 187 "fault_fetch", 188 "illegal_instruction", 189 "breakpoint", 190 "misaligned_load", 191 "fault_load", 192 "misaligned_store", 193 "fault_store", 194 "user_ecall", 195 "supervisor_ecall", 196 "hypervisor_ecall", 197 "machine_ecall", 198 "exec_page_fault", 199 "load_page_fault", 200 "reserved", 201 "store_page_fault", 202 "reserved", 203 "reserved", 204 "reserved", 205 "reserved", 206 "guest_exec_page_fault", 207 "guest_load_page_fault", 208 "reserved", 209 "guest_store_page_fault", 210 }; 211 212 static const char * const riscv_intr_names[] = { 213 "u_software", 214 "s_software", 215 "vs_software", 216 "m_software", 217 "u_timer", 218 "s_timer", 219 "vs_timer", 220 "m_timer", 221 "u_external", 222 "s_external", 223 "vs_external", 224 "m_external", 225 "reserved", 226 "reserved", 227 "reserved", 228 "reserved" 229 }; 230 231 static void register_cpu_props(Object *obj); 232 233 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 234 { 235 if (async) { 236 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 237 riscv_intr_names[cause] : "(unknown)"; 238 } else { 239 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 240 riscv_excp_names[cause] : "(unknown)"; 241 } 242 } 243 244 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 245 { 246 env->misa_mxl_max = env->misa_mxl = mxl; 247 env->misa_ext_mask = env->misa_ext = ext; 248 } 249 250 static void set_priv_version(CPURISCVState *env, int priv_ver) 251 { 252 env->priv_ver = priv_ver; 253 } 254 255 static void set_vext_version(CPURISCVState *env, int vext_ver) 256 { 257 env->vext_ver = vext_ver; 258 } 259 260 #ifndef CONFIG_USER_ONLY 261 static uint8_t satp_mode_from_str(const char *satp_mode_str) 262 { 263 if (!strncmp(satp_mode_str, "mbare", 5)) { 264 return VM_1_10_MBARE; 265 } 266 267 if (!strncmp(satp_mode_str, "sv32", 4)) { 268 return VM_1_10_SV32; 269 } 270 271 if (!strncmp(satp_mode_str, "sv39", 4)) { 272 return VM_1_10_SV39; 273 } 274 275 if (!strncmp(satp_mode_str, "sv48", 4)) { 276 return VM_1_10_SV48; 277 } 278 279 if (!strncmp(satp_mode_str, "sv57", 4)) { 280 return VM_1_10_SV57; 281 } 282 283 if (!strncmp(satp_mode_str, "sv64", 4)) { 284 return VM_1_10_SV64; 285 } 286 287 g_assert_not_reached(); 288 } 289 290 uint8_t satp_mode_max_from_map(uint32_t map) 291 { 292 /* map here has at least one bit set, so no problem with clz */ 293 return 31 - __builtin_clz(map); 294 } 295 296 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) 297 { 298 if (is_32_bit) { 299 switch (satp_mode) { 300 case VM_1_10_SV32: 301 return "sv32"; 302 case VM_1_10_MBARE: 303 return "none"; 304 } 305 } else { 306 switch (satp_mode) { 307 case VM_1_10_SV64: 308 return "sv64"; 309 case VM_1_10_SV57: 310 return "sv57"; 311 case VM_1_10_SV48: 312 return "sv48"; 313 case VM_1_10_SV39: 314 return "sv39"; 315 case VM_1_10_MBARE: 316 return "none"; 317 } 318 } 319 320 g_assert_not_reached(); 321 } 322 323 static void set_satp_mode_max_supported(RISCVCPU *cpu, 324 uint8_t satp_mode) 325 { 326 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 327 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; 328 329 for (int i = 0; i <= satp_mode; ++i) { 330 if (valid_vm[i]) { 331 cpu->cfg.satp_mode.supported |= (1 << i); 332 } 333 } 334 } 335 336 /* Set the satp mode to the max supported */ 337 static void set_satp_mode_default_map(RISCVCPU *cpu) 338 { 339 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; 340 } 341 #endif 342 343 static void riscv_any_cpu_init(Object *obj) 344 { 345 CPURISCVState *env = &RISCV_CPU(obj)->env; 346 #if defined(TARGET_RISCV32) 347 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 348 #elif defined(TARGET_RISCV64) 349 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 350 #endif 351 352 #ifndef CONFIG_USER_ONLY 353 set_satp_mode_max_supported(RISCV_CPU(obj), 354 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? 355 VM_1_10_SV32 : VM_1_10_SV57); 356 #endif 357 358 set_priv_version(env, PRIV_VERSION_1_12_0); 359 register_cpu_props(obj); 360 } 361 362 #if defined(TARGET_RISCV64) 363 static void rv64_base_cpu_init(Object *obj) 364 { 365 CPURISCVState *env = &RISCV_CPU(obj)->env; 366 /* We set this in the realise function */ 367 set_misa(env, MXL_RV64, 0); 368 register_cpu_props(obj); 369 /* Set latest version of privileged specification */ 370 set_priv_version(env, PRIV_VERSION_1_12_0); 371 #ifndef CONFIG_USER_ONLY 372 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 373 #endif 374 } 375 376 static void rv64_sifive_u_cpu_init(Object *obj) 377 { 378 CPURISCVState *env = &RISCV_CPU(obj)->env; 379 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 380 register_cpu_props(obj); 381 set_priv_version(env, PRIV_VERSION_1_10_0); 382 #ifndef CONFIG_USER_ONLY 383 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); 384 #endif 385 } 386 387 static void rv64_sifive_e_cpu_init(Object *obj) 388 { 389 CPURISCVState *env = &RISCV_CPU(obj)->env; 390 RISCVCPU *cpu = RISCV_CPU(obj); 391 392 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 393 register_cpu_props(obj); 394 set_priv_version(env, PRIV_VERSION_1_10_0); 395 cpu->cfg.mmu = false; 396 #ifndef CONFIG_USER_ONLY 397 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 398 #endif 399 } 400 401 static void rv64_thead_c906_cpu_init(Object *obj) 402 { 403 CPURISCVState *env = &RISCV_CPU(obj)->env; 404 RISCVCPU *cpu = RISCV_CPU(obj); 405 406 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 407 set_priv_version(env, PRIV_VERSION_1_11_0); 408 409 cpu->cfg.ext_g = true; 410 cpu->cfg.ext_u = true; 411 cpu->cfg.ext_s = true; 412 cpu->cfg.ext_icsr = true; 413 cpu->cfg.ext_zfh = true; 414 cpu->cfg.mmu = true; 415 cpu->cfg.ext_xtheadba = true; 416 cpu->cfg.ext_xtheadbb = true; 417 cpu->cfg.ext_xtheadbs = true; 418 cpu->cfg.ext_xtheadcmo = true; 419 cpu->cfg.ext_xtheadcondmov = true; 420 cpu->cfg.ext_xtheadfmemidx = true; 421 cpu->cfg.ext_xtheadmac = true; 422 cpu->cfg.ext_xtheadmemidx = true; 423 cpu->cfg.ext_xtheadmempair = true; 424 cpu->cfg.ext_xtheadsync = true; 425 426 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 427 #ifndef CONFIG_USER_ONLY 428 set_satp_mode_max_supported(cpu, VM_1_10_SV39); 429 #endif 430 } 431 432 static void rv128_base_cpu_init(Object *obj) 433 { 434 if (qemu_tcg_mttcg_enabled()) { 435 /* Missing 128-bit aligned atomics */ 436 error_report("128-bit RISC-V currently does not work with Multi " 437 "Threaded TCG. Please use: -accel tcg,thread=single"); 438 exit(EXIT_FAILURE); 439 } 440 CPURISCVState *env = &RISCV_CPU(obj)->env; 441 /* We set this in the realise function */ 442 set_misa(env, MXL_RV128, 0); 443 register_cpu_props(obj); 444 /* Set latest version of privileged specification */ 445 set_priv_version(env, PRIV_VERSION_1_12_0); 446 #ifndef CONFIG_USER_ONLY 447 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 448 #endif 449 } 450 #else 451 static void rv32_base_cpu_init(Object *obj) 452 { 453 CPURISCVState *env = &RISCV_CPU(obj)->env; 454 /* We set this in the realise function */ 455 set_misa(env, MXL_RV32, 0); 456 register_cpu_props(obj); 457 /* Set latest version of privileged specification */ 458 set_priv_version(env, PRIV_VERSION_1_12_0); 459 #ifndef CONFIG_USER_ONLY 460 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 461 #endif 462 } 463 464 static void rv32_sifive_u_cpu_init(Object *obj) 465 { 466 CPURISCVState *env = &RISCV_CPU(obj)->env; 467 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 468 register_cpu_props(obj); 469 set_priv_version(env, PRIV_VERSION_1_10_0); 470 #ifndef CONFIG_USER_ONLY 471 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 472 #endif 473 } 474 475 static void rv32_sifive_e_cpu_init(Object *obj) 476 { 477 CPURISCVState *env = &RISCV_CPU(obj)->env; 478 RISCVCPU *cpu = RISCV_CPU(obj); 479 480 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 481 register_cpu_props(obj); 482 set_priv_version(env, PRIV_VERSION_1_10_0); 483 cpu->cfg.mmu = false; 484 #ifndef CONFIG_USER_ONLY 485 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 486 #endif 487 } 488 489 static void rv32_ibex_cpu_init(Object *obj) 490 { 491 CPURISCVState *env = &RISCV_CPU(obj)->env; 492 RISCVCPU *cpu = RISCV_CPU(obj); 493 494 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 495 register_cpu_props(obj); 496 set_priv_version(env, PRIV_VERSION_1_11_0); 497 cpu->cfg.mmu = false; 498 #ifndef CONFIG_USER_ONLY 499 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 500 #endif 501 cpu->cfg.epmp = true; 502 } 503 504 static void rv32_imafcu_nommu_cpu_init(Object *obj) 505 { 506 CPURISCVState *env = &RISCV_CPU(obj)->env; 507 RISCVCPU *cpu = RISCV_CPU(obj); 508 509 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 510 register_cpu_props(obj); 511 set_priv_version(env, PRIV_VERSION_1_10_0); 512 cpu->cfg.mmu = false; 513 #ifndef CONFIG_USER_ONLY 514 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 515 #endif 516 } 517 #endif 518 519 #if defined(CONFIG_KVM) 520 static void riscv_host_cpu_init(Object *obj) 521 { 522 CPURISCVState *env = &RISCV_CPU(obj)->env; 523 #if defined(TARGET_RISCV32) 524 set_misa(env, MXL_RV32, 0); 525 #elif defined(TARGET_RISCV64) 526 set_misa(env, MXL_RV64, 0); 527 #endif 528 register_cpu_props(obj); 529 } 530 #endif 531 532 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 533 { 534 ObjectClass *oc; 535 char *typename; 536 char **cpuname; 537 538 cpuname = g_strsplit(cpu_model, ",", 1); 539 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 540 oc = object_class_by_name(typename); 541 g_strfreev(cpuname); 542 g_free(typename); 543 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 544 object_class_is_abstract(oc)) { 545 return NULL; 546 } 547 return oc; 548 } 549 550 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 551 { 552 RISCVCPU *cpu = RISCV_CPU(cs); 553 CPURISCVState *env = &cpu->env; 554 int i; 555 556 #if !defined(CONFIG_USER_ONLY) 557 if (riscv_has_ext(env, RVH)) { 558 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); 559 } 560 #endif 561 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 562 #ifndef CONFIG_USER_ONLY 563 { 564 static const int dump_csrs[] = { 565 CSR_MHARTID, 566 CSR_MSTATUS, 567 CSR_MSTATUSH, 568 /* 569 * CSR_SSTATUS is intentionally omitted here as its value 570 * can be figured out by looking at CSR_MSTATUS 571 */ 572 CSR_HSTATUS, 573 CSR_VSSTATUS, 574 CSR_MIP, 575 CSR_MIE, 576 CSR_MIDELEG, 577 CSR_HIDELEG, 578 CSR_MEDELEG, 579 CSR_HEDELEG, 580 CSR_MTVEC, 581 CSR_STVEC, 582 CSR_VSTVEC, 583 CSR_MEPC, 584 CSR_SEPC, 585 CSR_VSEPC, 586 CSR_MCAUSE, 587 CSR_SCAUSE, 588 CSR_VSCAUSE, 589 CSR_MTVAL, 590 CSR_STVAL, 591 CSR_HTVAL, 592 CSR_MTVAL2, 593 CSR_MSCRATCH, 594 CSR_SSCRATCH, 595 CSR_SATP, 596 CSR_MMTE, 597 CSR_UPMBASE, 598 CSR_UPMMASK, 599 CSR_SPMBASE, 600 CSR_SPMMASK, 601 CSR_MPMBASE, 602 CSR_MPMMASK, 603 }; 604 605 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 606 int csrno = dump_csrs[i]; 607 target_ulong val = 0; 608 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 609 610 /* 611 * Rely on the smode, hmode, etc, predicates within csr.c 612 * to do the filtering of the registers that are present. 613 */ 614 if (res == RISCV_EXCP_NONE) { 615 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 616 csr_ops[csrno].name, val); 617 } 618 } 619 } 620 #endif 621 622 for (i = 0; i < 32; i++) { 623 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 624 riscv_int_regnames[i], env->gpr[i]); 625 if ((i & 3) == 3) { 626 qemu_fprintf(f, "\n"); 627 } 628 } 629 if (flags & CPU_DUMP_FPU) { 630 for (i = 0; i < 32; i++) { 631 qemu_fprintf(f, " %-8s %016" PRIx64, 632 riscv_fpr_regnames[i], env->fpr[i]); 633 if ((i & 3) == 3) { 634 qemu_fprintf(f, "\n"); 635 } 636 } 637 } 638 } 639 640 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 641 { 642 RISCVCPU *cpu = RISCV_CPU(cs); 643 CPURISCVState *env = &cpu->env; 644 645 if (env->xl == MXL_RV32) { 646 env->pc = (int32_t)value; 647 } else { 648 env->pc = value; 649 } 650 } 651 652 static vaddr riscv_cpu_get_pc(CPUState *cs) 653 { 654 RISCVCPU *cpu = RISCV_CPU(cs); 655 CPURISCVState *env = &cpu->env; 656 657 /* Match cpu_get_tb_cpu_state. */ 658 if (env->xl == MXL_RV32) { 659 return env->pc & UINT32_MAX; 660 } 661 return env->pc; 662 } 663 664 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 665 const TranslationBlock *tb) 666 { 667 RISCVCPU *cpu = RISCV_CPU(cs); 668 CPURISCVState *env = &cpu->env; 669 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 670 671 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 672 673 if (xl == MXL_RV32) { 674 env->pc = (int32_t) tb->pc; 675 } else { 676 env->pc = tb->pc; 677 } 678 } 679 680 static bool riscv_cpu_has_work(CPUState *cs) 681 { 682 #ifndef CONFIG_USER_ONLY 683 RISCVCPU *cpu = RISCV_CPU(cs); 684 CPURISCVState *env = &cpu->env; 685 /* 686 * Definition of the WFI instruction requires it to ignore the privilege 687 * mode and delegation registers, but respect individual enables 688 */ 689 return riscv_cpu_all_pending(env) != 0; 690 #else 691 return true; 692 #endif 693 } 694 695 static void riscv_restore_state_to_opc(CPUState *cs, 696 const TranslationBlock *tb, 697 const uint64_t *data) 698 { 699 RISCVCPU *cpu = RISCV_CPU(cs); 700 CPURISCVState *env = &cpu->env; 701 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 702 703 if (xl == MXL_RV32) { 704 env->pc = (int32_t)data[0]; 705 } else { 706 env->pc = data[0]; 707 } 708 env->bins = data[1]; 709 } 710 711 static void riscv_cpu_reset_hold(Object *obj) 712 { 713 #ifndef CONFIG_USER_ONLY 714 uint8_t iprio; 715 int i, irq, rdzero; 716 #endif 717 CPUState *cs = CPU(obj); 718 RISCVCPU *cpu = RISCV_CPU(cs); 719 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 720 CPURISCVState *env = &cpu->env; 721 722 if (mcc->parent_phases.hold) { 723 mcc->parent_phases.hold(obj); 724 } 725 #ifndef CONFIG_USER_ONLY 726 env->misa_mxl = env->misa_mxl_max; 727 env->priv = PRV_M; 728 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 729 if (env->misa_mxl > MXL_RV32) { 730 /* 731 * The reset status of SXL/UXL is undefined, but mstatus is WARL 732 * and we must ensure that the value after init is valid for read. 733 */ 734 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 735 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 736 if (riscv_has_ext(env, RVH)) { 737 env->vsstatus = set_field(env->vsstatus, 738 MSTATUS64_SXL, env->misa_mxl); 739 env->vsstatus = set_field(env->vsstatus, 740 MSTATUS64_UXL, env->misa_mxl); 741 env->mstatus_hs = set_field(env->mstatus_hs, 742 MSTATUS64_SXL, env->misa_mxl); 743 env->mstatus_hs = set_field(env->mstatus_hs, 744 MSTATUS64_UXL, env->misa_mxl); 745 } 746 } 747 env->mcause = 0; 748 env->miclaim = MIP_SGEIP; 749 env->pc = env->resetvec; 750 env->bins = 0; 751 env->two_stage_lookup = false; 752 753 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | 754 (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); 755 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | 756 (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); 757 758 /* Initialized default priorities of local interrupts. */ 759 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 760 iprio = riscv_cpu_default_priority(i); 761 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 762 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 763 env->hviprio[i] = 0; 764 } 765 i = 0; 766 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 767 if (!rdzero) { 768 env->hviprio[irq] = env->miprio[irq]; 769 } 770 i++; 771 } 772 /* mmte is supposed to have pm.current hardwired to 1 */ 773 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 774 #endif 775 env->xl = riscv_cpu_mxl(env); 776 riscv_cpu_update_mask(env); 777 cs->exception_index = RISCV_EXCP_NONE; 778 env->load_res = -1; 779 set_default_nan_mode(1, &env->fp_status); 780 781 #ifndef CONFIG_USER_ONLY 782 if (cpu->cfg.debug) { 783 riscv_trigger_init(env); 784 } 785 786 if (kvm_enabled()) { 787 kvm_riscv_reset_vcpu(cpu); 788 } 789 #endif 790 } 791 792 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 793 { 794 RISCVCPU *cpu = RISCV_CPU(s); 795 796 switch (riscv_cpu_mxl(&cpu->env)) { 797 case MXL_RV32: 798 info->print_insn = print_insn_riscv32; 799 break; 800 case MXL_RV64: 801 info->print_insn = print_insn_riscv64; 802 break; 803 case MXL_RV128: 804 info->print_insn = print_insn_riscv128; 805 break; 806 default: 807 g_assert_not_reached(); 808 } 809 } 810 811 /* 812 * Check consistency between chosen extensions while setting 813 * cpu->cfg accordingly. 814 */ 815 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 816 { 817 CPURISCVState *env = &cpu->env; 818 819 /* Do some ISA extension error checking */ 820 if (cpu->cfg.ext_g && !(riscv_has_ext(env, RVI) && cpu->cfg.ext_m && 821 riscv_has_ext(env, RVA) && 822 riscv_has_ext(env, RVF) && 823 riscv_has_ext(env, RVD) && 824 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 825 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 826 cpu->cfg.ext_m = true; 827 cpu->cfg.ext_icsr = true; 828 cpu->cfg.ext_ifencei = true; 829 830 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; 831 env->misa_ext_mask = env->misa_ext; 832 } 833 834 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 835 error_setg(errp, 836 "I and E extensions are incompatible"); 837 return; 838 } 839 840 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 841 error_setg(errp, 842 "Either I or E extension must be set"); 843 return; 844 } 845 846 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 847 error_setg(errp, 848 "Setting S extension without U extension is illegal"); 849 return; 850 } 851 852 if (cpu->cfg.ext_h && !riscv_has_ext(env, RVI)) { 853 error_setg(errp, 854 "H depends on an I base integer ISA with 32 x registers"); 855 return; 856 } 857 858 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 859 error_setg(errp, "H extension implicitly requires S-mode"); 860 return; 861 } 862 863 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { 864 error_setg(errp, "F extension requires Zicsr"); 865 return; 866 } 867 868 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 869 error_setg(errp, "Zawrs extension requires A extension"); 870 return; 871 } 872 873 if (cpu->cfg.ext_zfh) { 874 cpu->cfg.ext_zfhmin = true; 875 } 876 877 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 878 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 879 return; 880 } 881 882 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 883 error_setg(errp, "D extension requires F extension"); 884 return; 885 } 886 887 /* The V vector extension depends on the Zve64d extension */ 888 if (cpu->cfg.ext_v) { 889 cpu->cfg.ext_zve64d = true; 890 } 891 892 /* The Zve64d extension depends on the Zve64f extension */ 893 if (cpu->cfg.ext_zve64d) { 894 cpu->cfg.ext_zve64f = true; 895 } 896 897 /* The Zve64f extension depends on the Zve32f extension */ 898 if (cpu->cfg.ext_zve64f) { 899 cpu->cfg.ext_zve32f = true; 900 } 901 902 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 903 error_setg(errp, "Zve64d/V extensions require D extension"); 904 return; 905 } 906 907 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 908 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 909 return; 910 } 911 912 if (cpu->cfg.ext_zvfh) { 913 cpu->cfg.ext_zvfhmin = true; 914 } 915 916 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 917 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 918 return; 919 } 920 921 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 922 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 923 return; 924 } 925 926 /* Set the ISA extensions, checks should have happened above */ 927 if (cpu->cfg.ext_zhinx) { 928 cpu->cfg.ext_zhinxmin = true; 929 } 930 931 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { 932 cpu->cfg.ext_zfinx = true; 933 } 934 935 if (cpu->cfg.ext_zfinx) { 936 if (!cpu->cfg.ext_icsr) { 937 error_setg(errp, "Zfinx extension requires Zicsr"); 938 return; 939 } 940 if (riscv_has_ext(env, RVF)) { 941 error_setg(errp, 942 "Zfinx cannot be supported together with F extension"); 943 return; 944 } 945 } 946 947 if (cpu->cfg.ext_zce) { 948 cpu->cfg.ext_zca = true; 949 cpu->cfg.ext_zcb = true; 950 cpu->cfg.ext_zcmp = true; 951 cpu->cfg.ext_zcmt = true; 952 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 953 cpu->cfg.ext_zcf = true; 954 } 955 } 956 957 if (riscv_has_ext(env, RVC)) { 958 cpu->cfg.ext_zca = true; 959 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 960 cpu->cfg.ext_zcf = true; 961 } 962 if (riscv_has_ext(env, RVD)) { 963 cpu->cfg.ext_zcd = true; 964 } 965 } 966 967 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 968 error_setg(errp, "Zcf extension is only relevant to RV32"); 969 return; 970 } 971 972 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 973 error_setg(errp, "Zcf extension requires F extension"); 974 return; 975 } 976 977 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 978 error_setg(errp, "Zcd extension requires D extension"); 979 return; 980 } 981 982 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 983 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 984 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 985 "extension"); 986 return; 987 } 988 989 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 990 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 991 "Zcd extension"); 992 return; 993 } 994 995 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { 996 error_setg(errp, "Zcmt extension requires Zicsr extension"); 997 return; 998 } 999 1000 if (cpu->cfg.ext_zk) { 1001 cpu->cfg.ext_zkn = true; 1002 cpu->cfg.ext_zkr = true; 1003 cpu->cfg.ext_zkt = true; 1004 } 1005 1006 if (cpu->cfg.ext_zkn) { 1007 cpu->cfg.ext_zbkb = true; 1008 cpu->cfg.ext_zbkc = true; 1009 cpu->cfg.ext_zbkx = true; 1010 cpu->cfg.ext_zkne = true; 1011 cpu->cfg.ext_zknd = true; 1012 cpu->cfg.ext_zknh = true; 1013 } 1014 1015 if (cpu->cfg.ext_zks) { 1016 cpu->cfg.ext_zbkb = true; 1017 cpu->cfg.ext_zbkc = true; 1018 cpu->cfg.ext_zbkx = true; 1019 cpu->cfg.ext_zksed = true; 1020 cpu->cfg.ext_zksh = true; 1021 } 1022 1023 if (cpu->cfg.ext_v) { 1024 int vext_version = VEXT_VERSION_1_00_0; 1025 if (!is_power_of_2(cpu->cfg.vlen)) { 1026 error_setg(errp, 1027 "Vector extension VLEN must be power of 2"); 1028 return; 1029 } 1030 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 1031 error_setg(errp, 1032 "Vector extension implementation only supports VLEN " 1033 "in the range [128, %d]", RV_VLEN_MAX); 1034 return; 1035 } 1036 if (!is_power_of_2(cpu->cfg.elen)) { 1037 error_setg(errp, 1038 "Vector extension ELEN must be power of 2"); 1039 return; 1040 } 1041 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 1042 error_setg(errp, 1043 "Vector extension implementation only supports ELEN " 1044 "in the range [8, 64]"); 1045 return; 1046 } 1047 if (cpu->cfg.vext_spec) { 1048 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 1049 vext_version = VEXT_VERSION_1_00_0; 1050 } else { 1051 error_setg(errp, 1052 "Unsupported vector spec version '%s'", 1053 cpu->cfg.vext_spec); 1054 return; 1055 } 1056 } else { 1057 qemu_log("vector version is not specified, " 1058 "use the default value v1.0\n"); 1059 } 1060 set_vext_version(env, vext_version); 1061 } 1062 } 1063 1064 #ifndef CONFIG_USER_ONLY 1065 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) 1066 { 1067 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 1068 uint8_t satp_mode_map_max; 1069 uint8_t satp_mode_supported_max = 1070 satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 1071 1072 if (cpu->cfg.satp_mode.map == 0) { 1073 if (cpu->cfg.satp_mode.init == 0) { 1074 /* If unset by the user, we fallback to the default satp mode. */ 1075 set_satp_mode_default_map(cpu); 1076 } else { 1077 /* 1078 * Find the lowest level that was disabled and then enable the 1079 * first valid level below which can be found in 1080 * valid_vm_1_10_32/64. 1081 */ 1082 for (int i = 1; i < 16; ++i) { 1083 if ((cpu->cfg.satp_mode.init & (1 << i)) && 1084 (cpu->cfg.satp_mode.supported & (1 << i))) { 1085 for (int j = i - 1; j >= 0; --j) { 1086 if (cpu->cfg.satp_mode.supported & (1 << j)) { 1087 cpu->cfg.satp_mode.map |= (1 << j); 1088 break; 1089 } 1090 } 1091 break; 1092 } 1093 } 1094 } 1095 } 1096 1097 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 1098 1099 /* Make sure the user asked for a supported configuration (HW and qemu) */ 1100 if (satp_mode_map_max > satp_mode_supported_max) { 1101 error_setg(errp, "satp_mode %s is higher than hw max capability %s", 1102 satp_mode_str(satp_mode_map_max, rv32), 1103 satp_mode_str(satp_mode_supported_max, rv32)); 1104 return; 1105 } 1106 1107 /* 1108 * Make sure the user did not ask for an invalid configuration as per 1109 * the specification. 1110 */ 1111 if (!rv32) { 1112 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1113 if (!(cpu->cfg.satp_mode.map & (1 << i)) && 1114 (cpu->cfg.satp_mode.init & (1 << i)) && 1115 (cpu->cfg.satp_mode.supported & (1 << i))) { 1116 error_setg(errp, "cannot disable %s satp mode if %s " 1117 "is enabled", satp_mode_str(i, false), 1118 satp_mode_str(satp_mode_map_max, false)); 1119 return; 1120 } 1121 } 1122 } 1123 1124 /* Finally expand the map so that all valid modes are set */ 1125 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1126 if (cpu->cfg.satp_mode.supported & (1 << i)) { 1127 cpu->cfg.satp_mode.map |= (1 << i); 1128 } 1129 } 1130 } 1131 #endif 1132 1133 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1134 { 1135 #ifndef CONFIG_USER_ONLY 1136 Error *local_err = NULL; 1137 1138 riscv_cpu_satp_mode_finalize(cpu, &local_err); 1139 if (local_err != NULL) { 1140 error_propagate(errp, local_err); 1141 return; 1142 } 1143 #endif 1144 } 1145 1146 static void riscv_cpu_sync_misa_cfg(CPURISCVState *env) 1147 { 1148 uint32_t ext = 0; 1149 1150 if (riscv_has_ext(env, RVI)) { 1151 ext |= RVI; 1152 } 1153 if (riscv_has_ext(env, RVE)) { 1154 ext |= RVE; 1155 } 1156 if (riscv_cpu_cfg(env)->ext_m) { 1157 ext |= RVM; 1158 } 1159 if (riscv_has_ext(env, RVA)) { 1160 ext |= RVA; 1161 } 1162 if (riscv_has_ext(env, RVF)) { 1163 ext |= RVF; 1164 } 1165 if (riscv_has_ext(env, RVD)) { 1166 ext |= RVD; 1167 } 1168 if (riscv_has_ext(env, RVC)) { 1169 ext |= RVC; 1170 } 1171 if (riscv_cpu_cfg(env)->ext_s) { 1172 ext |= RVS; 1173 } 1174 if (riscv_cpu_cfg(env)->ext_u) { 1175 ext |= RVU; 1176 } 1177 if (riscv_cpu_cfg(env)->ext_h) { 1178 ext |= RVH; 1179 } 1180 if (riscv_cpu_cfg(env)->ext_v) { 1181 ext |= RVV; 1182 } 1183 if (riscv_cpu_cfg(env)->ext_j) { 1184 ext |= RVJ; 1185 } 1186 1187 env->misa_ext = env->misa_ext_mask = ext; 1188 } 1189 1190 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 1191 { 1192 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 1193 error_setg(errp, "H extension requires priv spec 1.12.0"); 1194 return; 1195 } 1196 } 1197 1198 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 1199 { 1200 CPUState *cs = CPU(dev); 1201 RISCVCPU *cpu = RISCV_CPU(dev); 1202 CPURISCVState *env = &cpu->env; 1203 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 1204 CPUClass *cc = CPU_CLASS(mcc); 1205 int i, priv_version = -1; 1206 Error *local_err = NULL; 1207 1208 cpu_exec_realizefn(cs, &local_err); 1209 if (local_err != NULL) { 1210 error_propagate(errp, local_err); 1211 return; 1212 } 1213 1214 if (cpu->cfg.priv_spec) { 1215 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 1216 priv_version = PRIV_VERSION_1_12_0; 1217 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 1218 priv_version = PRIV_VERSION_1_11_0; 1219 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 1220 priv_version = PRIV_VERSION_1_10_0; 1221 } else { 1222 error_setg(errp, 1223 "Unsupported privilege spec version '%s'", 1224 cpu->cfg.priv_spec); 1225 return; 1226 } 1227 } 1228 1229 if (priv_version >= PRIV_VERSION_1_10_0) { 1230 set_priv_version(env, priv_version); 1231 } 1232 1233 /* 1234 * We can't be sure of whether we set defaults during cpu_init() 1235 * or whether the user enabled/disabled some bits via cpu->cfg 1236 * flags. Sync env->misa_ext with cpu->cfg now to allow us to 1237 * use just env->misa_ext later. 1238 */ 1239 riscv_cpu_sync_misa_cfg(env); 1240 1241 riscv_cpu_validate_misa_priv(env, &local_err); 1242 if (local_err != NULL) { 1243 error_propagate(errp, local_err); 1244 return; 1245 } 1246 1247 /* Force disable extensions if priv spec version does not match */ 1248 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1249 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 1250 (env->priv_ver < isa_edata_arr[i].min_version)) { 1251 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 1252 #ifndef CONFIG_USER_ONLY 1253 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 1254 " because privilege spec version does not match", 1255 isa_edata_arr[i].name, env->mhartid); 1256 #else 1257 warn_report("disabling %s extension because " 1258 "privilege spec version does not match", 1259 isa_edata_arr[i].name); 1260 #endif 1261 } 1262 } 1263 1264 if (cpu->cfg.epmp && !cpu->cfg.pmp) { 1265 /* 1266 * Enhanced PMP should only be available 1267 * on harts with PMP support 1268 */ 1269 error_setg(errp, "Invalid configuration: EPMP requires PMP support"); 1270 return; 1271 } 1272 1273 1274 #ifndef CONFIG_USER_ONLY 1275 if (cpu->cfg.ext_sstc) { 1276 riscv_timer_init(cpu); 1277 } 1278 #endif /* CONFIG_USER_ONLY */ 1279 1280 /* Validate that MISA_MXL is set properly. */ 1281 switch (env->misa_mxl_max) { 1282 #ifdef TARGET_RISCV64 1283 case MXL_RV64: 1284 case MXL_RV128: 1285 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 1286 break; 1287 #endif 1288 case MXL_RV32: 1289 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 1290 break; 1291 default: 1292 g_assert_not_reached(); 1293 } 1294 assert(env->misa_mxl_max == env->misa_mxl); 1295 1296 riscv_cpu_validate_set_extensions(cpu, &local_err); 1297 if (local_err != NULL) { 1298 error_propagate(errp, local_err); 1299 return; 1300 } 1301 1302 #ifndef CONFIG_USER_ONLY 1303 if (cpu->cfg.pmu_num) { 1304 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 1305 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1306 riscv_pmu_timer_cb, cpu); 1307 } 1308 } 1309 #endif 1310 1311 riscv_cpu_finalize_features(cpu, &local_err); 1312 if (local_err != NULL) { 1313 error_propagate(errp, local_err); 1314 return; 1315 } 1316 1317 riscv_cpu_register_gdb_regs_for_features(cs); 1318 1319 qemu_init_vcpu(cs); 1320 cpu_reset(cs); 1321 1322 mcc->parent_realize(dev, errp); 1323 } 1324 1325 #ifndef CONFIG_USER_ONLY 1326 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, 1327 void *opaque, Error **errp) 1328 { 1329 RISCVSATPMap *satp_map = opaque; 1330 uint8_t satp = satp_mode_from_str(name); 1331 bool value; 1332 1333 value = satp_map->map & (1 << satp); 1334 1335 visit_type_bool(v, name, &value, errp); 1336 } 1337 1338 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, 1339 void *opaque, Error **errp) 1340 { 1341 RISCVSATPMap *satp_map = opaque; 1342 uint8_t satp = satp_mode_from_str(name); 1343 bool value; 1344 1345 if (!visit_type_bool(v, name, &value, errp)) { 1346 return; 1347 } 1348 1349 satp_map->map = deposit32(satp_map->map, satp, 1, value); 1350 satp_map->init |= 1 << satp; 1351 } 1352 1353 static void riscv_add_satp_mode_properties(Object *obj) 1354 { 1355 RISCVCPU *cpu = RISCV_CPU(obj); 1356 1357 if (cpu->env.misa_mxl == MXL_RV32) { 1358 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, 1359 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1360 } else { 1361 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, 1362 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1363 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, 1364 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1365 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, 1366 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1367 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, 1368 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1369 } 1370 } 1371 1372 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1373 { 1374 RISCVCPU *cpu = RISCV_CPU(opaque); 1375 CPURISCVState *env = &cpu->env; 1376 1377 if (irq < IRQ_LOCAL_MAX) { 1378 switch (irq) { 1379 case IRQ_U_SOFT: 1380 case IRQ_S_SOFT: 1381 case IRQ_VS_SOFT: 1382 case IRQ_M_SOFT: 1383 case IRQ_U_TIMER: 1384 case IRQ_S_TIMER: 1385 case IRQ_VS_TIMER: 1386 case IRQ_M_TIMER: 1387 case IRQ_U_EXT: 1388 case IRQ_VS_EXT: 1389 case IRQ_M_EXT: 1390 if (kvm_enabled()) { 1391 kvm_riscv_set_irq(cpu, irq, level); 1392 } else { 1393 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); 1394 } 1395 break; 1396 case IRQ_S_EXT: 1397 if (kvm_enabled()) { 1398 kvm_riscv_set_irq(cpu, irq, level); 1399 } else { 1400 env->external_seip = level; 1401 riscv_cpu_update_mip(env, 1 << irq, 1402 BOOL_TO_MASK(level | env->software_seip)); 1403 } 1404 break; 1405 default: 1406 g_assert_not_reached(); 1407 } 1408 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1409 /* Require H-extension for handling guest local interrupts */ 1410 if (!riscv_has_ext(env, RVH)) { 1411 g_assert_not_reached(); 1412 } 1413 1414 /* Compute bit position in HGEIP CSR */ 1415 irq = irq - IRQ_LOCAL_MAX + 1; 1416 if (env->geilen < irq) { 1417 g_assert_not_reached(); 1418 } 1419 1420 /* Update HGEIP CSR */ 1421 env->hgeip &= ~((target_ulong)1 << irq); 1422 if (level) { 1423 env->hgeip |= (target_ulong)1 << irq; 1424 } 1425 1426 /* Update mip.SGEIP bit */ 1427 riscv_cpu_update_mip(env, MIP_SGEIP, 1428 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1429 } else { 1430 g_assert_not_reached(); 1431 } 1432 } 1433 #endif /* CONFIG_USER_ONLY */ 1434 1435 static void riscv_cpu_init(Object *obj) 1436 { 1437 RISCVCPU *cpu = RISCV_CPU(obj); 1438 1439 cpu->cfg.ext_ifencei = true; 1440 cpu->cfg.ext_icsr = true; 1441 cpu->cfg.mmu = true; 1442 cpu->cfg.pmp = true; 1443 1444 cpu_set_cpustate_pointers(cpu); 1445 1446 #ifndef CONFIG_USER_ONLY 1447 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1448 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1449 #endif /* CONFIG_USER_ONLY */ 1450 } 1451 1452 typedef struct RISCVCPUMisaExtConfig { 1453 const char *name; 1454 const char *description; 1455 target_ulong misa_bit; 1456 bool enabled; 1457 } RISCVCPUMisaExtConfig; 1458 1459 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1460 void *opaque, Error **errp) 1461 { 1462 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1463 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1464 RISCVCPU *cpu = RISCV_CPU(obj); 1465 CPURISCVState *env = &cpu->env; 1466 bool value; 1467 1468 if (!visit_type_bool(v, name, &value, errp)) { 1469 return; 1470 } 1471 1472 if (value) { 1473 env->misa_ext |= misa_bit; 1474 env->misa_ext_mask |= misa_bit; 1475 } else { 1476 env->misa_ext &= ~misa_bit; 1477 env->misa_ext_mask &= ~misa_bit; 1478 } 1479 } 1480 1481 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1482 void *opaque, Error **errp) 1483 { 1484 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1485 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1486 RISCVCPU *cpu = RISCV_CPU(obj); 1487 CPURISCVState *env = &cpu->env; 1488 bool value; 1489 1490 value = env->misa_ext & misa_bit; 1491 1492 visit_type_bool(v, name, &value, errp); 1493 } 1494 1495 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1496 {.name = "a", .description = "Atomic instructions", 1497 .misa_bit = RVA, .enabled = true}, 1498 {.name = "c", .description = "Compressed instructions", 1499 .misa_bit = RVC, .enabled = true}, 1500 {.name = "d", .description = "Double-precision float point", 1501 .misa_bit = RVD, .enabled = true}, 1502 {.name = "f", .description = "Single-precision float point", 1503 .misa_bit = RVF, .enabled = true}, 1504 {.name = "i", .description = "Base integer instruction set", 1505 .misa_bit = RVI, .enabled = true}, 1506 {.name = "e", .description = "Base integer instruction set (embedded)", 1507 .misa_bit = RVE, .enabled = false}, 1508 }; 1509 1510 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1511 { 1512 int i; 1513 1514 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1515 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1516 1517 object_property_add(cpu_obj, misa_cfg->name, "bool", 1518 cpu_get_misa_ext_cfg, 1519 cpu_set_misa_ext_cfg, 1520 NULL, (void *)misa_cfg); 1521 object_property_set_description(cpu_obj, misa_cfg->name, 1522 misa_cfg->description); 1523 object_property_set_bool(cpu_obj, misa_cfg->name, 1524 misa_cfg->enabled, NULL); 1525 } 1526 } 1527 1528 static Property riscv_cpu_extensions[] = { 1529 /* Defaults for standard extensions */ 1530 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1531 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 1532 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 1533 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1534 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1535 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1536 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1537 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1538 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1539 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1540 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1541 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1542 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1543 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1544 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1545 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1546 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), 1547 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1548 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1549 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1550 1551 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1552 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1553 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1554 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1555 1556 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), 1557 1558 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1559 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1560 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1561 1562 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1563 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1564 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1565 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1566 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1567 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1568 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1569 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1570 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1571 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1572 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1573 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1574 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1575 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1576 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1577 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1578 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1579 1580 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1581 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1582 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1583 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1584 1585 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), 1586 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), 1587 DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), 1588 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), 1589 1590 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1591 1592 /* Vendor-specific custom extensions */ 1593 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1594 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1595 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1596 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1597 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1598 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1599 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1600 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1601 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1602 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1603 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1604 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1605 1606 /* These are experimental so mark with 'x-' */ 1607 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), 1608 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1609 1610 DEFINE_PROP_BOOL("x-zca", RISCVCPU, cfg.ext_zca, false), 1611 DEFINE_PROP_BOOL("x-zcb", RISCVCPU, cfg.ext_zcb, false), 1612 DEFINE_PROP_BOOL("x-zcd", RISCVCPU, cfg.ext_zcd, false), 1613 DEFINE_PROP_BOOL("x-zce", RISCVCPU, cfg.ext_zce, false), 1614 DEFINE_PROP_BOOL("x-zcf", RISCVCPU, cfg.ext_zcf, false), 1615 DEFINE_PROP_BOOL("x-zcmp", RISCVCPU, cfg.ext_zcmp, false), 1616 DEFINE_PROP_BOOL("x-zcmt", RISCVCPU, cfg.ext_zcmt, false), 1617 1618 /* ePMP 0.9.3 */ 1619 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1620 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1621 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1622 1623 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), 1624 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), 1625 1626 DEFINE_PROP_END_OF_LIST(), 1627 }; 1628 1629 /* 1630 * Register CPU props based on env.misa_ext. If a non-zero 1631 * value was set, register only the required cpu->cfg.ext_* 1632 * properties and leave. env.misa_ext = 0 means that we want 1633 * all the default properties to be registered. 1634 */ 1635 static void register_cpu_props(Object *obj) 1636 { 1637 RISCVCPU *cpu = RISCV_CPU(obj); 1638 uint32_t misa_ext = cpu->env.misa_ext; 1639 Property *prop; 1640 DeviceState *dev = DEVICE(obj); 1641 1642 /* 1643 * If misa_ext is not zero, set cfg properties now to 1644 * allow them to be read during riscv_cpu_realize() 1645 * later on. 1646 */ 1647 if (cpu->env.misa_ext != 0) { 1648 cpu->cfg.ext_m = misa_ext & RVM; 1649 cpu->cfg.ext_v = misa_ext & RVV; 1650 cpu->cfg.ext_s = misa_ext & RVS; 1651 cpu->cfg.ext_u = misa_ext & RVU; 1652 cpu->cfg.ext_h = misa_ext & RVH; 1653 cpu->cfg.ext_j = misa_ext & RVJ; 1654 1655 /* 1656 * We don't want to set the default riscv_cpu_extensions 1657 * in this case. 1658 */ 1659 return; 1660 } 1661 1662 riscv_cpu_add_misa_properties(obj); 1663 1664 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1665 qdev_property_add_static(dev, prop); 1666 } 1667 1668 #ifndef CONFIG_USER_ONLY 1669 riscv_add_satp_mode_properties(obj); 1670 #endif 1671 } 1672 1673 static Property riscv_cpu_properties[] = { 1674 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1675 1676 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1677 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1678 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1679 1680 #ifndef CONFIG_USER_ONLY 1681 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1682 #endif 1683 1684 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1685 1686 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1687 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1688 1689 /* 1690 * write_misa() is marked as experimental for now so mark 1691 * it with -x and default to 'false'. 1692 */ 1693 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1694 DEFINE_PROP_END_OF_LIST(), 1695 }; 1696 1697 static gchar *riscv_gdb_arch_name(CPUState *cs) 1698 { 1699 RISCVCPU *cpu = RISCV_CPU(cs); 1700 CPURISCVState *env = &cpu->env; 1701 1702 switch (riscv_cpu_mxl(env)) { 1703 case MXL_RV32: 1704 return g_strdup("riscv:rv32"); 1705 case MXL_RV64: 1706 case MXL_RV128: 1707 return g_strdup("riscv:rv64"); 1708 default: 1709 g_assert_not_reached(); 1710 } 1711 } 1712 1713 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1714 { 1715 RISCVCPU *cpu = RISCV_CPU(cs); 1716 1717 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1718 return cpu->dyn_csr_xml; 1719 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1720 return cpu->dyn_vreg_xml; 1721 } 1722 1723 return NULL; 1724 } 1725 1726 #ifndef CONFIG_USER_ONLY 1727 static int64_t riscv_get_arch_id(CPUState *cs) 1728 { 1729 RISCVCPU *cpu = RISCV_CPU(cs); 1730 1731 return cpu->env.mhartid; 1732 } 1733 1734 #include "hw/core/sysemu-cpu-ops.h" 1735 1736 static const struct SysemuCPUOps riscv_sysemu_ops = { 1737 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1738 .write_elf64_note = riscv_cpu_write_elf64_note, 1739 .write_elf32_note = riscv_cpu_write_elf32_note, 1740 .legacy_vmsd = &vmstate_riscv_cpu, 1741 }; 1742 #endif 1743 1744 #include "hw/core/tcg-cpu-ops.h" 1745 1746 static const struct TCGCPUOps riscv_tcg_ops = { 1747 .initialize = riscv_translate_init, 1748 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1749 .restore_state_to_opc = riscv_restore_state_to_opc, 1750 1751 #ifndef CONFIG_USER_ONLY 1752 .tlb_fill = riscv_cpu_tlb_fill, 1753 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1754 .do_interrupt = riscv_cpu_do_interrupt, 1755 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1756 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1757 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1758 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1759 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1760 #endif /* !CONFIG_USER_ONLY */ 1761 }; 1762 1763 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1764 { 1765 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1766 CPUClass *cc = CPU_CLASS(c); 1767 DeviceClass *dc = DEVICE_CLASS(c); 1768 ResettableClass *rc = RESETTABLE_CLASS(c); 1769 1770 device_class_set_parent_realize(dc, riscv_cpu_realize, 1771 &mcc->parent_realize); 1772 1773 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1774 &mcc->parent_phases); 1775 1776 cc->class_by_name = riscv_cpu_class_by_name; 1777 cc->has_work = riscv_cpu_has_work; 1778 cc->dump_state = riscv_cpu_dump_state; 1779 cc->set_pc = riscv_cpu_set_pc; 1780 cc->get_pc = riscv_cpu_get_pc; 1781 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1782 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1783 cc->gdb_num_core_regs = 33; 1784 cc->gdb_stop_before_watchpoint = true; 1785 cc->disas_set_info = riscv_cpu_disas_set_info; 1786 #ifndef CONFIG_USER_ONLY 1787 cc->sysemu_ops = &riscv_sysemu_ops; 1788 cc->get_arch_id = riscv_get_arch_id; 1789 #endif 1790 cc->gdb_arch_name = riscv_gdb_arch_name; 1791 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1792 cc->tcg_ops = &riscv_tcg_ops; 1793 1794 device_class_set_props(dc, riscv_cpu_properties); 1795 } 1796 1797 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, 1798 int max_str_len) 1799 { 1800 char *old = *isa_str; 1801 char *new = *isa_str; 1802 int i; 1803 1804 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1805 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1806 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1807 g_free(old); 1808 old = new; 1809 } 1810 } 1811 1812 *isa_str = new; 1813 } 1814 1815 char *riscv_isa_string(RISCVCPU *cpu) 1816 { 1817 int i; 1818 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1819 char *isa_str = g_new(char, maxlen); 1820 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1821 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1822 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1823 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1824 } 1825 } 1826 *p = '\0'; 1827 if (!cpu->cfg.short_isa_string) { 1828 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1829 } 1830 return isa_str; 1831 } 1832 1833 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1834 { 1835 ObjectClass *class_a = (ObjectClass *)a; 1836 ObjectClass *class_b = (ObjectClass *)b; 1837 const char *name_a, *name_b; 1838 1839 name_a = object_class_get_name(class_a); 1840 name_b = object_class_get_name(class_b); 1841 return strcmp(name_a, name_b); 1842 } 1843 1844 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1845 { 1846 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1847 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1848 1849 qemu_printf("%.*s\n", len, typename); 1850 } 1851 1852 void riscv_cpu_list(void) 1853 { 1854 GSList *list; 1855 1856 list = object_class_get_list(TYPE_RISCV_CPU, false); 1857 list = g_slist_sort(list, riscv_cpu_list_compare); 1858 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1859 g_slist_free(list); 1860 } 1861 1862 #define DEFINE_CPU(type_name, initfn) \ 1863 { \ 1864 .name = type_name, \ 1865 .parent = TYPE_RISCV_CPU, \ 1866 .instance_init = initfn \ 1867 } 1868 1869 static const TypeInfo riscv_cpu_type_infos[] = { 1870 { 1871 .name = TYPE_RISCV_CPU, 1872 .parent = TYPE_CPU, 1873 .instance_size = sizeof(RISCVCPU), 1874 .instance_align = __alignof__(RISCVCPU), 1875 .instance_init = riscv_cpu_init, 1876 .abstract = true, 1877 .class_size = sizeof(RISCVCPUClass), 1878 .class_init = riscv_cpu_class_init, 1879 }, 1880 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1881 #if defined(CONFIG_KVM) 1882 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1883 #endif 1884 #if defined(TARGET_RISCV32) 1885 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1886 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1887 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1888 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1889 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1890 #elif defined(TARGET_RISCV64) 1891 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1892 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1893 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1894 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1895 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1896 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1897 #endif 1898 }; 1899 1900 DEFINE_TYPES(riscv_cpu_type_infos) 1901