1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "exec/exec-all.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "fpu/softfloat-helpers.h" 32 33 /* RISC-V CPU definitions */ 34 35 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 36 37 const char * const riscv_int_regnames[] = { 38 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 39 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 40 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 41 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 42 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 43 }; 44 45 const char * const riscv_fpr_regnames[] = { 46 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 47 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 48 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 49 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 50 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 51 "f30/ft10", "f31/ft11" 52 }; 53 54 static const char * const riscv_excp_names[] = { 55 "misaligned_fetch", 56 "fault_fetch", 57 "illegal_instruction", 58 "breakpoint", 59 "misaligned_load", 60 "fault_load", 61 "misaligned_store", 62 "fault_store", 63 "user_ecall", 64 "supervisor_ecall", 65 "hypervisor_ecall", 66 "machine_ecall", 67 "exec_page_fault", 68 "load_page_fault", 69 "reserved", 70 "store_page_fault", 71 "reserved", 72 "reserved", 73 "reserved", 74 "reserved", 75 "guest_exec_page_fault", 76 "guest_load_page_fault", 77 "reserved", 78 "guest_store_page_fault", 79 }; 80 81 static const char * const riscv_intr_names[] = { 82 "u_software", 83 "s_software", 84 "vs_software", 85 "m_software", 86 "u_timer", 87 "s_timer", 88 "vs_timer", 89 "m_timer", 90 "u_external", 91 "s_external", 92 "vs_external", 93 "m_external", 94 "reserved", 95 "reserved", 96 "reserved", 97 "reserved" 98 }; 99 100 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 101 { 102 if (async) { 103 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 104 riscv_intr_names[cause] : "(unknown)"; 105 } else { 106 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 107 riscv_excp_names[cause] : "(unknown)"; 108 } 109 } 110 111 bool riscv_cpu_is_32bit(CPURISCVState *env) 112 { 113 if (env->misa & RV64) { 114 return false; 115 } 116 117 return true; 118 } 119 120 static void set_misa(CPURISCVState *env, target_ulong misa) 121 { 122 env->misa_mask = env->misa = misa; 123 } 124 125 static void set_priv_version(CPURISCVState *env, int priv_ver) 126 { 127 env->priv_ver = priv_ver; 128 } 129 130 static void set_bext_version(CPURISCVState *env, int bext_ver) 131 { 132 env->bext_ver = bext_ver; 133 } 134 135 static void set_vext_version(CPURISCVState *env, int vext_ver) 136 { 137 env->vext_ver = vext_ver; 138 } 139 140 static void set_feature(CPURISCVState *env, int feature) 141 { 142 env->features |= (1ULL << feature); 143 } 144 145 static void set_resetvec(CPURISCVState *env, target_ulong resetvec) 146 { 147 #ifndef CONFIG_USER_ONLY 148 env->resetvec = resetvec; 149 #endif 150 } 151 152 static void riscv_any_cpu_init(Object *obj) 153 { 154 CPURISCVState *env = &RISCV_CPU(obj)->env; 155 #if defined(TARGET_RISCV32) 156 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); 157 #elif defined(TARGET_RISCV64) 158 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVU); 159 #endif 160 set_priv_version(env, PRIV_VERSION_1_11_0); 161 } 162 163 #if defined(TARGET_RISCV64) 164 static void rv64_base_cpu_init(Object *obj) 165 { 166 CPURISCVState *env = &RISCV_CPU(obj)->env; 167 /* We set this in the realise function */ 168 set_misa(env, RV64); 169 } 170 171 static void rv64_sifive_u_cpu_init(Object *obj) 172 { 173 CPURISCVState *env = &RISCV_CPU(obj)->env; 174 set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 175 set_priv_version(env, PRIV_VERSION_1_10_0); 176 } 177 178 static void rv64_sifive_e_cpu_init(Object *obj) 179 { 180 CPURISCVState *env = &RISCV_CPU(obj)->env; 181 set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); 182 set_priv_version(env, PRIV_VERSION_1_10_0); 183 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 184 } 185 #else 186 static void rv32_base_cpu_init(Object *obj) 187 { 188 CPURISCVState *env = &RISCV_CPU(obj)->env; 189 /* We set this in the realise function */ 190 set_misa(env, RV32); 191 } 192 193 static void rv32_sifive_u_cpu_init(Object *obj) 194 { 195 CPURISCVState *env = &RISCV_CPU(obj)->env; 196 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 197 set_priv_version(env, PRIV_VERSION_1_10_0); 198 } 199 200 static void rv32_sifive_e_cpu_init(Object *obj) 201 { 202 CPURISCVState *env = &RISCV_CPU(obj)->env; 203 set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); 204 set_priv_version(env, PRIV_VERSION_1_10_0); 205 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 206 } 207 208 static void rv32_ibex_cpu_init(Object *obj) 209 { 210 CPURISCVState *env = &RISCV_CPU(obj)->env; 211 set_misa(env, RV32 | RVI | RVM | RVC | RVU); 212 set_priv_version(env, PRIV_VERSION_1_10_0); 213 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 214 qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); 215 } 216 217 static void rv32_imafcu_nommu_cpu_init(Object *obj) 218 { 219 CPURISCVState *env = &RISCV_CPU(obj)->env; 220 set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC | RVU); 221 set_priv_version(env, PRIV_VERSION_1_10_0); 222 set_resetvec(env, DEFAULT_RSTVEC); 223 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 224 } 225 #endif 226 227 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 228 { 229 ObjectClass *oc; 230 char *typename; 231 char **cpuname; 232 233 cpuname = g_strsplit(cpu_model, ",", 1); 234 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 235 oc = object_class_by_name(typename); 236 g_strfreev(cpuname); 237 g_free(typename); 238 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 239 object_class_is_abstract(oc)) { 240 return NULL; 241 } 242 return oc; 243 } 244 245 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 246 { 247 RISCVCPU *cpu = RISCV_CPU(cs); 248 CPURISCVState *env = &cpu->env; 249 int i; 250 251 #if !defined(CONFIG_USER_ONLY) 252 if (riscv_has_ext(env, RVH)) { 253 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 254 } 255 #endif 256 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 257 #ifndef CONFIG_USER_ONLY 258 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); 259 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", (target_ulong)env->mstatus); 260 if (riscv_cpu_is_32bit(env)) { 261 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatush ", 262 (target_ulong)(env->mstatus >> 32)); 263 } 264 if (riscv_has_ext(env, RVH)) { 265 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hstatus ", env->hstatus); 266 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsstatus ", 267 (target_ulong)env->vsstatus); 268 } 269 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", env->mip); 270 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); 271 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); 272 if (riscv_has_ext(env, RVH)) { 273 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hideleg ", env->hideleg); 274 } 275 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); 276 if (riscv_has_ext(env, RVH)) { 277 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "hedeleg ", env->hedeleg); 278 } 279 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); 280 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stvec ", env->stvec); 281 if (riscv_has_ext(env, RVH)) { 282 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vstvec ", env->vstvec); 283 } 284 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); 285 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sepc ", env->sepc); 286 if (riscv_has_ext(env, RVH)) { 287 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vsepc ", env->vsepc); 288 } 289 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); 290 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "scause ", env->scause); 291 if (riscv_has_ext(env, RVH)) { 292 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "vscause ", env->vscause); 293 } 294 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval ", env->mtval); 295 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "stval ", env->stval); 296 if (riscv_has_ext(env, RVH)) { 297 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "htval ", env->htval); 298 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtval2 ", env->mtval2); 299 } 300 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mscratch", env->mscratch); 301 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "sscratch", env->sscratch); 302 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "satp ", env->satp); 303 #endif 304 305 for (i = 0; i < 32; i++) { 306 qemu_fprintf(f, " %s " TARGET_FMT_lx, 307 riscv_int_regnames[i], env->gpr[i]); 308 if ((i & 3) == 3) { 309 qemu_fprintf(f, "\n"); 310 } 311 } 312 if (flags & CPU_DUMP_FPU) { 313 for (i = 0; i < 32; i++) { 314 qemu_fprintf(f, " %s %016" PRIx64, 315 riscv_fpr_regnames[i], env->fpr[i]); 316 if ((i & 3) == 3) { 317 qemu_fprintf(f, "\n"); 318 } 319 } 320 } 321 } 322 323 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 324 { 325 RISCVCPU *cpu = RISCV_CPU(cs); 326 CPURISCVState *env = &cpu->env; 327 env->pc = value; 328 } 329 330 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 331 const TranslationBlock *tb) 332 { 333 RISCVCPU *cpu = RISCV_CPU(cs); 334 CPURISCVState *env = &cpu->env; 335 env->pc = tb->pc; 336 } 337 338 static bool riscv_cpu_has_work(CPUState *cs) 339 { 340 #ifndef CONFIG_USER_ONLY 341 RISCVCPU *cpu = RISCV_CPU(cs); 342 CPURISCVState *env = &cpu->env; 343 /* 344 * Definition of the WFI instruction requires it to ignore the privilege 345 * mode and delegation registers, but respect individual enables 346 */ 347 return (env->mip & env->mie) != 0; 348 #else 349 return true; 350 #endif 351 } 352 353 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 354 target_ulong *data) 355 { 356 env->pc = data[0]; 357 } 358 359 static void riscv_cpu_reset(DeviceState *dev) 360 { 361 CPUState *cs = CPU(dev); 362 RISCVCPU *cpu = RISCV_CPU(cs); 363 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 364 CPURISCVState *env = &cpu->env; 365 366 mcc->parent_reset(dev); 367 #ifndef CONFIG_USER_ONLY 368 env->priv = PRV_M; 369 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 370 env->mcause = 0; 371 env->pc = env->resetvec; 372 env->two_stage_lookup = false; 373 #endif 374 cs->exception_index = RISCV_EXCP_NONE; 375 env->load_res = -1; 376 set_default_nan_mode(1, &env->fp_status); 377 } 378 379 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 380 { 381 RISCVCPU *cpu = RISCV_CPU(s); 382 if (riscv_cpu_is_32bit(&cpu->env)) { 383 info->print_insn = print_insn_riscv32; 384 } else { 385 info->print_insn = print_insn_riscv64; 386 } 387 } 388 389 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 390 { 391 CPUState *cs = CPU(dev); 392 RISCVCPU *cpu = RISCV_CPU(dev); 393 CPURISCVState *env = &cpu->env; 394 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 395 int priv_version = PRIV_VERSION_1_11_0; 396 int bext_version = BEXT_VERSION_0_93_0; 397 int vext_version = VEXT_VERSION_0_07_1; 398 target_ulong target_misa = env->misa; 399 Error *local_err = NULL; 400 401 cpu_exec_realizefn(cs, &local_err); 402 if (local_err != NULL) { 403 error_propagate(errp, local_err); 404 return; 405 } 406 407 if (cpu->cfg.priv_spec) { 408 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 409 priv_version = PRIV_VERSION_1_11_0; 410 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 411 priv_version = PRIV_VERSION_1_10_0; 412 } else { 413 error_setg(errp, 414 "Unsupported privilege spec version '%s'", 415 cpu->cfg.priv_spec); 416 return; 417 } 418 } 419 420 set_priv_version(env, priv_version); 421 set_bext_version(env, bext_version); 422 set_vext_version(env, vext_version); 423 424 if (cpu->cfg.mmu) { 425 set_feature(env, RISCV_FEATURE_MMU); 426 } 427 428 if (cpu->cfg.pmp) { 429 set_feature(env, RISCV_FEATURE_PMP); 430 431 /* 432 * Enhanced PMP should only be available 433 * on harts with PMP support 434 */ 435 if (cpu->cfg.epmp) { 436 set_feature(env, RISCV_FEATURE_EPMP); 437 } 438 } 439 440 set_resetvec(env, cpu->cfg.resetvec); 441 442 /* If only XLEN is set for misa, then set misa from properties */ 443 if (env->misa == RV32 || env->misa == RV64) { 444 /* Do some ISA extension error checking */ 445 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 446 error_setg(errp, 447 "I and E extensions are incompatible"); 448 return; 449 } 450 451 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 452 error_setg(errp, 453 "Either I or E extension must be set"); 454 return; 455 } 456 457 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 458 cpu->cfg.ext_a & cpu->cfg.ext_f & 459 cpu->cfg.ext_d)) { 460 warn_report("Setting G will also set IMAFD"); 461 cpu->cfg.ext_i = true; 462 cpu->cfg.ext_m = true; 463 cpu->cfg.ext_a = true; 464 cpu->cfg.ext_f = true; 465 cpu->cfg.ext_d = true; 466 } 467 468 /* Set the ISA extensions, checks should have happened above */ 469 if (cpu->cfg.ext_i) { 470 target_misa |= RVI; 471 } 472 if (cpu->cfg.ext_e) { 473 target_misa |= RVE; 474 } 475 if (cpu->cfg.ext_m) { 476 target_misa |= RVM; 477 } 478 if (cpu->cfg.ext_a) { 479 target_misa |= RVA; 480 } 481 if (cpu->cfg.ext_f) { 482 target_misa |= RVF; 483 } 484 if (cpu->cfg.ext_d) { 485 target_misa |= RVD; 486 } 487 if (cpu->cfg.ext_c) { 488 target_misa |= RVC; 489 } 490 if (cpu->cfg.ext_s) { 491 target_misa |= RVS; 492 } 493 if (cpu->cfg.ext_u) { 494 target_misa |= RVU; 495 } 496 if (cpu->cfg.ext_h) { 497 target_misa |= RVH; 498 } 499 if (cpu->cfg.ext_b) { 500 target_misa |= RVB; 501 502 if (cpu->cfg.bext_spec) { 503 if (!g_strcmp0(cpu->cfg.bext_spec, "v0.93")) { 504 bext_version = BEXT_VERSION_0_93_0; 505 } else { 506 error_setg(errp, 507 "Unsupported bitmanip spec version '%s'", 508 cpu->cfg.bext_spec); 509 return; 510 } 511 } else { 512 qemu_log("bitmanip version is not specified, " 513 "use the default value v0.93\n"); 514 } 515 set_bext_version(env, bext_version); 516 } 517 if (cpu->cfg.ext_v) { 518 target_misa |= RVV; 519 if (!is_power_of_2(cpu->cfg.vlen)) { 520 error_setg(errp, 521 "Vector extension VLEN must be power of 2"); 522 return; 523 } 524 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 525 error_setg(errp, 526 "Vector extension implementation only supports VLEN " 527 "in the range [128, %d]", RV_VLEN_MAX); 528 return; 529 } 530 if (!is_power_of_2(cpu->cfg.elen)) { 531 error_setg(errp, 532 "Vector extension ELEN must be power of 2"); 533 return; 534 } 535 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 536 error_setg(errp, 537 "Vector extension implementation only supports ELEN " 538 "in the range [8, 64]"); 539 return; 540 } 541 if (cpu->cfg.vext_spec) { 542 if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { 543 vext_version = VEXT_VERSION_0_07_1; 544 } else { 545 error_setg(errp, 546 "Unsupported vector spec version '%s'", 547 cpu->cfg.vext_spec); 548 return; 549 } 550 } else { 551 qemu_log("vector version is not specified, " 552 "use the default value v0.7.1\n"); 553 } 554 set_vext_version(env, vext_version); 555 } 556 557 set_misa(env, target_misa); 558 } 559 560 riscv_cpu_register_gdb_regs_for_features(cs); 561 562 qemu_init_vcpu(cs); 563 cpu_reset(cs); 564 565 mcc->parent_realize(dev, errp); 566 } 567 568 static void riscv_cpu_init(Object *obj) 569 { 570 RISCVCPU *cpu = RISCV_CPU(obj); 571 572 cpu_set_cpustate_pointers(cpu); 573 } 574 575 static Property riscv_cpu_properties[] = { 576 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 577 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 578 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 579 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 580 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 581 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 582 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 583 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 584 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 585 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 586 /* This is experimental so mark with 'x-' */ 587 DEFINE_PROP_BOOL("x-b", RISCVCPU, cfg.ext_b, false), 588 DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), 589 DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), 590 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 591 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 592 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 593 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 594 DEFINE_PROP_STRING("bext_spec", RISCVCPU, cfg.bext_spec), 595 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 596 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 597 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 598 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 599 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 600 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 601 602 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 603 DEFINE_PROP_END_OF_LIST(), 604 }; 605 606 static gchar *riscv_gdb_arch_name(CPUState *cs) 607 { 608 RISCVCPU *cpu = RISCV_CPU(cs); 609 CPURISCVState *env = &cpu->env; 610 611 if (riscv_cpu_is_32bit(env)) { 612 return g_strdup("riscv:rv32"); 613 } else { 614 return g_strdup("riscv:rv64"); 615 } 616 } 617 618 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 619 { 620 RISCVCPU *cpu = RISCV_CPU(cs); 621 622 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 623 return cpu->dyn_csr_xml; 624 } 625 626 return NULL; 627 } 628 629 #ifndef CONFIG_USER_ONLY 630 #include "hw/core/sysemu-cpu-ops.h" 631 632 static const struct SysemuCPUOps riscv_sysemu_ops = { 633 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 634 .write_elf64_note = riscv_cpu_write_elf64_note, 635 .write_elf32_note = riscv_cpu_write_elf32_note, 636 .legacy_vmsd = &vmstate_riscv_cpu, 637 }; 638 #endif 639 640 #include "hw/core/tcg-cpu-ops.h" 641 642 static const struct TCGCPUOps riscv_tcg_ops = { 643 .initialize = riscv_translate_init, 644 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 645 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 646 .tlb_fill = riscv_cpu_tlb_fill, 647 648 #ifndef CONFIG_USER_ONLY 649 .do_interrupt = riscv_cpu_do_interrupt, 650 .do_transaction_failed = riscv_cpu_do_transaction_failed, 651 .do_unaligned_access = riscv_cpu_do_unaligned_access, 652 #endif /* !CONFIG_USER_ONLY */ 653 }; 654 655 static void riscv_cpu_class_init(ObjectClass *c, void *data) 656 { 657 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 658 CPUClass *cc = CPU_CLASS(c); 659 DeviceClass *dc = DEVICE_CLASS(c); 660 661 device_class_set_parent_realize(dc, riscv_cpu_realize, 662 &mcc->parent_realize); 663 664 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 665 666 cc->class_by_name = riscv_cpu_class_by_name; 667 cc->has_work = riscv_cpu_has_work; 668 cc->dump_state = riscv_cpu_dump_state; 669 cc->set_pc = riscv_cpu_set_pc; 670 cc->gdb_read_register = riscv_cpu_gdb_read_register; 671 cc->gdb_write_register = riscv_cpu_gdb_write_register; 672 cc->gdb_num_core_regs = 33; 673 #if defined(TARGET_RISCV32) 674 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 675 #elif defined(TARGET_RISCV64) 676 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 677 #endif 678 cc->gdb_stop_before_watchpoint = true; 679 cc->disas_set_info = riscv_cpu_disas_set_info; 680 #ifndef CONFIG_USER_ONLY 681 cc->sysemu_ops = &riscv_sysemu_ops; 682 #endif 683 cc->gdb_arch_name = riscv_gdb_arch_name; 684 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 685 cc->tcg_ops = &riscv_tcg_ops; 686 687 device_class_set_props(dc, riscv_cpu_properties); 688 } 689 690 char *riscv_isa_string(RISCVCPU *cpu) 691 { 692 int i; 693 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 694 char *isa_str = g_new(char, maxlen); 695 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 696 for (i = 0; i < sizeof(riscv_exts); i++) { 697 if (cpu->env.misa & RV(riscv_exts[i])) { 698 *p++ = qemu_tolower(riscv_exts[i]); 699 } 700 } 701 *p = '\0'; 702 return isa_str; 703 } 704 705 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 706 { 707 ObjectClass *class_a = (ObjectClass *)a; 708 ObjectClass *class_b = (ObjectClass *)b; 709 const char *name_a, *name_b; 710 711 name_a = object_class_get_name(class_a); 712 name_b = object_class_get_name(class_b); 713 return strcmp(name_a, name_b); 714 } 715 716 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 717 { 718 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 719 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 720 721 qemu_printf("%.*s\n", len, typename); 722 } 723 724 void riscv_cpu_list(void) 725 { 726 GSList *list; 727 728 list = object_class_get_list(TYPE_RISCV_CPU, false); 729 list = g_slist_sort(list, riscv_cpu_list_compare); 730 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 731 g_slist_free(list); 732 } 733 734 #define DEFINE_CPU(type_name, initfn) \ 735 { \ 736 .name = type_name, \ 737 .parent = TYPE_RISCV_CPU, \ 738 .instance_init = initfn \ 739 } 740 741 static const TypeInfo riscv_cpu_type_infos[] = { 742 { 743 .name = TYPE_RISCV_CPU, 744 .parent = TYPE_CPU, 745 .instance_size = sizeof(RISCVCPU), 746 .instance_align = __alignof__(RISCVCPU), 747 .instance_init = riscv_cpu_init, 748 .abstract = true, 749 .class_size = sizeof(RISCVCPUClass), 750 .class_init = riscv_cpu_class_init, 751 }, 752 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 753 #if defined(TARGET_RISCV32) 754 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 755 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 756 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 757 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 758 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 759 #elif defined(TARGET_RISCV64) 760 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 761 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 762 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 763 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 764 #endif 765 }; 766 767 DEFINE_TYPES(riscv_cpu_type_infos) 768