1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "qemu/error-report.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "fpu/softfloat-helpers.h" 36 #include "sysemu/kvm.h" 37 #include "kvm_riscv.h" 38 #include "tcg/tcg.h" 39 40 /* RISC-V CPU definitions */ 41 42 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 43 (QEMU_VERSION_MINOR << 8) | \ 44 (QEMU_VERSION_MICRO)) 45 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 46 47 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 48 49 struct isa_ext_data { 50 const char *name; 51 int min_version; 52 int ext_enable_offset; 53 }; 54 55 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ 56 {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 57 58 /* 59 * Here are the ordering rules of extension naming defined by RISC-V 60 * specification : 61 * 1. All extensions should be separated from other multi-letter extensions 62 * by an underscore. 63 * 2. The first letter following the 'Z' conventionally indicates the most 64 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 65 * If multiple 'Z' extensions are named, they should be ordered first 66 * by category, then alphabetically within a category. 67 * 3. Standard supervisor-level extensions (starts with 'S') should be 68 * listed after standard unprivileged extensions. If multiple 69 * supervisor-level extensions are listed, they should be ordered 70 * alphabetically. 71 * 4. Non-standard extensions (starts with 'X') must be listed after all 72 * standard extensions. They must be separated from other multi-letter 73 * extensions by an underscore. 74 * 75 * Single letter extensions are checked in riscv_cpu_validate_misa_priv() 76 * instead. 77 */ 78 static const struct isa_ext_data isa_edata_arr[] = { 79 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), 80 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), 81 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), 82 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), 83 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), 84 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), 85 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), 86 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), 87 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), 88 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), 89 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), 90 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), 91 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), 92 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), 93 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), 94 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), 95 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), 96 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), 97 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), 98 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), 99 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), 100 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), 101 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), 102 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), 103 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), 104 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), 105 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), 106 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), 107 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), 108 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), 109 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), 110 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), 111 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), 112 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), 113 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), 114 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), 115 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), 116 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), 117 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), 118 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), 119 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), 120 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), 121 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), 122 ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), 123 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), 124 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), 125 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), 126 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), 127 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), 128 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), 129 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), 130 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), 131 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), 132 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), 133 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), 134 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 135 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 136 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), 137 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), 138 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 139 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), 140 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), 141 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 142 }; 143 144 static bool isa_ext_is_enabled(RISCVCPU *cpu, 145 const struct isa_ext_data *edata) 146 { 147 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 148 149 return *ext_enabled; 150 } 151 152 static void isa_ext_update_enabled(RISCVCPU *cpu, 153 const struct isa_ext_data *edata, bool en) 154 { 155 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 156 157 *ext_enabled = en; 158 } 159 160 const char * const riscv_int_regnames[] = { 161 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 162 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 163 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 164 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 165 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 166 }; 167 168 const char * const riscv_int_regnamesh[] = { 169 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 170 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 171 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 172 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 173 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 174 "x30h/t5h", "x31h/t6h" 175 }; 176 177 const char * const riscv_fpr_regnames[] = { 178 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 179 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 180 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 181 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 182 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 183 "f30/ft10", "f31/ft11" 184 }; 185 186 static const char * const riscv_excp_names[] = { 187 "misaligned_fetch", 188 "fault_fetch", 189 "illegal_instruction", 190 "breakpoint", 191 "misaligned_load", 192 "fault_load", 193 "misaligned_store", 194 "fault_store", 195 "user_ecall", 196 "supervisor_ecall", 197 "hypervisor_ecall", 198 "machine_ecall", 199 "exec_page_fault", 200 "load_page_fault", 201 "reserved", 202 "store_page_fault", 203 "reserved", 204 "reserved", 205 "reserved", 206 "reserved", 207 "guest_exec_page_fault", 208 "guest_load_page_fault", 209 "reserved", 210 "guest_store_page_fault", 211 }; 212 213 static const char * const riscv_intr_names[] = { 214 "u_software", 215 "s_software", 216 "vs_software", 217 "m_software", 218 "u_timer", 219 "s_timer", 220 "vs_timer", 221 "m_timer", 222 "u_external", 223 "s_external", 224 "vs_external", 225 "m_external", 226 "reserved", 227 "reserved", 228 "reserved", 229 "reserved" 230 }; 231 232 static void riscv_cpu_add_user_properties(Object *obj); 233 234 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 235 { 236 if (async) { 237 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 238 riscv_intr_names[cause] : "(unknown)"; 239 } else { 240 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 241 riscv_excp_names[cause] : "(unknown)"; 242 } 243 } 244 245 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 246 { 247 env->misa_mxl_max = env->misa_mxl = mxl; 248 env->misa_ext_mask = env->misa_ext = ext; 249 } 250 251 #ifndef CONFIG_USER_ONLY 252 static uint8_t satp_mode_from_str(const char *satp_mode_str) 253 { 254 if (!strncmp(satp_mode_str, "mbare", 5)) { 255 return VM_1_10_MBARE; 256 } 257 258 if (!strncmp(satp_mode_str, "sv32", 4)) { 259 return VM_1_10_SV32; 260 } 261 262 if (!strncmp(satp_mode_str, "sv39", 4)) { 263 return VM_1_10_SV39; 264 } 265 266 if (!strncmp(satp_mode_str, "sv48", 4)) { 267 return VM_1_10_SV48; 268 } 269 270 if (!strncmp(satp_mode_str, "sv57", 4)) { 271 return VM_1_10_SV57; 272 } 273 274 if (!strncmp(satp_mode_str, "sv64", 4)) { 275 return VM_1_10_SV64; 276 } 277 278 g_assert_not_reached(); 279 } 280 281 uint8_t satp_mode_max_from_map(uint32_t map) 282 { 283 /* map here has at least one bit set, so no problem with clz */ 284 return 31 - __builtin_clz(map); 285 } 286 287 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) 288 { 289 if (is_32_bit) { 290 switch (satp_mode) { 291 case VM_1_10_SV32: 292 return "sv32"; 293 case VM_1_10_MBARE: 294 return "none"; 295 } 296 } else { 297 switch (satp_mode) { 298 case VM_1_10_SV64: 299 return "sv64"; 300 case VM_1_10_SV57: 301 return "sv57"; 302 case VM_1_10_SV48: 303 return "sv48"; 304 case VM_1_10_SV39: 305 return "sv39"; 306 case VM_1_10_MBARE: 307 return "none"; 308 } 309 } 310 311 g_assert_not_reached(); 312 } 313 314 static void set_satp_mode_max_supported(RISCVCPU *cpu, 315 uint8_t satp_mode) 316 { 317 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 318 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; 319 320 for (int i = 0; i <= satp_mode; ++i) { 321 if (valid_vm[i]) { 322 cpu->cfg.satp_mode.supported |= (1 << i); 323 } 324 } 325 } 326 327 /* Set the satp mode to the max supported */ 328 static void set_satp_mode_default_map(RISCVCPU *cpu) 329 { 330 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; 331 } 332 #endif 333 334 static void riscv_any_cpu_init(Object *obj) 335 { 336 RISCVCPU *cpu = RISCV_CPU(obj); 337 CPURISCVState *env = &cpu->env; 338 #if defined(TARGET_RISCV32) 339 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 340 #elif defined(TARGET_RISCV64) 341 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 342 #endif 343 344 #ifndef CONFIG_USER_ONLY 345 set_satp_mode_max_supported(RISCV_CPU(obj), 346 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? 347 VM_1_10_SV32 : VM_1_10_SV57); 348 #endif 349 350 env->priv_ver = PRIV_VERSION_LATEST; 351 352 /* inherited from parent obj via riscv_cpu_init() */ 353 cpu->cfg.ext_ifencei = true; 354 cpu->cfg.ext_icsr = true; 355 cpu->cfg.mmu = true; 356 cpu->cfg.pmp = true; 357 } 358 359 #if defined(TARGET_RISCV64) 360 static void rv64_base_cpu_init(Object *obj) 361 { 362 CPURISCVState *env = &RISCV_CPU(obj)->env; 363 /* We set this in the realise function */ 364 set_misa(env, MXL_RV64, 0); 365 riscv_cpu_add_user_properties(obj); 366 /* Set latest version of privileged specification */ 367 env->priv_ver = PRIV_VERSION_LATEST; 368 #ifndef CONFIG_USER_ONLY 369 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 370 #endif 371 } 372 373 static void rv64_sifive_u_cpu_init(Object *obj) 374 { 375 RISCVCPU *cpu = RISCV_CPU(obj); 376 CPURISCVState *env = &cpu->env; 377 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 378 env->priv_ver = PRIV_VERSION_1_10_0; 379 #ifndef CONFIG_USER_ONLY 380 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); 381 #endif 382 383 /* inherited from parent obj via riscv_cpu_init() */ 384 cpu->cfg.ext_ifencei = true; 385 cpu->cfg.ext_icsr = true; 386 cpu->cfg.mmu = true; 387 cpu->cfg.pmp = true; 388 } 389 390 static void rv64_sifive_e_cpu_init(Object *obj) 391 { 392 CPURISCVState *env = &RISCV_CPU(obj)->env; 393 RISCVCPU *cpu = RISCV_CPU(obj); 394 395 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 396 env->priv_ver = PRIV_VERSION_1_10_0; 397 #ifndef CONFIG_USER_ONLY 398 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 399 #endif 400 401 /* inherited from parent obj via riscv_cpu_init() */ 402 cpu->cfg.ext_ifencei = true; 403 cpu->cfg.ext_icsr = true; 404 cpu->cfg.pmp = true; 405 } 406 407 static void rv64_thead_c906_cpu_init(Object *obj) 408 { 409 CPURISCVState *env = &RISCV_CPU(obj)->env; 410 RISCVCPU *cpu = RISCV_CPU(obj); 411 412 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); 413 env->priv_ver = PRIV_VERSION_1_11_0; 414 415 cpu->cfg.ext_zfh = true; 416 cpu->cfg.mmu = true; 417 cpu->cfg.ext_xtheadba = true; 418 cpu->cfg.ext_xtheadbb = true; 419 cpu->cfg.ext_xtheadbs = true; 420 cpu->cfg.ext_xtheadcmo = true; 421 cpu->cfg.ext_xtheadcondmov = true; 422 cpu->cfg.ext_xtheadfmemidx = true; 423 cpu->cfg.ext_xtheadmac = true; 424 cpu->cfg.ext_xtheadmemidx = true; 425 cpu->cfg.ext_xtheadmempair = true; 426 cpu->cfg.ext_xtheadsync = true; 427 428 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 429 #ifndef CONFIG_USER_ONLY 430 set_satp_mode_max_supported(cpu, VM_1_10_SV39); 431 #endif 432 433 /* inherited from parent obj via riscv_cpu_init() */ 434 cpu->cfg.pmp = true; 435 } 436 437 static void rv64_veyron_v1_cpu_init(Object *obj) 438 { 439 CPURISCVState *env = &RISCV_CPU(obj)->env; 440 RISCVCPU *cpu = RISCV_CPU(obj); 441 442 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); 443 env->priv_ver = PRIV_VERSION_1_12_0; 444 445 /* Enable ISA extensions */ 446 cpu->cfg.mmu = true; 447 cpu->cfg.ext_icbom = true; 448 cpu->cfg.cbom_blocksize = 64; 449 cpu->cfg.cboz_blocksize = 64; 450 cpu->cfg.ext_icboz = true; 451 cpu->cfg.ext_smaia = true; 452 cpu->cfg.ext_ssaia = true; 453 cpu->cfg.ext_sscofpmf = true; 454 cpu->cfg.ext_sstc = true; 455 cpu->cfg.ext_svinval = true; 456 cpu->cfg.ext_svnapot = true; 457 cpu->cfg.ext_svpbmt = true; 458 cpu->cfg.ext_smstateen = true; 459 cpu->cfg.ext_zba = true; 460 cpu->cfg.ext_zbb = true; 461 cpu->cfg.ext_zbc = true; 462 cpu->cfg.ext_zbs = true; 463 cpu->cfg.ext_XVentanaCondOps = true; 464 465 cpu->cfg.mvendorid = VEYRON_V1_MVENDORID; 466 cpu->cfg.marchid = VEYRON_V1_MARCHID; 467 cpu->cfg.mimpid = VEYRON_V1_MIMPID; 468 469 #ifndef CONFIG_USER_ONLY 470 set_satp_mode_max_supported(cpu, VM_1_10_SV48); 471 #endif 472 } 473 474 static void rv128_base_cpu_init(Object *obj) 475 { 476 if (qemu_tcg_mttcg_enabled()) { 477 /* Missing 128-bit aligned atomics */ 478 error_report("128-bit RISC-V currently does not work with Multi " 479 "Threaded TCG. Please use: -accel tcg,thread=single"); 480 exit(EXIT_FAILURE); 481 } 482 CPURISCVState *env = &RISCV_CPU(obj)->env; 483 /* We set this in the realise function */ 484 set_misa(env, MXL_RV128, 0); 485 riscv_cpu_add_user_properties(obj); 486 /* Set latest version of privileged specification */ 487 env->priv_ver = PRIV_VERSION_LATEST; 488 #ifndef CONFIG_USER_ONLY 489 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 490 #endif 491 } 492 #else 493 static void rv32_base_cpu_init(Object *obj) 494 { 495 CPURISCVState *env = &RISCV_CPU(obj)->env; 496 /* We set this in the realise function */ 497 set_misa(env, MXL_RV32, 0); 498 riscv_cpu_add_user_properties(obj); 499 /* Set latest version of privileged specification */ 500 env->priv_ver = PRIV_VERSION_LATEST; 501 #ifndef CONFIG_USER_ONLY 502 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 503 #endif 504 } 505 506 static void rv32_sifive_u_cpu_init(Object *obj) 507 { 508 RISCVCPU *cpu = RISCV_CPU(obj); 509 CPURISCVState *env = &cpu->env; 510 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 511 env->priv_ver = PRIV_VERSION_1_10_0; 512 #ifndef CONFIG_USER_ONLY 513 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 514 #endif 515 516 /* inherited from parent obj via riscv_cpu_init() */ 517 cpu->cfg.ext_ifencei = true; 518 cpu->cfg.ext_icsr = true; 519 cpu->cfg.mmu = true; 520 cpu->cfg.pmp = true; 521 } 522 523 static void rv32_sifive_e_cpu_init(Object *obj) 524 { 525 CPURISCVState *env = &RISCV_CPU(obj)->env; 526 RISCVCPU *cpu = RISCV_CPU(obj); 527 528 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 529 env->priv_ver = PRIV_VERSION_1_10_0; 530 #ifndef CONFIG_USER_ONLY 531 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 532 #endif 533 534 /* inherited from parent obj via riscv_cpu_init() */ 535 cpu->cfg.ext_ifencei = true; 536 cpu->cfg.ext_icsr = true; 537 cpu->cfg.pmp = true; 538 } 539 540 static void rv32_ibex_cpu_init(Object *obj) 541 { 542 CPURISCVState *env = &RISCV_CPU(obj)->env; 543 RISCVCPU *cpu = RISCV_CPU(obj); 544 545 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 546 env->priv_ver = PRIV_VERSION_1_11_0; 547 #ifndef CONFIG_USER_ONLY 548 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 549 #endif 550 cpu->cfg.epmp = true; 551 552 /* inherited from parent obj via riscv_cpu_init() */ 553 cpu->cfg.ext_ifencei = true; 554 cpu->cfg.ext_icsr = true; 555 cpu->cfg.pmp = true; 556 } 557 558 static void rv32_imafcu_nommu_cpu_init(Object *obj) 559 { 560 CPURISCVState *env = &RISCV_CPU(obj)->env; 561 RISCVCPU *cpu = RISCV_CPU(obj); 562 563 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 564 env->priv_ver = PRIV_VERSION_1_10_0; 565 #ifndef CONFIG_USER_ONLY 566 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 567 #endif 568 569 /* inherited from parent obj via riscv_cpu_init() */ 570 cpu->cfg.ext_ifencei = true; 571 cpu->cfg.ext_icsr = true; 572 cpu->cfg.pmp = true; 573 } 574 #endif 575 576 #if defined(CONFIG_KVM) 577 static void riscv_host_cpu_init(Object *obj) 578 { 579 CPURISCVState *env = &RISCV_CPU(obj)->env; 580 #if defined(TARGET_RISCV32) 581 set_misa(env, MXL_RV32, 0); 582 #elif defined(TARGET_RISCV64) 583 set_misa(env, MXL_RV64, 0); 584 #endif 585 riscv_cpu_add_user_properties(obj); 586 } 587 #endif 588 589 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 590 { 591 ObjectClass *oc; 592 char *typename; 593 char **cpuname; 594 595 cpuname = g_strsplit(cpu_model, ",", 1); 596 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 597 oc = object_class_by_name(typename); 598 g_strfreev(cpuname); 599 g_free(typename); 600 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 601 object_class_is_abstract(oc)) { 602 return NULL; 603 } 604 return oc; 605 } 606 607 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 608 { 609 RISCVCPU *cpu = RISCV_CPU(cs); 610 CPURISCVState *env = &cpu->env; 611 int i; 612 613 #if !defined(CONFIG_USER_ONLY) 614 if (riscv_has_ext(env, RVH)) { 615 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); 616 } 617 #endif 618 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 619 #ifndef CONFIG_USER_ONLY 620 { 621 static const int dump_csrs[] = { 622 CSR_MHARTID, 623 CSR_MSTATUS, 624 CSR_MSTATUSH, 625 /* 626 * CSR_SSTATUS is intentionally omitted here as its value 627 * can be figured out by looking at CSR_MSTATUS 628 */ 629 CSR_HSTATUS, 630 CSR_VSSTATUS, 631 CSR_MIP, 632 CSR_MIE, 633 CSR_MIDELEG, 634 CSR_HIDELEG, 635 CSR_MEDELEG, 636 CSR_HEDELEG, 637 CSR_MTVEC, 638 CSR_STVEC, 639 CSR_VSTVEC, 640 CSR_MEPC, 641 CSR_SEPC, 642 CSR_VSEPC, 643 CSR_MCAUSE, 644 CSR_SCAUSE, 645 CSR_VSCAUSE, 646 CSR_MTVAL, 647 CSR_STVAL, 648 CSR_HTVAL, 649 CSR_MTVAL2, 650 CSR_MSCRATCH, 651 CSR_SSCRATCH, 652 CSR_SATP, 653 CSR_MMTE, 654 CSR_UPMBASE, 655 CSR_UPMMASK, 656 CSR_SPMBASE, 657 CSR_SPMMASK, 658 CSR_MPMBASE, 659 CSR_MPMMASK, 660 }; 661 662 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 663 int csrno = dump_csrs[i]; 664 target_ulong val = 0; 665 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 666 667 /* 668 * Rely on the smode, hmode, etc, predicates within csr.c 669 * to do the filtering of the registers that are present. 670 */ 671 if (res == RISCV_EXCP_NONE) { 672 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 673 csr_ops[csrno].name, val); 674 } 675 } 676 } 677 #endif 678 679 for (i = 0; i < 32; i++) { 680 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 681 riscv_int_regnames[i], env->gpr[i]); 682 if ((i & 3) == 3) { 683 qemu_fprintf(f, "\n"); 684 } 685 } 686 if (flags & CPU_DUMP_FPU) { 687 for (i = 0; i < 32; i++) { 688 qemu_fprintf(f, " %-8s %016" PRIx64, 689 riscv_fpr_regnames[i], env->fpr[i]); 690 if ((i & 3) == 3) { 691 qemu_fprintf(f, "\n"); 692 } 693 } 694 } 695 } 696 697 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 698 { 699 RISCVCPU *cpu = RISCV_CPU(cs); 700 CPURISCVState *env = &cpu->env; 701 702 if (env->xl == MXL_RV32) { 703 env->pc = (int32_t)value; 704 } else { 705 env->pc = value; 706 } 707 } 708 709 static vaddr riscv_cpu_get_pc(CPUState *cs) 710 { 711 RISCVCPU *cpu = RISCV_CPU(cs); 712 CPURISCVState *env = &cpu->env; 713 714 /* Match cpu_get_tb_cpu_state. */ 715 if (env->xl == MXL_RV32) { 716 return env->pc & UINT32_MAX; 717 } 718 return env->pc; 719 } 720 721 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 722 const TranslationBlock *tb) 723 { 724 RISCVCPU *cpu = RISCV_CPU(cs); 725 CPURISCVState *env = &cpu->env; 726 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 727 728 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 729 730 if (xl == MXL_RV32) { 731 env->pc = (int32_t) tb->pc; 732 } else { 733 env->pc = tb->pc; 734 } 735 } 736 737 static bool riscv_cpu_has_work(CPUState *cs) 738 { 739 #ifndef CONFIG_USER_ONLY 740 RISCVCPU *cpu = RISCV_CPU(cs); 741 CPURISCVState *env = &cpu->env; 742 /* 743 * Definition of the WFI instruction requires it to ignore the privilege 744 * mode and delegation registers, but respect individual enables 745 */ 746 return riscv_cpu_all_pending(env) != 0; 747 #else 748 return true; 749 #endif 750 } 751 752 static void riscv_restore_state_to_opc(CPUState *cs, 753 const TranslationBlock *tb, 754 const uint64_t *data) 755 { 756 RISCVCPU *cpu = RISCV_CPU(cs); 757 CPURISCVState *env = &cpu->env; 758 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 759 760 if (xl == MXL_RV32) { 761 env->pc = (int32_t)data[0]; 762 } else { 763 env->pc = data[0]; 764 } 765 env->bins = data[1]; 766 } 767 768 static void riscv_cpu_reset_hold(Object *obj) 769 { 770 #ifndef CONFIG_USER_ONLY 771 uint8_t iprio; 772 int i, irq, rdzero; 773 #endif 774 CPUState *cs = CPU(obj); 775 RISCVCPU *cpu = RISCV_CPU(cs); 776 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 777 CPURISCVState *env = &cpu->env; 778 779 if (mcc->parent_phases.hold) { 780 mcc->parent_phases.hold(obj); 781 } 782 #ifndef CONFIG_USER_ONLY 783 env->misa_mxl = env->misa_mxl_max; 784 env->priv = PRV_M; 785 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 786 if (env->misa_mxl > MXL_RV32) { 787 /* 788 * The reset status of SXL/UXL is undefined, but mstatus is WARL 789 * and we must ensure that the value after init is valid for read. 790 */ 791 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 792 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 793 if (riscv_has_ext(env, RVH)) { 794 env->vsstatus = set_field(env->vsstatus, 795 MSTATUS64_SXL, env->misa_mxl); 796 env->vsstatus = set_field(env->vsstatus, 797 MSTATUS64_UXL, env->misa_mxl); 798 env->mstatus_hs = set_field(env->mstatus_hs, 799 MSTATUS64_SXL, env->misa_mxl); 800 env->mstatus_hs = set_field(env->mstatus_hs, 801 MSTATUS64_UXL, env->misa_mxl); 802 } 803 } 804 env->mcause = 0; 805 env->miclaim = MIP_SGEIP; 806 env->pc = env->resetvec; 807 env->bins = 0; 808 env->two_stage_lookup = false; 809 810 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | 811 (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); 812 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | 813 (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); 814 815 /* Initialized default priorities of local interrupts. */ 816 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 817 iprio = riscv_cpu_default_priority(i); 818 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 819 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 820 env->hviprio[i] = 0; 821 } 822 i = 0; 823 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 824 if (!rdzero) { 825 env->hviprio[irq] = env->miprio[irq]; 826 } 827 i++; 828 } 829 /* mmte is supposed to have pm.current hardwired to 1 */ 830 env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); 831 #endif 832 env->xl = riscv_cpu_mxl(env); 833 riscv_cpu_update_mask(env); 834 cs->exception_index = RISCV_EXCP_NONE; 835 env->load_res = -1; 836 set_default_nan_mode(1, &env->fp_status); 837 838 #ifndef CONFIG_USER_ONLY 839 if (cpu->cfg.debug) { 840 riscv_trigger_init(env); 841 } 842 843 if (kvm_enabled()) { 844 kvm_riscv_reset_vcpu(cpu); 845 } 846 #endif 847 } 848 849 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 850 { 851 RISCVCPU *cpu = RISCV_CPU(s); 852 853 switch (riscv_cpu_mxl(&cpu->env)) { 854 case MXL_RV32: 855 info->print_insn = print_insn_riscv32; 856 break; 857 case MXL_RV64: 858 info->print_insn = print_insn_riscv64; 859 break; 860 case MXL_RV128: 861 info->print_insn = print_insn_riscv128; 862 break; 863 default: 864 g_assert_not_reached(); 865 } 866 } 867 868 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 869 Error **errp) 870 { 871 int vext_version = VEXT_VERSION_1_00_0; 872 873 if (!is_power_of_2(cfg->vlen)) { 874 error_setg(errp, "Vector extension VLEN must be power of 2"); 875 return; 876 } 877 if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { 878 error_setg(errp, 879 "Vector extension implementation only supports VLEN " 880 "in the range [128, %d]", RV_VLEN_MAX); 881 return; 882 } 883 if (!is_power_of_2(cfg->elen)) { 884 error_setg(errp, "Vector extension ELEN must be power of 2"); 885 return; 886 } 887 if (cfg->elen > 64 || cfg->elen < 8) { 888 error_setg(errp, 889 "Vector extension implementation only supports ELEN " 890 "in the range [8, 64]"); 891 return; 892 } 893 if (cfg->vext_spec) { 894 if (!g_strcmp0(cfg->vext_spec, "v1.0")) { 895 vext_version = VEXT_VERSION_1_00_0; 896 } else { 897 error_setg(errp, "Unsupported vector spec version '%s'", 898 cfg->vext_spec); 899 return; 900 } 901 } else { 902 qemu_log("vector version is not specified, " 903 "use the default value v1.0\n"); 904 } 905 env->vext_ver = vext_version; 906 } 907 908 static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) 909 { 910 CPURISCVState *env = &cpu->env; 911 int priv_version = -1; 912 913 if (cpu->cfg.priv_spec) { 914 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 915 priv_version = PRIV_VERSION_1_12_0; 916 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 917 priv_version = PRIV_VERSION_1_11_0; 918 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 919 priv_version = PRIV_VERSION_1_10_0; 920 } else { 921 error_setg(errp, 922 "Unsupported privilege spec version '%s'", 923 cpu->cfg.priv_spec); 924 return; 925 } 926 927 env->priv_ver = priv_version; 928 } 929 } 930 931 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 932 { 933 CPURISCVState *env = &cpu->env; 934 int i; 935 936 /* Force disable extensions if priv spec version does not match */ 937 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 938 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 939 (env->priv_ver < isa_edata_arr[i].min_version)) { 940 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 941 #ifndef CONFIG_USER_ONLY 942 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 943 " because privilege spec version does not match", 944 isa_edata_arr[i].name, env->mhartid); 945 #else 946 warn_report("disabling %s extension because " 947 "privilege spec version does not match", 948 isa_edata_arr[i].name); 949 #endif 950 } 951 } 952 } 953 954 static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) 955 { 956 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 957 CPUClass *cc = CPU_CLASS(mcc); 958 CPURISCVState *env = &cpu->env; 959 960 /* Validate that MISA_MXL is set properly. */ 961 switch (env->misa_mxl_max) { 962 #ifdef TARGET_RISCV64 963 case MXL_RV64: 964 case MXL_RV128: 965 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 966 break; 967 #endif 968 case MXL_RV32: 969 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 970 break; 971 default: 972 g_assert_not_reached(); 973 } 974 975 if (env->misa_mxl_max != env->misa_mxl) { 976 error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); 977 return; 978 } 979 } 980 981 /* 982 * Check consistency between chosen extensions while setting 983 * cpu->cfg accordingly. 984 */ 985 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 986 { 987 CPURISCVState *env = &cpu->env; 988 Error *local_err = NULL; 989 990 /* Do some ISA extension error checking */ 991 if (riscv_has_ext(env, RVG) && 992 !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && 993 riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && 994 riscv_has_ext(env, RVD) && 995 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 996 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 997 cpu->cfg.ext_icsr = true; 998 cpu->cfg.ext_ifencei = true; 999 1000 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; 1001 env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD; 1002 } 1003 1004 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 1005 error_setg(errp, 1006 "I and E extensions are incompatible"); 1007 return; 1008 } 1009 1010 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 1011 error_setg(errp, 1012 "Either I or E extension must be set"); 1013 return; 1014 } 1015 1016 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 1017 error_setg(errp, 1018 "Setting S extension without U extension is illegal"); 1019 return; 1020 } 1021 1022 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 1023 error_setg(errp, 1024 "H depends on an I base integer ISA with 32 x registers"); 1025 return; 1026 } 1027 1028 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 1029 error_setg(errp, "H extension implicitly requires S-mode"); 1030 return; 1031 } 1032 1033 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { 1034 error_setg(errp, "F extension requires Zicsr"); 1035 return; 1036 } 1037 1038 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 1039 error_setg(errp, "Zawrs extension requires A extension"); 1040 return; 1041 } 1042 1043 if (cpu->cfg.ext_zfh) { 1044 cpu->cfg.ext_zfhmin = true; 1045 } 1046 1047 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 1048 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 1049 return; 1050 } 1051 1052 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 1053 error_setg(errp, "D extension requires F extension"); 1054 return; 1055 } 1056 1057 if (riscv_has_ext(env, RVV)) { 1058 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 1059 if (local_err != NULL) { 1060 error_propagate(errp, local_err); 1061 return; 1062 } 1063 1064 /* The V vector extension depends on the Zve64d extension */ 1065 cpu->cfg.ext_zve64d = true; 1066 } 1067 1068 /* The Zve64d extension depends on the Zve64f extension */ 1069 if (cpu->cfg.ext_zve64d) { 1070 cpu->cfg.ext_zve64f = true; 1071 } 1072 1073 /* The Zve64f extension depends on the Zve32f extension */ 1074 if (cpu->cfg.ext_zve64f) { 1075 cpu->cfg.ext_zve32f = true; 1076 } 1077 1078 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 1079 error_setg(errp, "Zve64d/V extensions require D extension"); 1080 return; 1081 } 1082 1083 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 1084 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 1085 return; 1086 } 1087 1088 if (cpu->cfg.ext_zvfh) { 1089 cpu->cfg.ext_zvfhmin = true; 1090 } 1091 1092 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 1093 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 1094 return; 1095 } 1096 1097 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 1098 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 1099 return; 1100 } 1101 1102 /* Set the ISA extensions, checks should have happened above */ 1103 if (cpu->cfg.ext_zhinx) { 1104 cpu->cfg.ext_zhinxmin = true; 1105 } 1106 1107 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 1108 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 1109 return; 1110 } 1111 1112 if (cpu->cfg.ext_zfinx) { 1113 if (!cpu->cfg.ext_icsr) { 1114 error_setg(errp, "Zfinx extension requires Zicsr"); 1115 return; 1116 } 1117 if (riscv_has_ext(env, RVF)) { 1118 error_setg(errp, 1119 "Zfinx cannot be supported together with F extension"); 1120 return; 1121 } 1122 } 1123 1124 if (cpu->cfg.ext_zce) { 1125 cpu->cfg.ext_zca = true; 1126 cpu->cfg.ext_zcb = true; 1127 cpu->cfg.ext_zcmp = true; 1128 cpu->cfg.ext_zcmt = true; 1129 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 1130 cpu->cfg.ext_zcf = true; 1131 } 1132 } 1133 1134 if (riscv_has_ext(env, RVC)) { 1135 cpu->cfg.ext_zca = true; 1136 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 1137 cpu->cfg.ext_zcf = true; 1138 } 1139 if (riscv_has_ext(env, RVD)) { 1140 cpu->cfg.ext_zcd = true; 1141 } 1142 } 1143 1144 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 1145 error_setg(errp, "Zcf extension is only relevant to RV32"); 1146 return; 1147 } 1148 1149 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 1150 error_setg(errp, "Zcf extension requires F extension"); 1151 return; 1152 } 1153 1154 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 1155 error_setg(errp, "Zcd extension requires D extension"); 1156 return; 1157 } 1158 1159 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 1160 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 1161 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 1162 "extension"); 1163 return; 1164 } 1165 1166 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 1167 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 1168 "Zcd extension"); 1169 return; 1170 } 1171 1172 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { 1173 error_setg(errp, "Zcmt extension requires Zicsr extension"); 1174 return; 1175 } 1176 1177 if (cpu->cfg.ext_zk) { 1178 cpu->cfg.ext_zkn = true; 1179 cpu->cfg.ext_zkr = true; 1180 cpu->cfg.ext_zkt = true; 1181 } 1182 1183 if (cpu->cfg.ext_zkn) { 1184 cpu->cfg.ext_zbkb = true; 1185 cpu->cfg.ext_zbkc = true; 1186 cpu->cfg.ext_zbkx = true; 1187 cpu->cfg.ext_zkne = true; 1188 cpu->cfg.ext_zknd = true; 1189 cpu->cfg.ext_zknh = true; 1190 } 1191 1192 if (cpu->cfg.ext_zks) { 1193 cpu->cfg.ext_zbkb = true; 1194 cpu->cfg.ext_zbkc = true; 1195 cpu->cfg.ext_zbkx = true; 1196 cpu->cfg.ext_zksed = true; 1197 cpu->cfg.ext_zksh = true; 1198 } 1199 1200 /* 1201 * Disable isa extensions based on priv spec after we 1202 * validated and set everything we need. 1203 */ 1204 riscv_cpu_disable_priv_spec_isa_exts(cpu); 1205 } 1206 1207 #ifndef CONFIG_USER_ONLY 1208 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) 1209 { 1210 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 1211 uint8_t satp_mode_map_max; 1212 uint8_t satp_mode_supported_max = 1213 satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 1214 1215 if (cpu->cfg.satp_mode.map == 0) { 1216 if (cpu->cfg.satp_mode.init == 0) { 1217 /* If unset by the user, we fallback to the default satp mode. */ 1218 set_satp_mode_default_map(cpu); 1219 } else { 1220 /* 1221 * Find the lowest level that was disabled and then enable the 1222 * first valid level below which can be found in 1223 * valid_vm_1_10_32/64. 1224 */ 1225 for (int i = 1; i < 16; ++i) { 1226 if ((cpu->cfg.satp_mode.init & (1 << i)) && 1227 (cpu->cfg.satp_mode.supported & (1 << i))) { 1228 for (int j = i - 1; j >= 0; --j) { 1229 if (cpu->cfg.satp_mode.supported & (1 << j)) { 1230 cpu->cfg.satp_mode.map |= (1 << j); 1231 break; 1232 } 1233 } 1234 break; 1235 } 1236 } 1237 } 1238 } 1239 1240 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 1241 1242 /* Make sure the user asked for a supported configuration (HW and qemu) */ 1243 if (satp_mode_map_max > satp_mode_supported_max) { 1244 error_setg(errp, "satp_mode %s is higher than hw max capability %s", 1245 satp_mode_str(satp_mode_map_max, rv32), 1246 satp_mode_str(satp_mode_supported_max, rv32)); 1247 return; 1248 } 1249 1250 /* 1251 * Make sure the user did not ask for an invalid configuration as per 1252 * the specification. 1253 */ 1254 if (!rv32) { 1255 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1256 if (!(cpu->cfg.satp_mode.map & (1 << i)) && 1257 (cpu->cfg.satp_mode.init & (1 << i)) && 1258 (cpu->cfg.satp_mode.supported & (1 << i))) { 1259 error_setg(errp, "cannot disable %s satp mode if %s " 1260 "is enabled", satp_mode_str(i, false), 1261 satp_mode_str(satp_mode_map_max, false)); 1262 return; 1263 } 1264 } 1265 } 1266 1267 /* Finally expand the map so that all valid modes are set */ 1268 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1269 if (cpu->cfg.satp_mode.supported & (1 << i)) { 1270 cpu->cfg.satp_mode.map |= (1 << i); 1271 } 1272 } 1273 } 1274 #endif 1275 1276 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1277 { 1278 #ifndef CONFIG_USER_ONLY 1279 Error *local_err = NULL; 1280 1281 riscv_cpu_satp_mode_finalize(cpu, &local_err); 1282 if (local_err != NULL) { 1283 error_propagate(errp, local_err); 1284 return; 1285 } 1286 #endif 1287 } 1288 1289 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 1290 { 1291 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 1292 error_setg(errp, "H extension requires priv spec 1.12.0"); 1293 return; 1294 } 1295 } 1296 1297 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 1298 { 1299 CPUState *cs = CPU(dev); 1300 RISCVCPU *cpu = RISCV_CPU(dev); 1301 CPURISCVState *env = &cpu->env; 1302 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 1303 Error *local_err = NULL; 1304 1305 cpu_exec_realizefn(cs, &local_err); 1306 if (local_err != NULL) { 1307 error_propagate(errp, local_err); 1308 return; 1309 } 1310 1311 riscv_cpu_validate_misa_mxl(cpu, &local_err); 1312 if (local_err != NULL) { 1313 error_propagate(errp, local_err); 1314 return; 1315 } 1316 1317 riscv_cpu_validate_priv_spec(cpu, &local_err); 1318 if (local_err != NULL) { 1319 error_propagate(errp, local_err); 1320 return; 1321 } 1322 1323 riscv_cpu_validate_misa_priv(env, &local_err); 1324 if (local_err != NULL) { 1325 error_propagate(errp, local_err); 1326 return; 1327 } 1328 1329 if (cpu->cfg.epmp && !cpu->cfg.pmp) { 1330 /* 1331 * Enhanced PMP should only be available 1332 * on harts with PMP support 1333 */ 1334 error_setg(errp, "Invalid configuration: EPMP requires PMP support"); 1335 return; 1336 } 1337 1338 riscv_cpu_validate_set_extensions(cpu, &local_err); 1339 if (local_err != NULL) { 1340 error_propagate(errp, local_err); 1341 return; 1342 } 1343 1344 #ifndef CONFIG_USER_ONLY 1345 if (cpu->cfg.ext_sstc) { 1346 riscv_timer_init(cpu); 1347 } 1348 1349 if (cpu->cfg.pmu_num) { 1350 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 1351 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1352 riscv_pmu_timer_cb, cpu); 1353 } 1354 } 1355 #endif 1356 1357 riscv_cpu_finalize_features(cpu, &local_err); 1358 if (local_err != NULL) { 1359 error_propagate(errp, local_err); 1360 return; 1361 } 1362 1363 riscv_cpu_register_gdb_regs_for_features(cs); 1364 1365 qemu_init_vcpu(cs); 1366 cpu_reset(cs); 1367 1368 mcc->parent_realize(dev, errp); 1369 } 1370 1371 #ifndef CONFIG_USER_ONLY 1372 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, 1373 void *opaque, Error **errp) 1374 { 1375 RISCVSATPMap *satp_map = opaque; 1376 uint8_t satp = satp_mode_from_str(name); 1377 bool value; 1378 1379 value = satp_map->map & (1 << satp); 1380 1381 visit_type_bool(v, name, &value, errp); 1382 } 1383 1384 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, 1385 void *opaque, Error **errp) 1386 { 1387 RISCVSATPMap *satp_map = opaque; 1388 uint8_t satp = satp_mode_from_str(name); 1389 bool value; 1390 1391 if (!visit_type_bool(v, name, &value, errp)) { 1392 return; 1393 } 1394 1395 satp_map->map = deposit32(satp_map->map, satp, 1, value); 1396 satp_map->init |= 1 << satp; 1397 } 1398 1399 static void riscv_add_satp_mode_properties(Object *obj) 1400 { 1401 RISCVCPU *cpu = RISCV_CPU(obj); 1402 1403 if (cpu->env.misa_mxl == MXL_RV32) { 1404 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, 1405 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1406 } else { 1407 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, 1408 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1409 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, 1410 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1411 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, 1412 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1413 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, 1414 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1415 } 1416 } 1417 1418 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1419 { 1420 RISCVCPU *cpu = RISCV_CPU(opaque); 1421 CPURISCVState *env = &cpu->env; 1422 1423 if (irq < IRQ_LOCAL_MAX) { 1424 switch (irq) { 1425 case IRQ_U_SOFT: 1426 case IRQ_S_SOFT: 1427 case IRQ_VS_SOFT: 1428 case IRQ_M_SOFT: 1429 case IRQ_U_TIMER: 1430 case IRQ_S_TIMER: 1431 case IRQ_VS_TIMER: 1432 case IRQ_M_TIMER: 1433 case IRQ_U_EXT: 1434 case IRQ_VS_EXT: 1435 case IRQ_M_EXT: 1436 if (kvm_enabled()) { 1437 kvm_riscv_set_irq(cpu, irq, level); 1438 } else { 1439 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); 1440 } 1441 break; 1442 case IRQ_S_EXT: 1443 if (kvm_enabled()) { 1444 kvm_riscv_set_irq(cpu, irq, level); 1445 } else { 1446 env->external_seip = level; 1447 riscv_cpu_update_mip(env, 1 << irq, 1448 BOOL_TO_MASK(level | env->software_seip)); 1449 } 1450 break; 1451 default: 1452 g_assert_not_reached(); 1453 } 1454 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1455 /* Require H-extension for handling guest local interrupts */ 1456 if (!riscv_has_ext(env, RVH)) { 1457 g_assert_not_reached(); 1458 } 1459 1460 /* Compute bit position in HGEIP CSR */ 1461 irq = irq - IRQ_LOCAL_MAX + 1; 1462 if (env->geilen < irq) { 1463 g_assert_not_reached(); 1464 } 1465 1466 /* Update HGEIP CSR */ 1467 env->hgeip &= ~((target_ulong)1 << irq); 1468 if (level) { 1469 env->hgeip |= (target_ulong)1 << irq; 1470 } 1471 1472 /* Update mip.SGEIP bit */ 1473 riscv_cpu_update_mip(env, MIP_SGEIP, 1474 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1475 } else { 1476 g_assert_not_reached(); 1477 } 1478 } 1479 #endif /* CONFIG_USER_ONLY */ 1480 1481 static void riscv_cpu_init(Object *obj) 1482 { 1483 RISCVCPU *cpu = RISCV_CPU(obj); 1484 1485 cpu_set_cpustate_pointers(cpu); 1486 1487 #ifndef CONFIG_USER_ONLY 1488 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1489 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1490 #endif /* CONFIG_USER_ONLY */ 1491 } 1492 1493 typedef struct RISCVCPUMisaExtConfig { 1494 const char *name; 1495 const char *description; 1496 target_ulong misa_bit; 1497 bool enabled; 1498 } RISCVCPUMisaExtConfig; 1499 1500 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1501 void *opaque, Error **errp) 1502 { 1503 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1504 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1505 RISCVCPU *cpu = RISCV_CPU(obj); 1506 CPURISCVState *env = &cpu->env; 1507 bool value; 1508 1509 if (!visit_type_bool(v, name, &value, errp)) { 1510 return; 1511 } 1512 1513 if (value) { 1514 env->misa_ext |= misa_bit; 1515 env->misa_ext_mask |= misa_bit; 1516 } else { 1517 env->misa_ext &= ~misa_bit; 1518 env->misa_ext_mask &= ~misa_bit; 1519 } 1520 } 1521 1522 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1523 void *opaque, Error **errp) 1524 { 1525 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1526 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1527 RISCVCPU *cpu = RISCV_CPU(obj); 1528 CPURISCVState *env = &cpu->env; 1529 bool value; 1530 1531 value = env->misa_ext & misa_bit; 1532 1533 visit_type_bool(v, name, &value, errp); 1534 } 1535 1536 static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1537 {.name = "a", .description = "Atomic instructions", 1538 .misa_bit = RVA, .enabled = true}, 1539 {.name = "c", .description = "Compressed instructions", 1540 .misa_bit = RVC, .enabled = true}, 1541 {.name = "d", .description = "Double-precision float point", 1542 .misa_bit = RVD, .enabled = true}, 1543 {.name = "f", .description = "Single-precision float point", 1544 .misa_bit = RVF, .enabled = true}, 1545 {.name = "i", .description = "Base integer instruction set", 1546 .misa_bit = RVI, .enabled = true}, 1547 {.name = "e", .description = "Base integer instruction set (embedded)", 1548 .misa_bit = RVE, .enabled = false}, 1549 {.name = "m", .description = "Integer multiplication and division", 1550 .misa_bit = RVM, .enabled = true}, 1551 {.name = "s", .description = "Supervisor-level instructions", 1552 .misa_bit = RVS, .enabled = true}, 1553 {.name = "u", .description = "User-level instructions", 1554 .misa_bit = RVU, .enabled = true}, 1555 {.name = "h", .description = "Hypervisor", 1556 .misa_bit = RVH, .enabled = true}, 1557 {.name = "x-j", .description = "Dynamic translated languages", 1558 .misa_bit = RVJ, .enabled = false}, 1559 {.name = "v", .description = "Vector operations", 1560 .misa_bit = RVV, .enabled = false}, 1561 {.name = "g", .description = "General purpose (IMAFD_Zicsr_Zifencei)", 1562 .misa_bit = RVG, .enabled = false}, 1563 }; 1564 1565 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1566 { 1567 int i; 1568 1569 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1570 const RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1571 1572 object_property_add(cpu_obj, misa_cfg->name, "bool", 1573 cpu_get_misa_ext_cfg, 1574 cpu_set_misa_ext_cfg, 1575 NULL, (void *)misa_cfg); 1576 object_property_set_description(cpu_obj, misa_cfg->name, 1577 misa_cfg->description); 1578 object_property_set_bool(cpu_obj, misa_cfg->name, 1579 misa_cfg->enabled, NULL); 1580 } 1581 } 1582 1583 static Property riscv_cpu_extensions[] = { 1584 /* Defaults for standard extensions */ 1585 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1586 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1587 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1588 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1589 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1590 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1591 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1592 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1593 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1594 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1595 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), 1596 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1597 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1598 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1599 1600 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1601 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1602 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1603 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1604 1605 DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), 1606 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), 1607 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1608 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1609 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1610 1611 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1612 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1613 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1614 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1615 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1616 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1617 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1618 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1619 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1620 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1621 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1622 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1623 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1624 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1625 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1626 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1627 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1628 1629 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1630 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1631 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1632 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1633 1634 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), 1635 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), 1636 DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), 1637 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), 1638 1639 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1640 1641 DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false), 1642 DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false), 1643 DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false), 1644 DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false), 1645 DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), 1646 DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), 1647 DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), 1648 1649 /* Vendor-specific custom extensions */ 1650 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1651 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1652 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1653 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1654 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1655 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1656 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1657 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1658 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1659 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1660 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1661 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1662 1663 /* These are experimental so mark with 'x-' */ 1664 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), 1665 1666 /* ePMP 0.9.3 */ 1667 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1668 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1669 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1670 1671 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), 1672 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), 1673 1674 DEFINE_PROP_END_OF_LIST(), 1675 }; 1676 1677 /* 1678 * Add CPU properties with user-facing flags. 1679 * 1680 * This will overwrite existing env->misa_ext values with the 1681 * defaults set via riscv_cpu_add_misa_properties(). 1682 */ 1683 static void riscv_cpu_add_user_properties(Object *obj) 1684 { 1685 Property *prop; 1686 DeviceState *dev = DEVICE(obj); 1687 1688 riscv_cpu_add_misa_properties(obj); 1689 1690 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1691 qdev_property_add_static(dev, prop); 1692 } 1693 1694 #ifndef CONFIG_USER_ONLY 1695 riscv_add_satp_mode_properties(obj); 1696 #endif 1697 } 1698 1699 static Property riscv_cpu_properties[] = { 1700 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1701 1702 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1703 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1704 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1705 1706 #ifndef CONFIG_USER_ONLY 1707 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1708 #endif 1709 1710 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1711 1712 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1713 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1714 1715 /* 1716 * write_misa() is marked as experimental for now so mark 1717 * it with -x and default to 'false'. 1718 */ 1719 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1720 DEFINE_PROP_END_OF_LIST(), 1721 }; 1722 1723 static gchar *riscv_gdb_arch_name(CPUState *cs) 1724 { 1725 RISCVCPU *cpu = RISCV_CPU(cs); 1726 CPURISCVState *env = &cpu->env; 1727 1728 switch (riscv_cpu_mxl(env)) { 1729 case MXL_RV32: 1730 return g_strdup("riscv:rv32"); 1731 case MXL_RV64: 1732 case MXL_RV128: 1733 return g_strdup("riscv:rv64"); 1734 default: 1735 g_assert_not_reached(); 1736 } 1737 } 1738 1739 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1740 { 1741 RISCVCPU *cpu = RISCV_CPU(cs); 1742 1743 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1744 return cpu->dyn_csr_xml; 1745 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1746 return cpu->dyn_vreg_xml; 1747 } 1748 1749 return NULL; 1750 } 1751 1752 #ifndef CONFIG_USER_ONLY 1753 static int64_t riscv_get_arch_id(CPUState *cs) 1754 { 1755 RISCVCPU *cpu = RISCV_CPU(cs); 1756 1757 return cpu->env.mhartid; 1758 } 1759 1760 #include "hw/core/sysemu-cpu-ops.h" 1761 1762 static const struct SysemuCPUOps riscv_sysemu_ops = { 1763 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1764 .write_elf64_note = riscv_cpu_write_elf64_note, 1765 .write_elf32_note = riscv_cpu_write_elf32_note, 1766 .legacy_vmsd = &vmstate_riscv_cpu, 1767 }; 1768 #endif 1769 1770 #include "hw/core/tcg-cpu-ops.h" 1771 1772 static const struct TCGCPUOps riscv_tcg_ops = { 1773 .initialize = riscv_translate_init, 1774 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1775 .restore_state_to_opc = riscv_restore_state_to_opc, 1776 1777 #ifndef CONFIG_USER_ONLY 1778 .tlb_fill = riscv_cpu_tlb_fill, 1779 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1780 .do_interrupt = riscv_cpu_do_interrupt, 1781 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1782 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1783 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1784 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1785 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1786 #endif /* !CONFIG_USER_ONLY */ 1787 }; 1788 1789 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1790 { 1791 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1792 CPUClass *cc = CPU_CLASS(c); 1793 DeviceClass *dc = DEVICE_CLASS(c); 1794 ResettableClass *rc = RESETTABLE_CLASS(c); 1795 1796 device_class_set_parent_realize(dc, riscv_cpu_realize, 1797 &mcc->parent_realize); 1798 1799 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1800 &mcc->parent_phases); 1801 1802 cc->class_by_name = riscv_cpu_class_by_name; 1803 cc->has_work = riscv_cpu_has_work; 1804 cc->dump_state = riscv_cpu_dump_state; 1805 cc->set_pc = riscv_cpu_set_pc; 1806 cc->get_pc = riscv_cpu_get_pc; 1807 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1808 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1809 cc->gdb_num_core_regs = 33; 1810 cc->gdb_stop_before_watchpoint = true; 1811 cc->disas_set_info = riscv_cpu_disas_set_info; 1812 #ifndef CONFIG_USER_ONLY 1813 cc->sysemu_ops = &riscv_sysemu_ops; 1814 cc->get_arch_id = riscv_get_arch_id; 1815 #endif 1816 cc->gdb_arch_name = riscv_gdb_arch_name; 1817 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1818 cc->tcg_ops = &riscv_tcg_ops; 1819 1820 device_class_set_props(dc, riscv_cpu_properties); 1821 } 1822 1823 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, 1824 int max_str_len) 1825 { 1826 char *old = *isa_str; 1827 char *new = *isa_str; 1828 int i; 1829 1830 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1831 if (cpu->env.priv_ver >= isa_edata_arr[i].min_version && 1832 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1833 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1834 g_free(old); 1835 old = new; 1836 } 1837 } 1838 1839 *isa_str = new; 1840 } 1841 1842 char *riscv_isa_string(RISCVCPU *cpu) 1843 { 1844 int i; 1845 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1846 char *isa_str = g_new(char, maxlen); 1847 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1848 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1849 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1850 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1851 } 1852 } 1853 *p = '\0'; 1854 if (!cpu->cfg.short_isa_string) { 1855 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1856 } 1857 return isa_str; 1858 } 1859 1860 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1861 { 1862 ObjectClass *class_a = (ObjectClass *)a; 1863 ObjectClass *class_b = (ObjectClass *)b; 1864 const char *name_a, *name_b; 1865 1866 name_a = object_class_get_name(class_a); 1867 name_b = object_class_get_name(class_b); 1868 return strcmp(name_a, name_b); 1869 } 1870 1871 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1872 { 1873 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1874 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1875 1876 qemu_printf("%.*s\n", len, typename); 1877 } 1878 1879 void riscv_cpu_list(void) 1880 { 1881 GSList *list; 1882 1883 list = object_class_get_list(TYPE_RISCV_CPU, false); 1884 list = g_slist_sort(list, riscv_cpu_list_compare); 1885 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1886 g_slist_free(list); 1887 } 1888 1889 #define DEFINE_CPU(type_name, initfn) \ 1890 { \ 1891 .name = type_name, \ 1892 .parent = TYPE_RISCV_CPU, \ 1893 .instance_init = initfn \ 1894 } 1895 1896 #define DEFINE_DYNAMIC_CPU(type_name, initfn) \ 1897 { \ 1898 .name = type_name, \ 1899 .parent = TYPE_RISCV_DYNAMIC_CPU, \ 1900 .instance_init = initfn \ 1901 } 1902 1903 static const TypeInfo riscv_cpu_type_infos[] = { 1904 { 1905 .name = TYPE_RISCV_CPU, 1906 .parent = TYPE_CPU, 1907 .instance_size = sizeof(RISCVCPU), 1908 .instance_align = __alignof__(RISCVCPU), 1909 .instance_init = riscv_cpu_init, 1910 .abstract = true, 1911 .class_size = sizeof(RISCVCPUClass), 1912 .class_init = riscv_cpu_class_init, 1913 }, 1914 { 1915 .name = TYPE_RISCV_DYNAMIC_CPU, 1916 .parent = TYPE_RISCV_CPU, 1917 .abstract = true, 1918 }, 1919 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1920 #if defined(CONFIG_KVM) 1921 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1922 #endif 1923 #if defined(TARGET_RISCV32) 1924 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1925 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1926 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1927 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1928 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1929 #elif defined(TARGET_RISCV64) 1930 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1931 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1932 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1933 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1934 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1935 DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), 1936 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1937 #endif 1938 }; 1939 1940 DEFINE_TYPES(riscv_cpu_type_infos) 1941