1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "internals.h" 26 #include "exec/exec-all.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "hw/qdev-properties.h" 30 #include "migration/vmstate.h" 31 #include "fpu/softfloat-helpers.h" 32 33 /* RISC-V CPU definitions */ 34 35 static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; 36 37 const char * const riscv_int_regnames[] = { 38 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 39 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 40 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 41 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 42 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 43 }; 44 45 const char * const riscv_int_regnamesh[] = { 46 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 47 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 48 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 49 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 50 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 51 "x30h/t5h", "x31h/t6h" 52 }; 53 54 const char * const riscv_fpr_regnames[] = { 55 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 56 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 57 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 58 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 59 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 60 "f30/ft10", "f31/ft11" 61 }; 62 63 static const char * const riscv_excp_names[] = { 64 "misaligned_fetch", 65 "fault_fetch", 66 "illegal_instruction", 67 "breakpoint", 68 "misaligned_load", 69 "fault_load", 70 "misaligned_store", 71 "fault_store", 72 "user_ecall", 73 "supervisor_ecall", 74 "hypervisor_ecall", 75 "machine_ecall", 76 "exec_page_fault", 77 "load_page_fault", 78 "reserved", 79 "store_page_fault", 80 "reserved", 81 "reserved", 82 "reserved", 83 "reserved", 84 "guest_exec_page_fault", 85 "guest_load_page_fault", 86 "reserved", 87 "guest_store_page_fault", 88 }; 89 90 static const char * const riscv_intr_names[] = { 91 "u_software", 92 "s_software", 93 "vs_software", 94 "m_software", 95 "u_timer", 96 "s_timer", 97 "vs_timer", 98 "m_timer", 99 "u_external", 100 "s_external", 101 "vs_external", 102 "m_external", 103 "reserved", 104 "reserved", 105 "reserved", 106 "reserved" 107 }; 108 109 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 110 { 111 if (async) { 112 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 113 riscv_intr_names[cause] : "(unknown)"; 114 } else { 115 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 116 riscv_excp_names[cause] : "(unknown)"; 117 } 118 } 119 120 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 121 { 122 env->misa_mxl_max = env->misa_mxl = mxl; 123 env->misa_ext_mask = env->misa_ext = ext; 124 } 125 126 static void set_priv_version(CPURISCVState *env, int priv_ver) 127 { 128 env->priv_ver = priv_ver; 129 } 130 131 static void set_vext_version(CPURISCVState *env, int vext_ver) 132 { 133 env->vext_ver = vext_ver; 134 } 135 136 static void set_feature(CPURISCVState *env, int feature) 137 { 138 env->features |= (1ULL << feature); 139 } 140 141 static void set_resetvec(CPURISCVState *env, target_ulong resetvec) 142 { 143 #ifndef CONFIG_USER_ONLY 144 env->resetvec = resetvec; 145 #endif 146 } 147 148 static void riscv_any_cpu_init(Object *obj) 149 { 150 CPURISCVState *env = &RISCV_CPU(obj)->env; 151 #if defined(TARGET_RISCV32) 152 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 153 #elif defined(TARGET_RISCV64) 154 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 155 #endif 156 set_priv_version(env, PRIV_VERSION_1_11_0); 157 } 158 159 #if defined(TARGET_RISCV64) 160 static void rv64_base_cpu_init(Object *obj) 161 { 162 CPURISCVState *env = &RISCV_CPU(obj)->env; 163 /* We set this in the realise function */ 164 set_misa(env, MXL_RV64, 0); 165 } 166 167 static void rv64_sifive_u_cpu_init(Object *obj) 168 { 169 CPURISCVState *env = &RISCV_CPU(obj)->env; 170 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 171 set_priv_version(env, PRIV_VERSION_1_10_0); 172 } 173 174 static void rv64_sifive_e_cpu_init(Object *obj) 175 { 176 CPURISCVState *env = &RISCV_CPU(obj)->env; 177 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 178 set_priv_version(env, PRIV_VERSION_1_10_0); 179 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 180 } 181 #else 182 static void rv32_base_cpu_init(Object *obj) 183 { 184 CPURISCVState *env = &RISCV_CPU(obj)->env; 185 /* We set this in the realise function */ 186 set_misa(env, MXL_RV32, 0); 187 } 188 189 static void rv32_sifive_u_cpu_init(Object *obj) 190 { 191 CPURISCVState *env = &RISCV_CPU(obj)->env; 192 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 193 set_priv_version(env, PRIV_VERSION_1_10_0); 194 } 195 196 static void rv32_sifive_e_cpu_init(Object *obj) 197 { 198 CPURISCVState *env = &RISCV_CPU(obj)->env; 199 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 200 set_priv_version(env, PRIV_VERSION_1_10_0); 201 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 202 } 203 204 static void rv32_ibex_cpu_init(Object *obj) 205 { 206 CPURISCVState *env = &RISCV_CPU(obj)->env; 207 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 208 set_priv_version(env, PRIV_VERSION_1_10_0); 209 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 210 qdev_prop_set_bit(DEVICE(obj), "x-epmp", true); 211 } 212 213 static void rv32_imafcu_nommu_cpu_init(Object *obj) 214 { 215 CPURISCVState *env = &RISCV_CPU(obj)->env; 216 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 217 set_priv_version(env, PRIV_VERSION_1_10_0); 218 set_resetvec(env, DEFAULT_RSTVEC); 219 qdev_prop_set_bit(DEVICE(obj), "mmu", false); 220 } 221 #endif 222 223 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 224 { 225 ObjectClass *oc; 226 char *typename; 227 char **cpuname; 228 229 cpuname = g_strsplit(cpu_model, ",", 1); 230 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 231 oc = object_class_by_name(typename); 232 g_strfreev(cpuname); 233 g_free(typename); 234 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 235 object_class_is_abstract(oc)) { 236 return NULL; 237 } 238 return oc; 239 } 240 241 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 242 { 243 RISCVCPU *cpu = RISCV_CPU(cs); 244 CPURISCVState *env = &cpu->env; 245 int i; 246 247 #if !defined(CONFIG_USER_ONLY) 248 if (riscv_has_ext(env, RVH)) { 249 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 250 } 251 #endif 252 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 253 #ifndef CONFIG_USER_ONLY 254 { 255 static const int dump_csrs[] = { 256 CSR_MHARTID, 257 CSR_MSTATUS, 258 CSR_MSTATUSH, 259 CSR_HSTATUS, 260 CSR_VSSTATUS, 261 CSR_MIP, 262 CSR_MIE, 263 CSR_MIDELEG, 264 CSR_HIDELEG, 265 CSR_MEDELEG, 266 CSR_HEDELEG, 267 CSR_MTVEC, 268 CSR_STVEC, 269 CSR_VSTVEC, 270 CSR_MEPC, 271 CSR_SEPC, 272 CSR_VSEPC, 273 CSR_MCAUSE, 274 CSR_SCAUSE, 275 CSR_VSCAUSE, 276 CSR_MTVAL, 277 CSR_STVAL, 278 CSR_HTVAL, 279 CSR_MTVAL2, 280 CSR_MSCRATCH, 281 CSR_SSCRATCH, 282 CSR_SATP, 283 CSR_MMTE, 284 CSR_UPMBASE, 285 CSR_UPMMASK, 286 CSR_SPMBASE, 287 CSR_SPMMASK, 288 CSR_MPMBASE, 289 CSR_MPMMASK, 290 }; 291 292 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 293 int csrno = dump_csrs[i]; 294 target_ulong val = 0; 295 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 296 297 /* 298 * Rely on the smode, hmode, etc, predicates within csr.c 299 * to do the filtering of the registers that are present. 300 */ 301 if (res == RISCV_EXCP_NONE) { 302 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 303 csr_ops[csrno].name, val); 304 } 305 } 306 } 307 #endif 308 309 for (i = 0; i < 32; i++) { 310 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 311 riscv_int_regnames[i], env->gpr[i]); 312 if ((i & 3) == 3) { 313 qemu_fprintf(f, "\n"); 314 } 315 } 316 if (flags & CPU_DUMP_FPU) { 317 for (i = 0; i < 32; i++) { 318 qemu_fprintf(f, " %-8s %016" PRIx64, 319 riscv_fpr_regnames[i], env->fpr[i]); 320 if ((i & 3) == 3) { 321 qemu_fprintf(f, "\n"); 322 } 323 } 324 } 325 } 326 327 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 328 { 329 RISCVCPU *cpu = RISCV_CPU(cs); 330 CPURISCVState *env = &cpu->env; 331 env->pc = value; 332 } 333 334 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 335 const TranslationBlock *tb) 336 { 337 RISCVCPU *cpu = RISCV_CPU(cs); 338 CPURISCVState *env = &cpu->env; 339 env->pc = tb->pc; 340 } 341 342 static bool riscv_cpu_has_work(CPUState *cs) 343 { 344 #ifndef CONFIG_USER_ONLY 345 RISCVCPU *cpu = RISCV_CPU(cs); 346 CPURISCVState *env = &cpu->env; 347 /* 348 * Definition of the WFI instruction requires it to ignore the privilege 349 * mode and delegation registers, but respect individual enables 350 */ 351 return (env->mip & env->mie) != 0; 352 #else 353 return true; 354 #endif 355 } 356 357 void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, 358 target_ulong *data) 359 { 360 env->pc = data[0]; 361 } 362 363 static void riscv_cpu_reset(DeviceState *dev) 364 { 365 CPUState *cs = CPU(dev); 366 RISCVCPU *cpu = RISCV_CPU(cs); 367 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 368 CPURISCVState *env = &cpu->env; 369 370 mcc->parent_reset(dev); 371 #ifndef CONFIG_USER_ONLY 372 env->misa_mxl = env->misa_mxl_max; 373 env->priv = PRV_M; 374 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 375 if (env->misa_mxl > MXL_RV32) { 376 /* 377 * The reset status of SXL/UXL is undefined, but mstatus is WARL 378 * and we must ensure that the value after init is valid for read. 379 */ 380 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 381 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 382 } 383 env->mcause = 0; 384 env->pc = env->resetvec; 385 env->two_stage_lookup = false; 386 /* mmte is supposed to have pm.current hardwired to 1 */ 387 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 388 #endif 389 cs->exception_index = RISCV_EXCP_NONE; 390 env->load_res = -1; 391 set_default_nan_mode(1, &env->fp_status); 392 } 393 394 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 395 { 396 RISCVCPU *cpu = RISCV_CPU(s); 397 398 switch (riscv_cpu_mxl(&cpu->env)) { 399 case MXL_RV32: 400 info->print_insn = print_insn_riscv32; 401 break; 402 case MXL_RV64: 403 info->print_insn = print_insn_riscv64; 404 break; 405 default: 406 g_assert_not_reached(); 407 } 408 } 409 410 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 411 { 412 CPUState *cs = CPU(dev); 413 RISCVCPU *cpu = RISCV_CPU(dev); 414 CPURISCVState *env = &cpu->env; 415 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 416 int priv_version = 0; 417 Error *local_err = NULL; 418 419 cpu_exec_realizefn(cs, &local_err); 420 if (local_err != NULL) { 421 error_propagate(errp, local_err); 422 return; 423 } 424 425 if (cpu->cfg.priv_spec) { 426 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 427 priv_version = PRIV_VERSION_1_11_0; 428 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 429 priv_version = PRIV_VERSION_1_10_0; 430 } else { 431 error_setg(errp, 432 "Unsupported privilege spec version '%s'", 433 cpu->cfg.priv_spec); 434 return; 435 } 436 } 437 438 if (priv_version) { 439 set_priv_version(env, priv_version); 440 } else if (!env->priv_ver) { 441 set_priv_version(env, PRIV_VERSION_1_11_0); 442 } 443 444 if (cpu->cfg.mmu) { 445 set_feature(env, RISCV_FEATURE_MMU); 446 } 447 448 if (cpu->cfg.pmp) { 449 set_feature(env, RISCV_FEATURE_PMP); 450 451 /* 452 * Enhanced PMP should only be available 453 * on harts with PMP support 454 */ 455 if (cpu->cfg.epmp) { 456 set_feature(env, RISCV_FEATURE_EPMP); 457 } 458 } 459 460 set_resetvec(env, cpu->cfg.resetvec); 461 462 /* Validate that MISA_MXL is set properly. */ 463 switch (env->misa_mxl_max) { 464 #ifdef TARGET_RISCV64 465 case MXL_RV64: 466 break; 467 #endif 468 case MXL_RV32: 469 break; 470 default: 471 g_assert_not_reached(); 472 } 473 assert(env->misa_mxl_max == env->misa_mxl); 474 475 /* If only MISA_EXT is unset for misa, then set it from properties */ 476 if (env->misa_ext == 0) { 477 uint32_t ext = 0; 478 479 /* Do some ISA extension error checking */ 480 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 481 error_setg(errp, 482 "I and E extensions are incompatible"); 483 return; 484 } 485 486 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 487 error_setg(errp, 488 "Either I or E extension must be set"); 489 return; 490 } 491 492 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & 493 cpu->cfg.ext_a & cpu->cfg.ext_f & 494 cpu->cfg.ext_d)) { 495 warn_report("Setting G will also set IMAFD"); 496 cpu->cfg.ext_i = true; 497 cpu->cfg.ext_m = true; 498 cpu->cfg.ext_a = true; 499 cpu->cfg.ext_f = true; 500 cpu->cfg.ext_d = true; 501 } 502 503 /* Set the ISA extensions, checks should have happened above */ 504 if (cpu->cfg.ext_i) { 505 ext |= RVI; 506 } 507 if (cpu->cfg.ext_e) { 508 ext |= RVE; 509 } 510 if (cpu->cfg.ext_m) { 511 ext |= RVM; 512 } 513 if (cpu->cfg.ext_a) { 514 ext |= RVA; 515 } 516 if (cpu->cfg.ext_f) { 517 ext |= RVF; 518 } 519 if (cpu->cfg.ext_d) { 520 ext |= RVD; 521 } 522 if (cpu->cfg.ext_c) { 523 ext |= RVC; 524 } 525 if (cpu->cfg.ext_s) { 526 ext |= RVS; 527 } 528 if (cpu->cfg.ext_u) { 529 ext |= RVU; 530 } 531 if (cpu->cfg.ext_h) { 532 ext |= RVH; 533 } 534 if (cpu->cfg.ext_v) { 535 int vext_version = VEXT_VERSION_1_00_0; 536 ext |= RVV; 537 if (!is_power_of_2(cpu->cfg.vlen)) { 538 error_setg(errp, 539 "Vector extension VLEN must be power of 2"); 540 return; 541 } 542 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 543 error_setg(errp, 544 "Vector extension implementation only supports VLEN " 545 "in the range [128, %d]", RV_VLEN_MAX); 546 return; 547 } 548 if (!is_power_of_2(cpu->cfg.elen)) { 549 error_setg(errp, 550 "Vector extension ELEN must be power of 2"); 551 return; 552 } 553 if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { 554 error_setg(errp, 555 "Vector extension implementation only supports ELEN " 556 "in the range [8, 64]"); 557 return; 558 } 559 if (cpu->cfg.vext_spec) { 560 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 561 vext_version = VEXT_VERSION_1_00_0; 562 } else { 563 error_setg(errp, 564 "Unsupported vector spec version '%s'", 565 cpu->cfg.vext_spec); 566 return; 567 } 568 } else { 569 qemu_log("vector version is not specified, " 570 "use the default value v1.0\n"); 571 } 572 set_vext_version(env, vext_version); 573 } 574 if (cpu->cfg.ext_j) { 575 ext |= RVJ; 576 } 577 578 set_misa(env, env->misa_mxl, ext); 579 } 580 581 riscv_cpu_register_gdb_regs_for_features(cs); 582 583 qemu_init_vcpu(cs); 584 cpu_reset(cs); 585 586 mcc->parent_realize(dev, errp); 587 } 588 589 #ifndef CONFIG_USER_ONLY 590 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 591 { 592 RISCVCPU *cpu = RISCV_CPU(opaque); 593 594 switch (irq) { 595 case IRQ_U_SOFT: 596 case IRQ_S_SOFT: 597 case IRQ_VS_SOFT: 598 case IRQ_M_SOFT: 599 case IRQ_U_TIMER: 600 case IRQ_S_TIMER: 601 case IRQ_VS_TIMER: 602 case IRQ_M_TIMER: 603 case IRQ_U_EXT: 604 case IRQ_S_EXT: 605 case IRQ_VS_EXT: 606 case IRQ_M_EXT: 607 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 608 break; 609 default: 610 g_assert_not_reached(); 611 } 612 } 613 #endif /* CONFIG_USER_ONLY */ 614 615 static void riscv_cpu_init(Object *obj) 616 { 617 RISCVCPU *cpu = RISCV_CPU(obj); 618 619 cpu_set_cpustate_pointers(cpu); 620 621 #ifndef CONFIG_USER_ONLY 622 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); 623 #endif /* CONFIG_USER_ONLY */ 624 } 625 626 static Property riscv_cpu_properties[] = { 627 /* Defaults for standard extensions */ 628 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 629 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 630 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), 631 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 632 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 633 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 634 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 635 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 636 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 637 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 638 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 639 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 640 DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), 641 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 642 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 643 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 644 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 645 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 646 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 647 648 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 649 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 650 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 651 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 652 653 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 654 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 655 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 656 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 657 658 /* These are experimental so mark with 'x-' */ 659 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 660 /* ePMP 0.9.3 */ 661 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 662 663 DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), 664 DEFINE_PROP_END_OF_LIST(), 665 }; 666 667 static gchar *riscv_gdb_arch_name(CPUState *cs) 668 { 669 RISCVCPU *cpu = RISCV_CPU(cs); 670 CPURISCVState *env = &cpu->env; 671 672 switch (riscv_cpu_mxl(env)) { 673 case MXL_RV32: 674 return g_strdup("riscv:rv32"); 675 case MXL_RV64: 676 return g_strdup("riscv:rv64"); 677 default: 678 g_assert_not_reached(); 679 } 680 } 681 682 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 683 { 684 RISCVCPU *cpu = RISCV_CPU(cs); 685 686 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 687 return cpu->dyn_csr_xml; 688 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 689 return cpu->dyn_vreg_xml; 690 } 691 692 return NULL; 693 } 694 695 #ifndef CONFIG_USER_ONLY 696 #include "hw/core/sysemu-cpu-ops.h" 697 698 static const struct SysemuCPUOps riscv_sysemu_ops = { 699 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 700 .write_elf64_note = riscv_cpu_write_elf64_note, 701 .write_elf32_note = riscv_cpu_write_elf32_note, 702 .legacy_vmsd = &vmstate_riscv_cpu, 703 }; 704 #endif 705 706 #include "hw/core/tcg-cpu-ops.h" 707 708 static const struct TCGCPUOps riscv_tcg_ops = { 709 .initialize = riscv_translate_init, 710 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 711 712 #ifndef CONFIG_USER_ONLY 713 .tlb_fill = riscv_cpu_tlb_fill, 714 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 715 .do_interrupt = riscv_cpu_do_interrupt, 716 .do_transaction_failed = riscv_cpu_do_transaction_failed, 717 .do_unaligned_access = riscv_cpu_do_unaligned_access, 718 #endif /* !CONFIG_USER_ONLY */ 719 }; 720 721 static void riscv_cpu_class_init(ObjectClass *c, void *data) 722 { 723 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 724 CPUClass *cc = CPU_CLASS(c); 725 DeviceClass *dc = DEVICE_CLASS(c); 726 727 device_class_set_parent_realize(dc, riscv_cpu_realize, 728 &mcc->parent_realize); 729 730 device_class_set_parent_reset(dc, riscv_cpu_reset, &mcc->parent_reset); 731 732 cc->class_by_name = riscv_cpu_class_by_name; 733 cc->has_work = riscv_cpu_has_work; 734 cc->dump_state = riscv_cpu_dump_state; 735 cc->set_pc = riscv_cpu_set_pc; 736 cc->gdb_read_register = riscv_cpu_gdb_read_register; 737 cc->gdb_write_register = riscv_cpu_gdb_write_register; 738 cc->gdb_num_core_regs = 33; 739 #if defined(TARGET_RISCV32) 740 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 741 #elif defined(TARGET_RISCV64) 742 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 743 #endif 744 cc->gdb_stop_before_watchpoint = true; 745 cc->disas_set_info = riscv_cpu_disas_set_info; 746 #ifndef CONFIG_USER_ONLY 747 cc->sysemu_ops = &riscv_sysemu_ops; 748 #endif 749 cc->gdb_arch_name = riscv_gdb_arch_name; 750 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 751 cc->tcg_ops = &riscv_tcg_ops; 752 753 device_class_set_props(dc, riscv_cpu_properties); 754 } 755 756 char *riscv_isa_string(RISCVCPU *cpu) 757 { 758 int i; 759 const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; 760 char *isa_str = g_new(char, maxlen); 761 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 762 for (i = 0; i < sizeof(riscv_exts); i++) { 763 if (cpu->env.misa_ext & RV(riscv_exts[i])) { 764 *p++ = qemu_tolower(riscv_exts[i]); 765 } 766 } 767 *p = '\0'; 768 return isa_str; 769 } 770 771 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 772 { 773 ObjectClass *class_a = (ObjectClass *)a; 774 ObjectClass *class_b = (ObjectClass *)b; 775 const char *name_a, *name_b; 776 777 name_a = object_class_get_name(class_a); 778 name_b = object_class_get_name(class_b); 779 return strcmp(name_a, name_b); 780 } 781 782 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 783 { 784 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 785 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 786 787 qemu_printf("%.*s\n", len, typename); 788 } 789 790 void riscv_cpu_list(void) 791 { 792 GSList *list; 793 794 list = object_class_get_list(TYPE_RISCV_CPU, false); 795 list = g_slist_sort(list, riscv_cpu_list_compare); 796 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 797 g_slist_free(list); 798 } 799 800 #define DEFINE_CPU(type_name, initfn) \ 801 { \ 802 .name = type_name, \ 803 .parent = TYPE_RISCV_CPU, \ 804 .instance_init = initfn \ 805 } 806 807 static const TypeInfo riscv_cpu_type_infos[] = { 808 { 809 .name = TYPE_RISCV_CPU, 810 .parent = TYPE_CPU, 811 .instance_size = sizeof(RISCVCPU), 812 .instance_align = __alignof__(RISCVCPU), 813 .instance_init = riscv_cpu_init, 814 .abstract = true, 815 .class_size = sizeof(RISCVCPUClass), 816 .class_init = riscv_cpu_class_init, 817 }, 818 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 819 #if defined(TARGET_RISCV32) 820 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 821 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 822 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 823 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 824 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 825 #elif defined(TARGET_RISCV64) 826 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 827 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 828 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 829 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 830 #endif 831 }; 832 833 DEFINE_TYPES(riscv_cpu_type_infos) 834