1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qapi/visitor.h" 32 #include "qemu/error-report.h" 33 #include "hw/qdev-properties.h" 34 #include "migration/vmstate.h" 35 #include "fpu/softfloat-helpers.h" 36 #include "sysemu/kvm.h" 37 #include "sysemu/tcg.h" 38 #include "kvm_riscv.h" 39 #include "tcg/tcg.h" 40 41 /* RISC-V CPU definitions */ 42 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 43 44 struct isa_ext_data { 45 const char *name; 46 int min_version; 47 int ext_enable_offset; 48 }; 49 50 #define ISA_EXT_DATA_ENTRY(_name, _min_ver, _prop) \ 51 {#_name, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 52 53 /* 54 * From vector_helper.c 55 * Note that vector data is stored in host-endian 64-bit chunks, 56 * so addressing bytes needs a host-endian fixup. 57 */ 58 #if HOST_BIG_ENDIAN 59 #define BYTE(x) ((x) ^ 7) 60 #else 61 #define BYTE(x) (x) 62 #endif 63 64 /* 65 * Here are the ordering rules of extension naming defined by RISC-V 66 * specification : 67 * 1. All extensions should be separated from other multi-letter extensions 68 * by an underscore. 69 * 2. The first letter following the 'Z' conventionally indicates the most 70 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 71 * If multiple 'Z' extensions are named, they should be ordered first 72 * by category, then alphabetically within a category. 73 * 3. Standard supervisor-level extensions (starts with 'S') should be 74 * listed after standard unprivileged extensions. If multiple 75 * supervisor-level extensions are listed, they should be ordered 76 * alphabetically. 77 * 4. Non-standard extensions (starts with 'X') must be listed after all 78 * standard extensions. They must be separated from other multi-letter 79 * extensions by an underscore. 80 * 81 * Single letter extensions are checked in riscv_cpu_validate_misa_priv() 82 * instead. 83 */ 84 static const struct isa_ext_data isa_edata_arr[] = { 85 ISA_EXT_DATA_ENTRY(zicbom, PRIV_VERSION_1_12_0, ext_icbom), 86 ISA_EXT_DATA_ENTRY(zicboz, PRIV_VERSION_1_12_0, ext_icboz), 87 ISA_EXT_DATA_ENTRY(zicond, PRIV_VERSION_1_12_0, ext_zicond), 88 ISA_EXT_DATA_ENTRY(zicsr, PRIV_VERSION_1_10_0, ext_icsr), 89 ISA_EXT_DATA_ENTRY(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), 90 ISA_EXT_DATA_ENTRY(zihintpause, PRIV_VERSION_1_10_0, ext_zihintpause), 91 ISA_EXT_DATA_ENTRY(zmmul, PRIV_VERSION_1_12_0, ext_zmmul), 92 ISA_EXT_DATA_ENTRY(zawrs, PRIV_VERSION_1_12_0, ext_zawrs), 93 ISA_EXT_DATA_ENTRY(zfa, PRIV_VERSION_1_12_0, ext_zfa), 94 ISA_EXT_DATA_ENTRY(zfbfmin, PRIV_VERSION_1_12_0, ext_zfbfmin), 95 ISA_EXT_DATA_ENTRY(zfh, PRIV_VERSION_1_11_0, ext_zfh), 96 ISA_EXT_DATA_ENTRY(zfhmin, PRIV_VERSION_1_11_0, ext_zfhmin), 97 ISA_EXT_DATA_ENTRY(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), 98 ISA_EXT_DATA_ENTRY(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), 99 ISA_EXT_DATA_ENTRY(zca, PRIV_VERSION_1_12_0, ext_zca), 100 ISA_EXT_DATA_ENTRY(zcb, PRIV_VERSION_1_12_0, ext_zcb), 101 ISA_EXT_DATA_ENTRY(zcf, PRIV_VERSION_1_12_0, ext_zcf), 102 ISA_EXT_DATA_ENTRY(zcd, PRIV_VERSION_1_12_0, ext_zcd), 103 ISA_EXT_DATA_ENTRY(zce, PRIV_VERSION_1_12_0, ext_zce), 104 ISA_EXT_DATA_ENTRY(zcmp, PRIV_VERSION_1_12_0, ext_zcmp), 105 ISA_EXT_DATA_ENTRY(zcmt, PRIV_VERSION_1_12_0, ext_zcmt), 106 ISA_EXT_DATA_ENTRY(zba, PRIV_VERSION_1_12_0, ext_zba), 107 ISA_EXT_DATA_ENTRY(zbb, PRIV_VERSION_1_12_0, ext_zbb), 108 ISA_EXT_DATA_ENTRY(zbc, PRIV_VERSION_1_12_0, ext_zbc), 109 ISA_EXT_DATA_ENTRY(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), 110 ISA_EXT_DATA_ENTRY(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), 111 ISA_EXT_DATA_ENTRY(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), 112 ISA_EXT_DATA_ENTRY(zbs, PRIV_VERSION_1_12_0, ext_zbs), 113 ISA_EXT_DATA_ENTRY(zk, PRIV_VERSION_1_12_0, ext_zk), 114 ISA_EXT_DATA_ENTRY(zkn, PRIV_VERSION_1_12_0, ext_zkn), 115 ISA_EXT_DATA_ENTRY(zknd, PRIV_VERSION_1_12_0, ext_zknd), 116 ISA_EXT_DATA_ENTRY(zkne, PRIV_VERSION_1_12_0, ext_zkne), 117 ISA_EXT_DATA_ENTRY(zknh, PRIV_VERSION_1_12_0, ext_zknh), 118 ISA_EXT_DATA_ENTRY(zkr, PRIV_VERSION_1_12_0, ext_zkr), 119 ISA_EXT_DATA_ENTRY(zks, PRIV_VERSION_1_12_0, ext_zks), 120 ISA_EXT_DATA_ENTRY(zksed, PRIV_VERSION_1_12_0, ext_zksed), 121 ISA_EXT_DATA_ENTRY(zksh, PRIV_VERSION_1_12_0, ext_zksh), 122 ISA_EXT_DATA_ENTRY(zkt, PRIV_VERSION_1_12_0, ext_zkt), 123 ISA_EXT_DATA_ENTRY(zvbb, PRIV_VERSION_1_12_0, ext_zvbb), 124 ISA_EXT_DATA_ENTRY(zvbc, PRIV_VERSION_1_12_0, ext_zvbc), 125 ISA_EXT_DATA_ENTRY(zve32f, PRIV_VERSION_1_10_0, ext_zve32f), 126 ISA_EXT_DATA_ENTRY(zve64f, PRIV_VERSION_1_10_0, ext_zve64f), 127 ISA_EXT_DATA_ENTRY(zve64d, PRIV_VERSION_1_10_0, ext_zve64d), 128 ISA_EXT_DATA_ENTRY(zvfbfmin, PRIV_VERSION_1_12_0, ext_zvfbfmin), 129 ISA_EXT_DATA_ENTRY(zvfbfwma, PRIV_VERSION_1_12_0, ext_zvfbfwma), 130 ISA_EXT_DATA_ENTRY(zvfh, PRIV_VERSION_1_12_0, ext_zvfh), 131 ISA_EXT_DATA_ENTRY(zvfhmin, PRIV_VERSION_1_12_0, ext_zvfhmin), 132 ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), 133 ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), 134 ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), 135 ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, epmp), 136 ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), 137 ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), 138 ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), 139 ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), 140 ISA_EXT_DATA_ENTRY(svadu, PRIV_VERSION_1_12_0, ext_svadu), 141 ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), 142 ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), 143 ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), 144 ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), 145 ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), 146 ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), 147 ISA_EXT_DATA_ENTRY(xtheadcmo, PRIV_VERSION_1_11_0, ext_xtheadcmo), 148 ISA_EXT_DATA_ENTRY(xtheadcondmov, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 149 ISA_EXT_DATA_ENTRY(xtheadfmemidx, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 150 ISA_EXT_DATA_ENTRY(xtheadfmv, PRIV_VERSION_1_11_0, ext_xtheadfmv), 151 ISA_EXT_DATA_ENTRY(xtheadmac, PRIV_VERSION_1_11_0, ext_xtheadmac), 152 ISA_EXT_DATA_ENTRY(xtheadmemidx, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 153 ISA_EXT_DATA_ENTRY(xtheadmempair, PRIV_VERSION_1_11_0, ext_xtheadmempair), 154 ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), 155 ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 156 }; 157 158 static bool isa_ext_is_enabled(RISCVCPU *cpu, 159 const struct isa_ext_data *edata) 160 { 161 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 162 163 return *ext_enabled; 164 } 165 166 static void isa_ext_update_enabled(RISCVCPU *cpu, 167 const struct isa_ext_data *edata, bool en) 168 { 169 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 170 171 *ext_enabled = en; 172 } 173 174 const char * const riscv_int_regnames[] = { 175 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 176 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 177 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 178 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 179 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 180 }; 181 182 const char * const riscv_int_regnamesh[] = { 183 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 184 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 185 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 186 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 187 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 188 "x30h/t5h", "x31h/t6h" 189 }; 190 191 const char * const riscv_fpr_regnames[] = { 192 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 193 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 194 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 195 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 196 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 197 "f30/ft10", "f31/ft11" 198 }; 199 200 const char * const riscv_rvv_regnames[] = { 201 "v0", "v1", "v2", "v3", "v4", "v5", "v6", 202 "v7", "v8", "v9", "v10", "v11", "v12", "v13", 203 "v14", "v15", "v16", "v17", "v18", "v19", "v20", 204 "v21", "v22", "v23", "v24", "v25", "v26", "v27", 205 "v28", "v29", "v30", "v31" 206 }; 207 208 static const char * const riscv_excp_names[] = { 209 "misaligned_fetch", 210 "fault_fetch", 211 "illegal_instruction", 212 "breakpoint", 213 "misaligned_load", 214 "fault_load", 215 "misaligned_store", 216 "fault_store", 217 "user_ecall", 218 "supervisor_ecall", 219 "hypervisor_ecall", 220 "machine_ecall", 221 "exec_page_fault", 222 "load_page_fault", 223 "reserved", 224 "store_page_fault", 225 "reserved", 226 "reserved", 227 "reserved", 228 "reserved", 229 "guest_exec_page_fault", 230 "guest_load_page_fault", 231 "reserved", 232 "guest_store_page_fault", 233 }; 234 235 static const char * const riscv_intr_names[] = { 236 "u_software", 237 "s_software", 238 "vs_software", 239 "m_software", 240 "u_timer", 241 "s_timer", 242 "vs_timer", 243 "m_timer", 244 "u_external", 245 "s_external", 246 "vs_external", 247 "m_external", 248 "reserved", 249 "reserved", 250 "reserved", 251 "reserved" 252 }; 253 254 static void riscv_cpu_add_user_properties(Object *obj); 255 256 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 257 { 258 if (async) { 259 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 260 riscv_intr_names[cause] : "(unknown)"; 261 } else { 262 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 263 riscv_excp_names[cause] : "(unknown)"; 264 } 265 } 266 267 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 268 { 269 env->misa_mxl_max = env->misa_mxl = mxl; 270 env->misa_ext_mask = env->misa_ext = ext; 271 } 272 273 #ifndef CONFIG_USER_ONLY 274 static uint8_t satp_mode_from_str(const char *satp_mode_str) 275 { 276 if (!strncmp(satp_mode_str, "mbare", 5)) { 277 return VM_1_10_MBARE; 278 } 279 280 if (!strncmp(satp_mode_str, "sv32", 4)) { 281 return VM_1_10_SV32; 282 } 283 284 if (!strncmp(satp_mode_str, "sv39", 4)) { 285 return VM_1_10_SV39; 286 } 287 288 if (!strncmp(satp_mode_str, "sv48", 4)) { 289 return VM_1_10_SV48; 290 } 291 292 if (!strncmp(satp_mode_str, "sv57", 4)) { 293 return VM_1_10_SV57; 294 } 295 296 if (!strncmp(satp_mode_str, "sv64", 4)) { 297 return VM_1_10_SV64; 298 } 299 300 g_assert_not_reached(); 301 } 302 303 uint8_t satp_mode_max_from_map(uint32_t map) 304 { 305 /* map here has at least one bit set, so no problem with clz */ 306 return 31 - __builtin_clz(map); 307 } 308 309 const char *satp_mode_str(uint8_t satp_mode, bool is_32_bit) 310 { 311 if (is_32_bit) { 312 switch (satp_mode) { 313 case VM_1_10_SV32: 314 return "sv32"; 315 case VM_1_10_MBARE: 316 return "none"; 317 } 318 } else { 319 switch (satp_mode) { 320 case VM_1_10_SV64: 321 return "sv64"; 322 case VM_1_10_SV57: 323 return "sv57"; 324 case VM_1_10_SV48: 325 return "sv48"; 326 case VM_1_10_SV39: 327 return "sv39"; 328 case VM_1_10_MBARE: 329 return "none"; 330 } 331 } 332 333 g_assert_not_reached(); 334 } 335 336 static void set_satp_mode_max_supported(RISCVCPU *cpu, 337 uint8_t satp_mode) 338 { 339 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 340 const bool *valid_vm = rv32 ? valid_vm_1_10_32 : valid_vm_1_10_64; 341 342 for (int i = 0; i <= satp_mode; ++i) { 343 if (valid_vm[i]) { 344 cpu->cfg.satp_mode.supported |= (1 << i); 345 } 346 } 347 } 348 349 /* Set the satp mode to the max supported */ 350 static void set_satp_mode_default_map(RISCVCPU *cpu) 351 { 352 cpu->cfg.satp_mode.map = cpu->cfg.satp_mode.supported; 353 } 354 #endif 355 356 static void riscv_any_cpu_init(Object *obj) 357 { 358 RISCVCPU *cpu = RISCV_CPU(obj); 359 CPURISCVState *env = &cpu->env; 360 #if defined(TARGET_RISCV32) 361 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 362 #elif defined(TARGET_RISCV64) 363 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 364 #endif 365 366 #ifndef CONFIG_USER_ONLY 367 set_satp_mode_max_supported(RISCV_CPU(obj), 368 riscv_cpu_mxl(&RISCV_CPU(obj)->env) == MXL_RV32 ? 369 VM_1_10_SV32 : VM_1_10_SV57); 370 #endif 371 372 env->priv_ver = PRIV_VERSION_LATEST; 373 374 /* inherited from parent obj via riscv_cpu_init() */ 375 cpu->cfg.ext_ifencei = true; 376 cpu->cfg.ext_icsr = true; 377 cpu->cfg.mmu = true; 378 cpu->cfg.pmp = true; 379 } 380 381 #if defined(TARGET_RISCV64) 382 static void rv64_base_cpu_init(Object *obj) 383 { 384 CPURISCVState *env = &RISCV_CPU(obj)->env; 385 /* We set this in the realise function */ 386 set_misa(env, MXL_RV64, 0); 387 riscv_cpu_add_user_properties(obj); 388 /* Set latest version of privileged specification */ 389 env->priv_ver = PRIV_VERSION_LATEST; 390 #ifndef CONFIG_USER_ONLY 391 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 392 #endif 393 } 394 395 static void rv64_sifive_u_cpu_init(Object *obj) 396 { 397 RISCVCPU *cpu = RISCV_CPU(obj); 398 CPURISCVState *env = &cpu->env; 399 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 400 env->priv_ver = PRIV_VERSION_1_10_0; 401 #ifndef CONFIG_USER_ONLY 402 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV39); 403 #endif 404 405 /* inherited from parent obj via riscv_cpu_init() */ 406 cpu->cfg.ext_ifencei = true; 407 cpu->cfg.ext_icsr = true; 408 cpu->cfg.mmu = true; 409 cpu->cfg.pmp = true; 410 } 411 412 static void rv64_sifive_e_cpu_init(Object *obj) 413 { 414 CPURISCVState *env = &RISCV_CPU(obj)->env; 415 RISCVCPU *cpu = RISCV_CPU(obj); 416 417 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 418 env->priv_ver = PRIV_VERSION_1_10_0; 419 #ifndef CONFIG_USER_ONLY 420 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 421 #endif 422 423 /* inherited from parent obj via riscv_cpu_init() */ 424 cpu->cfg.ext_ifencei = true; 425 cpu->cfg.ext_icsr = true; 426 cpu->cfg.pmp = true; 427 } 428 429 static void rv64_thead_c906_cpu_init(Object *obj) 430 { 431 CPURISCVState *env = &RISCV_CPU(obj)->env; 432 RISCVCPU *cpu = RISCV_CPU(obj); 433 434 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU); 435 env->priv_ver = PRIV_VERSION_1_11_0; 436 437 cpu->cfg.ext_zfa = true; 438 cpu->cfg.ext_zfh = true; 439 cpu->cfg.mmu = true; 440 cpu->cfg.ext_xtheadba = true; 441 cpu->cfg.ext_xtheadbb = true; 442 cpu->cfg.ext_xtheadbs = true; 443 cpu->cfg.ext_xtheadcmo = true; 444 cpu->cfg.ext_xtheadcondmov = true; 445 cpu->cfg.ext_xtheadfmemidx = true; 446 cpu->cfg.ext_xtheadmac = true; 447 cpu->cfg.ext_xtheadmemidx = true; 448 cpu->cfg.ext_xtheadmempair = true; 449 cpu->cfg.ext_xtheadsync = true; 450 451 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 452 #ifndef CONFIG_USER_ONLY 453 set_satp_mode_max_supported(cpu, VM_1_10_SV39); 454 #endif 455 456 /* inherited from parent obj via riscv_cpu_init() */ 457 cpu->cfg.pmp = true; 458 } 459 460 static void rv64_veyron_v1_cpu_init(Object *obj) 461 { 462 CPURISCVState *env = &RISCV_CPU(obj)->env; 463 RISCVCPU *cpu = RISCV_CPU(obj); 464 465 set_misa(env, MXL_RV64, RVG | RVC | RVS | RVU | RVH); 466 env->priv_ver = PRIV_VERSION_1_12_0; 467 468 /* Enable ISA extensions */ 469 cpu->cfg.mmu = true; 470 cpu->cfg.ext_ifencei = true; 471 cpu->cfg.ext_icsr = true; 472 cpu->cfg.pmp = true; 473 cpu->cfg.ext_icbom = true; 474 cpu->cfg.cbom_blocksize = 64; 475 cpu->cfg.cboz_blocksize = 64; 476 cpu->cfg.ext_icboz = true; 477 cpu->cfg.ext_smaia = true; 478 cpu->cfg.ext_ssaia = true; 479 cpu->cfg.ext_sscofpmf = true; 480 cpu->cfg.ext_sstc = true; 481 cpu->cfg.ext_svinval = true; 482 cpu->cfg.ext_svnapot = true; 483 cpu->cfg.ext_svpbmt = true; 484 cpu->cfg.ext_smstateen = true; 485 cpu->cfg.ext_zba = true; 486 cpu->cfg.ext_zbb = true; 487 cpu->cfg.ext_zbc = true; 488 cpu->cfg.ext_zbs = true; 489 cpu->cfg.ext_XVentanaCondOps = true; 490 491 cpu->cfg.mvendorid = VEYRON_V1_MVENDORID; 492 cpu->cfg.marchid = VEYRON_V1_MARCHID; 493 cpu->cfg.mimpid = VEYRON_V1_MIMPID; 494 495 #ifndef CONFIG_USER_ONLY 496 set_satp_mode_max_supported(cpu, VM_1_10_SV48); 497 #endif 498 } 499 500 static void rv128_base_cpu_init(Object *obj) 501 { 502 if (qemu_tcg_mttcg_enabled()) { 503 /* Missing 128-bit aligned atomics */ 504 error_report("128-bit RISC-V currently does not work with Multi " 505 "Threaded TCG. Please use: -accel tcg,thread=single"); 506 exit(EXIT_FAILURE); 507 } 508 CPURISCVState *env = &RISCV_CPU(obj)->env; 509 /* We set this in the realise function */ 510 set_misa(env, MXL_RV128, 0); 511 riscv_cpu_add_user_properties(obj); 512 /* Set latest version of privileged specification */ 513 env->priv_ver = PRIV_VERSION_LATEST; 514 #ifndef CONFIG_USER_ONLY 515 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); 516 #endif 517 } 518 #else 519 static void rv32_base_cpu_init(Object *obj) 520 { 521 CPURISCVState *env = &RISCV_CPU(obj)->env; 522 /* We set this in the realise function */ 523 set_misa(env, MXL_RV32, 0); 524 riscv_cpu_add_user_properties(obj); 525 /* Set latest version of privileged specification */ 526 env->priv_ver = PRIV_VERSION_LATEST; 527 #ifndef CONFIG_USER_ONLY 528 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 529 #endif 530 } 531 532 static void rv32_sifive_u_cpu_init(Object *obj) 533 { 534 RISCVCPU *cpu = RISCV_CPU(obj); 535 CPURISCVState *env = &cpu->env; 536 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 537 env->priv_ver = PRIV_VERSION_1_10_0; 538 #ifndef CONFIG_USER_ONLY 539 set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV32); 540 #endif 541 542 /* inherited from parent obj via riscv_cpu_init() */ 543 cpu->cfg.ext_ifencei = true; 544 cpu->cfg.ext_icsr = true; 545 cpu->cfg.mmu = true; 546 cpu->cfg.pmp = true; 547 } 548 549 static void rv32_sifive_e_cpu_init(Object *obj) 550 { 551 CPURISCVState *env = &RISCV_CPU(obj)->env; 552 RISCVCPU *cpu = RISCV_CPU(obj); 553 554 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 555 env->priv_ver = PRIV_VERSION_1_10_0; 556 #ifndef CONFIG_USER_ONLY 557 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 558 #endif 559 560 /* inherited from parent obj via riscv_cpu_init() */ 561 cpu->cfg.ext_ifencei = true; 562 cpu->cfg.ext_icsr = true; 563 cpu->cfg.pmp = true; 564 } 565 566 static void rv32_ibex_cpu_init(Object *obj) 567 { 568 CPURISCVState *env = &RISCV_CPU(obj)->env; 569 RISCVCPU *cpu = RISCV_CPU(obj); 570 571 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 572 env->priv_ver = PRIV_VERSION_1_11_0; 573 #ifndef CONFIG_USER_ONLY 574 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 575 #endif 576 cpu->cfg.epmp = true; 577 578 /* inherited from parent obj via riscv_cpu_init() */ 579 cpu->cfg.ext_ifencei = true; 580 cpu->cfg.ext_icsr = true; 581 cpu->cfg.pmp = true; 582 } 583 584 static void rv32_imafcu_nommu_cpu_init(Object *obj) 585 { 586 CPURISCVState *env = &RISCV_CPU(obj)->env; 587 RISCVCPU *cpu = RISCV_CPU(obj); 588 589 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 590 env->priv_ver = PRIV_VERSION_1_10_0; 591 #ifndef CONFIG_USER_ONLY 592 set_satp_mode_max_supported(cpu, VM_1_10_MBARE); 593 #endif 594 595 /* inherited from parent obj via riscv_cpu_init() */ 596 cpu->cfg.ext_ifencei = true; 597 cpu->cfg.ext_icsr = true; 598 cpu->cfg.pmp = true; 599 } 600 #endif 601 602 #if defined(CONFIG_KVM) 603 static void riscv_host_cpu_init(Object *obj) 604 { 605 CPURISCVState *env = &RISCV_CPU(obj)->env; 606 #if defined(TARGET_RISCV32) 607 set_misa(env, MXL_RV32, 0); 608 #elif defined(TARGET_RISCV64) 609 set_misa(env, MXL_RV64, 0); 610 #endif 611 riscv_cpu_add_user_properties(obj); 612 } 613 #endif /* CONFIG_KVM */ 614 615 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 616 { 617 ObjectClass *oc; 618 char *typename; 619 char **cpuname; 620 621 cpuname = g_strsplit(cpu_model, ",", 1); 622 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 623 oc = object_class_by_name(typename); 624 g_strfreev(cpuname); 625 g_free(typename); 626 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 627 object_class_is_abstract(oc)) { 628 return NULL; 629 } 630 return oc; 631 } 632 633 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 634 { 635 RISCVCPU *cpu = RISCV_CPU(cs); 636 CPURISCVState *env = &cpu->env; 637 int i, j; 638 uint8_t *p; 639 640 #if !defined(CONFIG_USER_ONLY) 641 if (riscv_has_ext(env, RVH)) { 642 qemu_fprintf(f, " %s %d\n", "V = ", env->virt_enabled); 643 } 644 #endif 645 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 646 #ifndef CONFIG_USER_ONLY 647 { 648 static const int dump_csrs[] = { 649 CSR_MHARTID, 650 CSR_MSTATUS, 651 CSR_MSTATUSH, 652 /* 653 * CSR_SSTATUS is intentionally omitted here as its value 654 * can be figured out by looking at CSR_MSTATUS 655 */ 656 CSR_HSTATUS, 657 CSR_VSSTATUS, 658 CSR_MIP, 659 CSR_MIE, 660 CSR_MIDELEG, 661 CSR_HIDELEG, 662 CSR_MEDELEG, 663 CSR_HEDELEG, 664 CSR_MTVEC, 665 CSR_STVEC, 666 CSR_VSTVEC, 667 CSR_MEPC, 668 CSR_SEPC, 669 CSR_VSEPC, 670 CSR_MCAUSE, 671 CSR_SCAUSE, 672 CSR_VSCAUSE, 673 CSR_MTVAL, 674 CSR_STVAL, 675 CSR_HTVAL, 676 CSR_MTVAL2, 677 CSR_MSCRATCH, 678 CSR_SSCRATCH, 679 CSR_SATP, 680 CSR_MMTE, 681 CSR_UPMBASE, 682 CSR_UPMMASK, 683 CSR_SPMBASE, 684 CSR_SPMMASK, 685 CSR_MPMBASE, 686 CSR_MPMMASK, 687 }; 688 689 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 690 int csrno = dump_csrs[i]; 691 target_ulong val = 0; 692 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 693 694 /* 695 * Rely on the smode, hmode, etc, predicates within csr.c 696 * to do the filtering of the registers that are present. 697 */ 698 if (res == RISCV_EXCP_NONE) { 699 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 700 csr_ops[csrno].name, val); 701 } 702 } 703 } 704 #endif 705 706 for (i = 0; i < 32; i++) { 707 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 708 riscv_int_regnames[i], env->gpr[i]); 709 if ((i & 3) == 3) { 710 qemu_fprintf(f, "\n"); 711 } 712 } 713 if (flags & CPU_DUMP_FPU) { 714 for (i = 0; i < 32; i++) { 715 qemu_fprintf(f, " %-8s %016" PRIx64, 716 riscv_fpr_regnames[i], env->fpr[i]); 717 if ((i & 3) == 3) { 718 qemu_fprintf(f, "\n"); 719 } 720 } 721 } 722 if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) { 723 static const int dump_rvv_csrs[] = { 724 CSR_VSTART, 725 CSR_VXSAT, 726 CSR_VXRM, 727 CSR_VCSR, 728 CSR_VL, 729 CSR_VTYPE, 730 CSR_VLENB, 731 }; 732 for (int i = 0; i < ARRAY_SIZE(dump_rvv_csrs); ++i) { 733 int csrno = dump_rvv_csrs[i]; 734 target_ulong val = 0; 735 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 736 737 /* 738 * Rely on the smode, hmode, etc, predicates within csr.c 739 * to do the filtering of the registers that are present. 740 */ 741 if (res == RISCV_EXCP_NONE) { 742 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 743 csr_ops[csrno].name, val); 744 } 745 } 746 uint16_t vlenb = cpu->cfg.vlen >> 3; 747 748 for (i = 0; i < 32; i++) { 749 qemu_fprintf(f, " %-8s ", riscv_rvv_regnames[i]); 750 p = (uint8_t *)env->vreg; 751 for (j = vlenb - 1 ; j >= 0; j--) { 752 qemu_fprintf(f, "%02x", *(p + i * vlenb + BYTE(j))); 753 } 754 qemu_fprintf(f, "\n"); 755 } 756 } 757 } 758 759 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 760 { 761 RISCVCPU *cpu = RISCV_CPU(cs); 762 CPURISCVState *env = &cpu->env; 763 764 if (env->xl == MXL_RV32) { 765 env->pc = (int32_t)value; 766 } else { 767 env->pc = value; 768 } 769 } 770 771 static vaddr riscv_cpu_get_pc(CPUState *cs) 772 { 773 RISCVCPU *cpu = RISCV_CPU(cs); 774 CPURISCVState *env = &cpu->env; 775 776 /* Match cpu_get_tb_cpu_state. */ 777 if (env->xl == MXL_RV32) { 778 return env->pc & UINT32_MAX; 779 } 780 return env->pc; 781 } 782 783 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 784 const TranslationBlock *tb) 785 { 786 if (!(tb_cflags(tb) & CF_PCREL)) { 787 RISCVCPU *cpu = RISCV_CPU(cs); 788 CPURISCVState *env = &cpu->env; 789 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 790 791 tcg_debug_assert(!(cs->tcg_cflags & CF_PCREL)); 792 793 if (xl == MXL_RV32) { 794 env->pc = (int32_t) tb->pc; 795 } else { 796 env->pc = tb->pc; 797 } 798 } 799 } 800 801 static bool riscv_cpu_has_work(CPUState *cs) 802 { 803 #ifndef CONFIG_USER_ONLY 804 RISCVCPU *cpu = RISCV_CPU(cs); 805 CPURISCVState *env = &cpu->env; 806 /* 807 * Definition of the WFI instruction requires it to ignore the privilege 808 * mode and delegation registers, but respect individual enables 809 */ 810 return riscv_cpu_all_pending(env) != 0; 811 #else 812 return true; 813 #endif 814 } 815 816 static void riscv_restore_state_to_opc(CPUState *cs, 817 const TranslationBlock *tb, 818 const uint64_t *data) 819 { 820 RISCVCPU *cpu = RISCV_CPU(cs); 821 CPURISCVState *env = &cpu->env; 822 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 823 target_ulong pc; 824 825 if (tb_cflags(tb) & CF_PCREL) { 826 pc = (env->pc & TARGET_PAGE_MASK) | data[0]; 827 } else { 828 pc = data[0]; 829 } 830 831 if (xl == MXL_RV32) { 832 env->pc = (int32_t)pc; 833 } else { 834 env->pc = pc; 835 } 836 env->bins = data[1]; 837 } 838 839 static void riscv_cpu_reset_hold(Object *obj) 840 { 841 #ifndef CONFIG_USER_ONLY 842 uint8_t iprio; 843 int i, irq, rdzero; 844 #endif 845 CPUState *cs = CPU(obj); 846 RISCVCPU *cpu = RISCV_CPU(cs); 847 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 848 CPURISCVState *env = &cpu->env; 849 850 if (mcc->parent_phases.hold) { 851 mcc->parent_phases.hold(obj); 852 } 853 #ifndef CONFIG_USER_ONLY 854 env->misa_mxl = env->misa_mxl_max; 855 env->priv = PRV_M; 856 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 857 if (env->misa_mxl > MXL_RV32) { 858 /* 859 * The reset status of SXL/UXL is undefined, but mstatus is WARL 860 * and we must ensure that the value after init is valid for read. 861 */ 862 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 863 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 864 if (riscv_has_ext(env, RVH)) { 865 env->vsstatus = set_field(env->vsstatus, 866 MSTATUS64_SXL, env->misa_mxl); 867 env->vsstatus = set_field(env->vsstatus, 868 MSTATUS64_UXL, env->misa_mxl); 869 env->mstatus_hs = set_field(env->mstatus_hs, 870 MSTATUS64_SXL, env->misa_mxl); 871 env->mstatus_hs = set_field(env->mstatus_hs, 872 MSTATUS64_UXL, env->misa_mxl); 873 } 874 } 875 env->mcause = 0; 876 env->miclaim = MIP_SGEIP; 877 env->pc = env->resetvec; 878 env->bins = 0; 879 env->two_stage_lookup = false; 880 881 env->menvcfg = (cpu->cfg.ext_svpbmt ? MENVCFG_PBMTE : 0) | 882 (cpu->cfg.ext_svadu ? MENVCFG_HADE : 0); 883 env->henvcfg = (cpu->cfg.ext_svpbmt ? HENVCFG_PBMTE : 0) | 884 (cpu->cfg.ext_svadu ? HENVCFG_HADE : 0); 885 886 /* Initialized default priorities of local interrupts. */ 887 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 888 iprio = riscv_cpu_default_priority(i); 889 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 890 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 891 env->hviprio[i] = 0; 892 } 893 i = 0; 894 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 895 if (!rdzero) { 896 env->hviprio[irq] = env->miprio[irq]; 897 } 898 i++; 899 } 900 /* mmte is supposed to have pm.current hardwired to 1 */ 901 env->mmte |= (EXT_STATUS_INITIAL | MMTE_M_PM_CURRENT); 902 #endif 903 env->xl = riscv_cpu_mxl(env); 904 riscv_cpu_update_mask(env); 905 cs->exception_index = RISCV_EXCP_NONE; 906 env->load_res = -1; 907 set_default_nan_mode(1, &env->fp_status); 908 909 #ifndef CONFIG_USER_ONLY 910 if (cpu->cfg.debug) { 911 riscv_trigger_init(env); 912 } 913 914 if (kvm_enabled()) { 915 kvm_riscv_reset_vcpu(cpu); 916 } 917 #endif 918 } 919 920 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 921 { 922 RISCVCPU *cpu = RISCV_CPU(s); 923 CPURISCVState *env = &cpu->env; 924 info->target_info = &cpu->cfg; 925 926 switch (env->xl) { 927 case MXL_RV32: 928 info->print_insn = print_insn_riscv32; 929 break; 930 case MXL_RV64: 931 info->print_insn = print_insn_riscv64; 932 break; 933 case MXL_RV128: 934 info->print_insn = print_insn_riscv128; 935 break; 936 default: 937 g_assert_not_reached(); 938 } 939 } 940 941 static void riscv_cpu_validate_v(CPURISCVState *env, RISCVCPUConfig *cfg, 942 Error **errp) 943 { 944 int vext_version = VEXT_VERSION_1_00_0; 945 946 if (!is_power_of_2(cfg->vlen)) { 947 error_setg(errp, "Vector extension VLEN must be power of 2"); 948 return; 949 } 950 if (cfg->vlen > RV_VLEN_MAX || cfg->vlen < 128) { 951 error_setg(errp, 952 "Vector extension implementation only supports VLEN " 953 "in the range [128, %d]", RV_VLEN_MAX); 954 return; 955 } 956 if (!is_power_of_2(cfg->elen)) { 957 error_setg(errp, "Vector extension ELEN must be power of 2"); 958 return; 959 } 960 if (cfg->elen > 64 || cfg->elen < 8) { 961 error_setg(errp, 962 "Vector extension implementation only supports ELEN " 963 "in the range [8, 64]"); 964 return; 965 } 966 if (cfg->vext_spec) { 967 if (!g_strcmp0(cfg->vext_spec, "v1.0")) { 968 vext_version = VEXT_VERSION_1_00_0; 969 } else { 970 error_setg(errp, "Unsupported vector spec version '%s'", 971 cfg->vext_spec); 972 return; 973 } 974 } else { 975 qemu_log("vector version is not specified, " 976 "use the default value v1.0\n"); 977 } 978 env->vext_ver = vext_version; 979 } 980 981 static void riscv_cpu_validate_priv_spec(RISCVCPU *cpu, Error **errp) 982 { 983 CPURISCVState *env = &cpu->env; 984 int priv_version = -1; 985 986 if (cpu->cfg.priv_spec) { 987 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 988 priv_version = PRIV_VERSION_1_12_0; 989 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 990 priv_version = PRIV_VERSION_1_11_0; 991 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 992 priv_version = PRIV_VERSION_1_10_0; 993 } else { 994 error_setg(errp, 995 "Unsupported privilege spec version '%s'", 996 cpu->cfg.priv_spec); 997 return; 998 } 999 1000 env->priv_ver = priv_version; 1001 } 1002 } 1003 1004 static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) 1005 { 1006 CPURISCVState *env = &cpu->env; 1007 int i; 1008 1009 /* Force disable extensions if priv spec version does not match */ 1010 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1011 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 1012 (env->priv_ver < isa_edata_arr[i].min_version)) { 1013 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 1014 #ifndef CONFIG_USER_ONLY 1015 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 1016 " because privilege spec version does not match", 1017 isa_edata_arr[i].name, env->mhartid); 1018 #else 1019 warn_report("disabling %s extension because " 1020 "privilege spec version does not match", 1021 isa_edata_arr[i].name); 1022 #endif 1023 } 1024 } 1025 } 1026 1027 static void riscv_cpu_validate_misa_mxl(RISCVCPU *cpu, Error **errp) 1028 { 1029 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 1030 CPUClass *cc = CPU_CLASS(mcc); 1031 CPURISCVState *env = &cpu->env; 1032 1033 /* Validate that MISA_MXL is set properly. */ 1034 switch (env->misa_mxl_max) { 1035 #ifdef TARGET_RISCV64 1036 case MXL_RV64: 1037 case MXL_RV128: 1038 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 1039 break; 1040 #endif 1041 case MXL_RV32: 1042 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 1043 break; 1044 default: 1045 g_assert_not_reached(); 1046 } 1047 1048 if (env->misa_mxl_max != env->misa_mxl) { 1049 error_setg(errp, "misa_mxl_max must be equal to misa_mxl"); 1050 return; 1051 } 1052 } 1053 1054 /* 1055 * Check consistency between chosen extensions while setting 1056 * cpu->cfg accordingly. 1057 */ 1058 void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 1059 { 1060 CPURISCVState *env = &cpu->env; 1061 Error *local_err = NULL; 1062 1063 /* Do some ISA extension error checking */ 1064 if (riscv_has_ext(env, RVG) && 1065 !(riscv_has_ext(env, RVI) && riscv_has_ext(env, RVM) && 1066 riscv_has_ext(env, RVA) && riscv_has_ext(env, RVF) && 1067 riscv_has_ext(env, RVD) && 1068 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 1069 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 1070 cpu->cfg.ext_icsr = true; 1071 cpu->cfg.ext_ifencei = true; 1072 1073 env->misa_ext |= RVI | RVM | RVA | RVF | RVD; 1074 env->misa_ext_mask |= RVI | RVM | RVA | RVF | RVD; 1075 } 1076 1077 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { 1078 error_setg(errp, 1079 "I and E extensions are incompatible"); 1080 return; 1081 } 1082 1083 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { 1084 error_setg(errp, 1085 "Either I or E extension must be set"); 1086 return; 1087 } 1088 1089 if (riscv_has_ext(env, RVS) && !riscv_has_ext(env, RVU)) { 1090 error_setg(errp, 1091 "Setting S extension without U extension is illegal"); 1092 return; 1093 } 1094 1095 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { 1096 error_setg(errp, 1097 "H depends on an I base integer ISA with 32 x registers"); 1098 return; 1099 } 1100 1101 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { 1102 error_setg(errp, "H extension implicitly requires S-mode"); 1103 return; 1104 } 1105 1106 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_icsr) { 1107 error_setg(errp, "F extension requires Zicsr"); 1108 return; 1109 } 1110 1111 if ((cpu->cfg.ext_zawrs) && !riscv_has_ext(env, RVA)) { 1112 error_setg(errp, "Zawrs extension requires A extension"); 1113 return; 1114 } 1115 1116 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { 1117 error_setg(errp, "Zfa extension requires F extension"); 1118 return; 1119 } 1120 1121 if (cpu->cfg.ext_zfh) { 1122 cpu->cfg.ext_zfhmin = true; 1123 } 1124 1125 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { 1126 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 1127 return; 1128 } 1129 1130 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { 1131 error_setg(errp, "Zfbfmin extension depends on F extension"); 1132 return; 1133 } 1134 1135 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { 1136 error_setg(errp, "D extension requires F extension"); 1137 return; 1138 } 1139 1140 if (riscv_has_ext(env, RVV)) { 1141 riscv_cpu_validate_v(env, &cpu->cfg, &local_err); 1142 if (local_err != NULL) { 1143 error_propagate(errp, local_err); 1144 return; 1145 } 1146 1147 /* The V vector extension depends on the Zve64d extension */ 1148 cpu->cfg.ext_zve64d = true; 1149 } 1150 1151 /* The Zve64d extension depends on the Zve64f extension */ 1152 if (cpu->cfg.ext_zve64d) { 1153 cpu->cfg.ext_zve64f = true; 1154 } 1155 1156 /* The Zve64f extension depends on the Zve32f extension */ 1157 if (cpu->cfg.ext_zve64f) { 1158 cpu->cfg.ext_zve32f = true; 1159 } 1160 1161 if (cpu->cfg.ext_zve64d && !riscv_has_ext(env, RVD)) { 1162 error_setg(errp, "Zve64d/V extensions require D extension"); 1163 return; 1164 } 1165 1166 if (cpu->cfg.ext_zve32f && !riscv_has_ext(env, RVF)) { 1167 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 1168 return; 1169 } 1170 1171 if (cpu->cfg.ext_zvfh) { 1172 cpu->cfg.ext_zvfhmin = true; 1173 } 1174 1175 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 1176 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 1177 return; 1178 } 1179 1180 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 1181 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 1182 return; 1183 } 1184 1185 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zfbfmin) { 1186 error_setg(errp, "Zvfbfmin extension depends on Zfbfmin extension"); 1187 return; 1188 } 1189 1190 if (cpu->cfg.ext_zvfbfmin && !cpu->cfg.ext_zve32f) { 1191 error_setg(errp, "Zvfbfmin extension depends on Zve32f extension"); 1192 return; 1193 } 1194 1195 if (cpu->cfg.ext_zvfbfwma && !cpu->cfg.ext_zvfbfmin) { 1196 error_setg(errp, "Zvfbfwma extension depends on Zvfbfmin extension"); 1197 return; 1198 } 1199 1200 /* Set the ISA extensions, checks should have happened above */ 1201 if (cpu->cfg.ext_zhinx) { 1202 cpu->cfg.ext_zhinxmin = true; 1203 } 1204 1205 if ((cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) && !cpu->cfg.ext_zfinx) { 1206 error_setg(errp, "Zdinx/Zhinx/Zhinxmin extensions require Zfinx"); 1207 return; 1208 } 1209 1210 if (cpu->cfg.ext_zfinx) { 1211 if (!cpu->cfg.ext_icsr) { 1212 error_setg(errp, "Zfinx extension requires Zicsr"); 1213 return; 1214 } 1215 if (riscv_has_ext(env, RVF)) { 1216 error_setg(errp, 1217 "Zfinx cannot be supported together with F extension"); 1218 return; 1219 } 1220 } 1221 1222 if (cpu->cfg.ext_zce) { 1223 cpu->cfg.ext_zca = true; 1224 cpu->cfg.ext_zcb = true; 1225 cpu->cfg.ext_zcmp = true; 1226 cpu->cfg.ext_zcmt = true; 1227 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 1228 cpu->cfg.ext_zcf = true; 1229 } 1230 } 1231 1232 /* zca, zcd and zcf has a PRIV 1.12.0 restriction */ 1233 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { 1234 cpu->cfg.ext_zca = true; 1235 if (riscv_has_ext(env, RVF) && env->misa_mxl_max == MXL_RV32) { 1236 cpu->cfg.ext_zcf = true; 1237 } 1238 if (riscv_has_ext(env, RVD)) { 1239 cpu->cfg.ext_zcd = true; 1240 } 1241 } 1242 1243 if (env->misa_mxl_max != MXL_RV32 && cpu->cfg.ext_zcf) { 1244 error_setg(errp, "Zcf extension is only relevant to RV32"); 1245 return; 1246 } 1247 1248 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { 1249 error_setg(errp, "Zcf extension requires F extension"); 1250 return; 1251 } 1252 1253 if (!riscv_has_ext(env, RVD) && cpu->cfg.ext_zcd) { 1254 error_setg(errp, "Zcd extension requires D extension"); 1255 return; 1256 } 1257 1258 if ((cpu->cfg.ext_zcf || cpu->cfg.ext_zcd || cpu->cfg.ext_zcb || 1259 cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt) && !cpu->cfg.ext_zca) { 1260 error_setg(errp, "Zcf/Zcd/Zcb/Zcmp/Zcmt extensions require Zca " 1261 "extension"); 1262 return; 1263 } 1264 1265 if (cpu->cfg.ext_zcd && (cpu->cfg.ext_zcmp || cpu->cfg.ext_zcmt)) { 1266 error_setg(errp, "Zcmp/Zcmt extensions are incompatible with " 1267 "Zcd extension"); 1268 return; 1269 } 1270 1271 if (cpu->cfg.ext_zcmt && !cpu->cfg.ext_icsr) { 1272 error_setg(errp, "Zcmt extension requires Zicsr extension"); 1273 return; 1274 } 1275 1276 /* 1277 * In principle Zve*x would also suffice here, were they supported 1278 * in qemu 1279 */ 1280 if (cpu->cfg.ext_zvbb && !cpu->cfg.ext_zve32f) { 1281 error_setg(errp, 1282 "Vector crypto extensions require V or Zve* extensions"); 1283 return; 1284 } 1285 1286 if (cpu->cfg.ext_zvbc && !cpu->cfg.ext_zve64f) { 1287 error_setg(errp, "Zvbc extension requires V or Zve64{f,d} extensions"); 1288 return; 1289 } 1290 1291 if (cpu->cfg.ext_zk) { 1292 cpu->cfg.ext_zkn = true; 1293 cpu->cfg.ext_zkr = true; 1294 cpu->cfg.ext_zkt = true; 1295 } 1296 1297 if (cpu->cfg.ext_zkn) { 1298 cpu->cfg.ext_zbkb = true; 1299 cpu->cfg.ext_zbkc = true; 1300 cpu->cfg.ext_zbkx = true; 1301 cpu->cfg.ext_zkne = true; 1302 cpu->cfg.ext_zknd = true; 1303 cpu->cfg.ext_zknh = true; 1304 } 1305 1306 if (cpu->cfg.ext_zks) { 1307 cpu->cfg.ext_zbkb = true; 1308 cpu->cfg.ext_zbkc = true; 1309 cpu->cfg.ext_zbkx = true; 1310 cpu->cfg.ext_zksed = true; 1311 cpu->cfg.ext_zksh = true; 1312 } 1313 1314 /* 1315 * Disable isa extensions based on priv spec after we 1316 * validated and set everything we need. 1317 */ 1318 riscv_cpu_disable_priv_spec_isa_exts(cpu); 1319 } 1320 1321 #ifndef CONFIG_USER_ONLY 1322 static void riscv_cpu_satp_mode_finalize(RISCVCPU *cpu, Error **errp) 1323 { 1324 bool rv32 = riscv_cpu_mxl(&cpu->env) == MXL_RV32; 1325 uint8_t satp_mode_map_max; 1326 uint8_t satp_mode_supported_max = 1327 satp_mode_max_from_map(cpu->cfg.satp_mode.supported); 1328 1329 if (cpu->cfg.satp_mode.map == 0) { 1330 if (cpu->cfg.satp_mode.init == 0) { 1331 /* If unset by the user, we fallback to the default satp mode. */ 1332 set_satp_mode_default_map(cpu); 1333 } else { 1334 /* 1335 * Find the lowest level that was disabled and then enable the 1336 * first valid level below which can be found in 1337 * valid_vm_1_10_32/64. 1338 */ 1339 for (int i = 1; i < 16; ++i) { 1340 if ((cpu->cfg.satp_mode.init & (1 << i)) && 1341 (cpu->cfg.satp_mode.supported & (1 << i))) { 1342 for (int j = i - 1; j >= 0; --j) { 1343 if (cpu->cfg.satp_mode.supported & (1 << j)) { 1344 cpu->cfg.satp_mode.map |= (1 << j); 1345 break; 1346 } 1347 } 1348 break; 1349 } 1350 } 1351 } 1352 } 1353 1354 satp_mode_map_max = satp_mode_max_from_map(cpu->cfg.satp_mode.map); 1355 1356 /* Make sure the user asked for a supported configuration (HW and qemu) */ 1357 if (satp_mode_map_max > satp_mode_supported_max) { 1358 error_setg(errp, "satp_mode %s is higher than hw max capability %s", 1359 satp_mode_str(satp_mode_map_max, rv32), 1360 satp_mode_str(satp_mode_supported_max, rv32)); 1361 return; 1362 } 1363 1364 /* 1365 * Make sure the user did not ask for an invalid configuration as per 1366 * the specification. 1367 */ 1368 if (!rv32) { 1369 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1370 if (!(cpu->cfg.satp_mode.map & (1 << i)) && 1371 (cpu->cfg.satp_mode.init & (1 << i)) && 1372 (cpu->cfg.satp_mode.supported & (1 << i))) { 1373 error_setg(errp, "cannot disable %s satp mode if %s " 1374 "is enabled", satp_mode_str(i, false), 1375 satp_mode_str(satp_mode_map_max, false)); 1376 return; 1377 } 1378 } 1379 } 1380 1381 /* Finally expand the map so that all valid modes are set */ 1382 for (int i = satp_mode_map_max - 1; i >= 0; --i) { 1383 if (cpu->cfg.satp_mode.supported & (1 << i)) { 1384 cpu->cfg.satp_mode.map |= (1 << i); 1385 } 1386 } 1387 } 1388 #endif 1389 1390 static void riscv_cpu_finalize_features(RISCVCPU *cpu, Error **errp) 1391 { 1392 #ifndef CONFIG_USER_ONLY 1393 Error *local_err = NULL; 1394 1395 riscv_cpu_satp_mode_finalize(cpu, &local_err); 1396 if (local_err != NULL) { 1397 error_propagate(errp, local_err); 1398 return; 1399 } 1400 #endif 1401 } 1402 1403 static void riscv_cpu_validate_misa_priv(CPURISCVState *env, Error **errp) 1404 { 1405 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { 1406 error_setg(errp, "H extension requires priv spec 1.12.0"); 1407 return; 1408 } 1409 } 1410 1411 static void riscv_cpu_realize_tcg(DeviceState *dev, Error **errp) 1412 { 1413 RISCVCPU *cpu = RISCV_CPU(dev); 1414 CPURISCVState *env = &cpu->env; 1415 Error *local_err = NULL; 1416 1417 if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_CPU_HOST)) { 1418 error_setg(errp, "'host' CPU is not compatible with TCG acceleration"); 1419 return; 1420 } 1421 1422 riscv_cpu_validate_misa_mxl(cpu, &local_err); 1423 if (local_err != NULL) { 1424 error_propagate(errp, local_err); 1425 return; 1426 } 1427 1428 riscv_cpu_validate_priv_spec(cpu, &local_err); 1429 if (local_err != NULL) { 1430 error_propagate(errp, local_err); 1431 return; 1432 } 1433 1434 riscv_cpu_validate_misa_priv(env, &local_err); 1435 if (local_err != NULL) { 1436 error_propagate(errp, local_err); 1437 return; 1438 } 1439 1440 if (cpu->cfg.epmp && !cpu->cfg.pmp) { 1441 /* 1442 * Enhanced PMP should only be available 1443 * on harts with PMP support 1444 */ 1445 error_setg(errp, "Invalid configuration: EPMP requires PMP support"); 1446 return; 1447 } 1448 1449 riscv_cpu_validate_set_extensions(cpu, &local_err); 1450 if (local_err != NULL) { 1451 error_propagate(errp, local_err); 1452 return; 1453 } 1454 1455 #ifndef CONFIG_USER_ONLY 1456 CPU(dev)->tcg_cflags |= CF_PCREL; 1457 1458 if (cpu->cfg.ext_sstc) { 1459 riscv_timer_init(cpu); 1460 } 1461 1462 if (cpu->cfg.pmu_num) { 1463 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 1464 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1465 riscv_pmu_timer_cb, cpu); 1466 } 1467 } 1468 #endif 1469 } 1470 1471 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 1472 { 1473 CPUState *cs = CPU(dev); 1474 RISCVCPU *cpu = RISCV_CPU(dev); 1475 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 1476 Error *local_err = NULL; 1477 1478 cpu_exec_realizefn(cs, &local_err); 1479 if (local_err != NULL) { 1480 error_propagate(errp, local_err); 1481 return; 1482 } 1483 1484 if (tcg_enabled()) { 1485 riscv_cpu_realize_tcg(dev, &local_err); 1486 if (local_err != NULL) { 1487 error_propagate(errp, local_err); 1488 return; 1489 } 1490 } 1491 1492 riscv_cpu_finalize_features(cpu, &local_err); 1493 if (local_err != NULL) { 1494 error_propagate(errp, local_err); 1495 return; 1496 } 1497 1498 riscv_cpu_register_gdb_regs_for_features(cs); 1499 1500 qemu_init_vcpu(cs); 1501 cpu_reset(cs); 1502 1503 mcc->parent_realize(dev, errp); 1504 } 1505 1506 #ifndef CONFIG_USER_ONLY 1507 static void cpu_riscv_get_satp(Object *obj, Visitor *v, const char *name, 1508 void *opaque, Error **errp) 1509 { 1510 RISCVSATPMap *satp_map = opaque; 1511 uint8_t satp = satp_mode_from_str(name); 1512 bool value; 1513 1514 value = satp_map->map & (1 << satp); 1515 1516 visit_type_bool(v, name, &value, errp); 1517 } 1518 1519 static void cpu_riscv_set_satp(Object *obj, Visitor *v, const char *name, 1520 void *opaque, Error **errp) 1521 { 1522 RISCVSATPMap *satp_map = opaque; 1523 uint8_t satp = satp_mode_from_str(name); 1524 bool value; 1525 1526 if (!visit_type_bool(v, name, &value, errp)) { 1527 return; 1528 } 1529 1530 satp_map->map = deposit32(satp_map->map, satp, 1, value); 1531 satp_map->init |= 1 << satp; 1532 } 1533 1534 static void riscv_add_satp_mode_properties(Object *obj) 1535 { 1536 RISCVCPU *cpu = RISCV_CPU(obj); 1537 1538 if (cpu->env.misa_mxl == MXL_RV32) { 1539 object_property_add(obj, "sv32", "bool", cpu_riscv_get_satp, 1540 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1541 } else { 1542 object_property_add(obj, "sv39", "bool", cpu_riscv_get_satp, 1543 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1544 object_property_add(obj, "sv48", "bool", cpu_riscv_get_satp, 1545 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1546 object_property_add(obj, "sv57", "bool", cpu_riscv_get_satp, 1547 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1548 object_property_add(obj, "sv64", "bool", cpu_riscv_get_satp, 1549 cpu_riscv_set_satp, NULL, &cpu->cfg.satp_mode); 1550 } 1551 } 1552 1553 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1554 { 1555 RISCVCPU *cpu = RISCV_CPU(opaque); 1556 CPURISCVState *env = &cpu->env; 1557 1558 if (irq < IRQ_LOCAL_MAX) { 1559 switch (irq) { 1560 case IRQ_U_SOFT: 1561 case IRQ_S_SOFT: 1562 case IRQ_VS_SOFT: 1563 case IRQ_M_SOFT: 1564 case IRQ_U_TIMER: 1565 case IRQ_S_TIMER: 1566 case IRQ_VS_TIMER: 1567 case IRQ_M_TIMER: 1568 case IRQ_U_EXT: 1569 case IRQ_VS_EXT: 1570 case IRQ_M_EXT: 1571 if (kvm_enabled()) { 1572 kvm_riscv_set_irq(cpu, irq, level); 1573 } else { 1574 riscv_cpu_update_mip(env, 1 << irq, BOOL_TO_MASK(level)); 1575 } 1576 break; 1577 case IRQ_S_EXT: 1578 if (kvm_enabled()) { 1579 kvm_riscv_set_irq(cpu, irq, level); 1580 } else { 1581 env->external_seip = level; 1582 riscv_cpu_update_mip(env, 1 << irq, 1583 BOOL_TO_MASK(level | env->software_seip)); 1584 } 1585 break; 1586 default: 1587 g_assert_not_reached(); 1588 } 1589 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1590 /* Require H-extension for handling guest local interrupts */ 1591 if (!riscv_has_ext(env, RVH)) { 1592 g_assert_not_reached(); 1593 } 1594 1595 /* Compute bit position in HGEIP CSR */ 1596 irq = irq - IRQ_LOCAL_MAX + 1; 1597 if (env->geilen < irq) { 1598 g_assert_not_reached(); 1599 } 1600 1601 /* Update HGEIP CSR */ 1602 env->hgeip &= ~((target_ulong)1 << irq); 1603 if (level) { 1604 env->hgeip |= (target_ulong)1 << irq; 1605 } 1606 1607 /* Update mip.SGEIP bit */ 1608 riscv_cpu_update_mip(env, MIP_SGEIP, 1609 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1610 } else { 1611 g_assert_not_reached(); 1612 } 1613 } 1614 #endif /* CONFIG_USER_ONLY */ 1615 1616 static void riscv_cpu_init(Object *obj) 1617 { 1618 RISCVCPU *cpu = RISCV_CPU(obj); 1619 1620 cpu_set_cpustate_pointers(cpu); 1621 1622 #ifndef CONFIG_USER_ONLY 1623 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1624 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1625 #endif /* CONFIG_USER_ONLY */ 1626 } 1627 1628 typedef struct RISCVCPUMisaExtConfig { 1629 const char *name; 1630 const char *description; 1631 target_ulong misa_bit; 1632 bool enabled; 1633 } RISCVCPUMisaExtConfig; 1634 1635 static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1636 void *opaque, Error **errp) 1637 { 1638 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1639 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1640 RISCVCPU *cpu = RISCV_CPU(obj); 1641 CPURISCVState *env = &cpu->env; 1642 bool value; 1643 1644 if (!visit_type_bool(v, name, &value, errp)) { 1645 return; 1646 } 1647 1648 if (value) { 1649 env->misa_ext |= misa_bit; 1650 env->misa_ext_mask |= misa_bit; 1651 } else { 1652 env->misa_ext &= ~misa_bit; 1653 env->misa_ext_mask &= ~misa_bit; 1654 } 1655 } 1656 1657 static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name, 1658 void *opaque, Error **errp) 1659 { 1660 const RISCVCPUMisaExtConfig *misa_ext_cfg = opaque; 1661 target_ulong misa_bit = misa_ext_cfg->misa_bit; 1662 RISCVCPU *cpu = RISCV_CPU(obj); 1663 CPURISCVState *env = &cpu->env; 1664 bool value; 1665 1666 value = env->misa_ext & misa_bit; 1667 1668 visit_type_bool(v, name, &value, errp); 1669 } 1670 1671 typedef struct misa_ext_info { 1672 const char *name; 1673 const char *description; 1674 } MISAExtInfo; 1675 1676 #define MISA_INFO_IDX(_bit) \ 1677 __builtin_ctz(_bit) 1678 1679 #define MISA_EXT_INFO(_bit, _propname, _descr) \ 1680 [MISA_INFO_IDX(_bit)] = {.name = _propname, .description = _descr} 1681 1682 static const MISAExtInfo misa_ext_info_arr[] = { 1683 MISA_EXT_INFO(RVA, "a", "Atomic instructions"), 1684 MISA_EXT_INFO(RVC, "c", "Compressed instructions"), 1685 MISA_EXT_INFO(RVD, "d", "Double-precision float point"), 1686 MISA_EXT_INFO(RVF, "f", "Single-precision float point"), 1687 MISA_EXT_INFO(RVI, "i", "Base integer instruction set"), 1688 MISA_EXT_INFO(RVE, "e", "Base integer instruction set (embedded)"), 1689 MISA_EXT_INFO(RVM, "m", "Integer multiplication and division"), 1690 MISA_EXT_INFO(RVS, "s", "Supervisor-level instructions"), 1691 MISA_EXT_INFO(RVU, "u", "User-level instructions"), 1692 MISA_EXT_INFO(RVH, "h", "Hypervisor"), 1693 MISA_EXT_INFO(RVJ, "x-j", "Dynamic translated languages"), 1694 MISA_EXT_INFO(RVV, "v", "Vector operations"), 1695 MISA_EXT_INFO(RVG, "g", "General purpose (IMAFD_Zicsr_Zifencei)"), 1696 }; 1697 1698 static int riscv_validate_misa_info_idx(uint32_t bit) 1699 { 1700 int idx; 1701 1702 /* 1703 * Our lowest valid input (RVA) is 1 and 1704 * __builtin_ctz() is UB with zero. 1705 */ 1706 g_assert(bit != 0); 1707 idx = MISA_INFO_IDX(bit); 1708 1709 g_assert(idx < ARRAY_SIZE(misa_ext_info_arr)); 1710 return idx; 1711 } 1712 1713 const char *riscv_get_misa_ext_name(uint32_t bit) 1714 { 1715 int idx = riscv_validate_misa_info_idx(bit); 1716 const char *val = misa_ext_info_arr[idx].name; 1717 1718 g_assert(val != NULL); 1719 return val; 1720 } 1721 1722 const char *riscv_get_misa_ext_description(uint32_t bit) 1723 { 1724 int idx = riscv_validate_misa_info_idx(bit); 1725 const char *val = misa_ext_info_arr[idx].description; 1726 1727 g_assert(val != NULL); 1728 return val; 1729 } 1730 1731 #define MISA_CFG(_bit, _enabled) \ 1732 {.misa_bit = _bit, .enabled = _enabled} 1733 1734 static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { 1735 MISA_CFG(RVA, true), 1736 MISA_CFG(RVC, true), 1737 MISA_CFG(RVD, true), 1738 MISA_CFG(RVF, true), 1739 MISA_CFG(RVI, true), 1740 MISA_CFG(RVE, false), 1741 MISA_CFG(RVM, true), 1742 MISA_CFG(RVS, true), 1743 MISA_CFG(RVU, true), 1744 MISA_CFG(RVH, true), 1745 MISA_CFG(RVJ, false), 1746 MISA_CFG(RVV, false), 1747 MISA_CFG(RVG, false), 1748 }; 1749 1750 static void riscv_cpu_add_misa_properties(Object *cpu_obj) 1751 { 1752 int i; 1753 1754 for (i = 0; i < ARRAY_SIZE(misa_ext_cfgs); i++) { 1755 RISCVCPUMisaExtConfig *misa_cfg = &misa_ext_cfgs[i]; 1756 int bit = misa_cfg->misa_bit; 1757 1758 misa_cfg->name = riscv_get_misa_ext_name(bit); 1759 misa_cfg->description = riscv_get_misa_ext_description(bit); 1760 1761 /* Check if KVM already created the property */ 1762 if (object_property_find(cpu_obj, misa_cfg->name)) { 1763 continue; 1764 } 1765 1766 object_property_add(cpu_obj, misa_cfg->name, "bool", 1767 cpu_get_misa_ext_cfg, 1768 cpu_set_misa_ext_cfg, 1769 NULL, (void *)misa_cfg); 1770 object_property_set_description(cpu_obj, misa_cfg->name, 1771 misa_cfg->description); 1772 object_property_set_bool(cpu_obj, misa_cfg->name, 1773 misa_cfg->enabled, NULL); 1774 } 1775 } 1776 1777 static Property riscv_cpu_extensions[] = { 1778 /* Defaults for standard extensions */ 1779 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1780 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1781 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1782 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1783 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1784 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1785 DEFINE_PROP_BOOL("Zfa", RISCVCPU, cfg.ext_zfa, true), 1786 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1787 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1788 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1789 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1790 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), 1791 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1792 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1793 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1794 1795 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1796 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1797 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1798 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1799 1800 DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, false), 1801 DEFINE_PROP_BOOL("svadu", RISCVCPU, cfg.ext_svadu, true), 1802 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1803 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1804 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1805 1806 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1807 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1808 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1809 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1810 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1811 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1812 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1813 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1814 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1815 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1816 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1817 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1818 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1819 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1820 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1821 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1822 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1823 1824 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1825 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1826 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1827 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1828 1829 DEFINE_PROP_BOOL("zicbom", RISCVCPU, cfg.ext_icbom, true), 1830 DEFINE_PROP_UINT16("cbom_blocksize", RISCVCPU, cfg.cbom_blocksize, 64), 1831 DEFINE_PROP_BOOL("zicboz", RISCVCPU, cfg.ext_icboz, true), 1832 DEFINE_PROP_UINT16("cboz_blocksize", RISCVCPU, cfg.cboz_blocksize, 64), 1833 1834 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1835 1836 DEFINE_PROP_BOOL("zca", RISCVCPU, cfg.ext_zca, false), 1837 DEFINE_PROP_BOOL("zcb", RISCVCPU, cfg.ext_zcb, false), 1838 DEFINE_PROP_BOOL("zcd", RISCVCPU, cfg.ext_zcd, false), 1839 DEFINE_PROP_BOOL("zce", RISCVCPU, cfg.ext_zce, false), 1840 DEFINE_PROP_BOOL("zcf", RISCVCPU, cfg.ext_zcf, false), 1841 DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false), 1842 DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false), 1843 1844 /* Vendor-specific custom extensions */ 1845 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1846 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1847 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1848 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1849 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1850 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1851 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1852 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1853 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1854 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1855 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1856 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1857 1858 /* These are experimental so mark with 'x-' */ 1859 DEFINE_PROP_BOOL("x-zicond", RISCVCPU, cfg.ext_zicond, false), 1860 1861 /* ePMP 0.9.3 */ 1862 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1863 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1864 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1865 1866 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), 1867 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), 1868 1869 DEFINE_PROP_BOOL("x-zfbfmin", RISCVCPU, cfg.ext_zfbfmin, false), 1870 DEFINE_PROP_BOOL("x-zvfbfmin", RISCVCPU, cfg.ext_zvfbfmin, false), 1871 DEFINE_PROP_BOOL("x-zvfbfwma", RISCVCPU, cfg.ext_zvfbfwma, false), 1872 1873 /* Vector cryptography extensions */ 1874 DEFINE_PROP_BOOL("x-zvbb", RISCVCPU, cfg.ext_zvbb, false), 1875 DEFINE_PROP_BOOL("x-zvbc", RISCVCPU, cfg.ext_zvbc, false), 1876 1877 DEFINE_PROP_END_OF_LIST(), 1878 }; 1879 1880 1881 #ifndef CONFIG_USER_ONLY 1882 static void cpu_set_cfg_unavailable(Object *obj, Visitor *v, 1883 const char *name, 1884 void *opaque, Error **errp) 1885 { 1886 const char *propname = opaque; 1887 bool value; 1888 1889 if (!visit_type_bool(v, name, &value, errp)) { 1890 return; 1891 } 1892 1893 if (value) { 1894 error_setg(errp, "extension %s is not available with KVM", 1895 propname); 1896 } 1897 } 1898 #endif 1899 1900 /* 1901 * Add CPU properties with user-facing flags. 1902 * 1903 * This will overwrite existing env->misa_ext values with the 1904 * defaults set via riscv_cpu_add_misa_properties(). 1905 */ 1906 static void riscv_cpu_add_user_properties(Object *obj) 1907 { 1908 Property *prop; 1909 DeviceState *dev = DEVICE(obj); 1910 1911 #ifndef CONFIG_USER_ONLY 1912 riscv_add_satp_mode_properties(obj); 1913 1914 if (kvm_enabled()) { 1915 kvm_riscv_init_user_properties(obj); 1916 } 1917 #endif 1918 1919 riscv_cpu_add_misa_properties(obj); 1920 1921 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1922 #ifndef CONFIG_USER_ONLY 1923 if (kvm_enabled()) { 1924 /* Check if KVM created the property already */ 1925 if (object_property_find(obj, prop->name)) { 1926 continue; 1927 } 1928 1929 /* 1930 * Set the default to disabled for every extension 1931 * unknown to KVM and error out if the user attempts 1932 * to enable any of them. 1933 * 1934 * We're giving a pass for non-bool properties since they're 1935 * not related to the availability of extensions and can be 1936 * safely ignored as is. 1937 */ 1938 if (prop->info == &qdev_prop_bool) { 1939 object_property_add(obj, prop->name, "bool", 1940 NULL, cpu_set_cfg_unavailable, 1941 NULL, (void *)prop->name); 1942 continue; 1943 } 1944 } 1945 #endif 1946 qdev_property_add_static(dev, prop); 1947 } 1948 } 1949 1950 static Property riscv_cpu_properties[] = { 1951 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1952 1953 #ifndef CONFIG_USER_ONLY 1954 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1955 #endif 1956 1957 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1958 1959 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1960 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1961 1962 /* 1963 * write_misa() is marked as experimental for now so mark 1964 * it with -x and default to 'false'. 1965 */ 1966 DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), 1967 DEFINE_PROP_END_OF_LIST(), 1968 }; 1969 1970 static gchar *riscv_gdb_arch_name(CPUState *cs) 1971 { 1972 RISCVCPU *cpu = RISCV_CPU(cs); 1973 CPURISCVState *env = &cpu->env; 1974 1975 switch (riscv_cpu_mxl(env)) { 1976 case MXL_RV32: 1977 return g_strdup("riscv:rv32"); 1978 case MXL_RV64: 1979 case MXL_RV128: 1980 return g_strdup("riscv:rv64"); 1981 default: 1982 g_assert_not_reached(); 1983 } 1984 } 1985 1986 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1987 { 1988 RISCVCPU *cpu = RISCV_CPU(cs); 1989 1990 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1991 return cpu->dyn_csr_xml; 1992 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1993 return cpu->dyn_vreg_xml; 1994 } 1995 1996 return NULL; 1997 } 1998 1999 #ifndef CONFIG_USER_ONLY 2000 static int64_t riscv_get_arch_id(CPUState *cs) 2001 { 2002 RISCVCPU *cpu = RISCV_CPU(cs); 2003 2004 return cpu->env.mhartid; 2005 } 2006 2007 #include "hw/core/sysemu-cpu-ops.h" 2008 2009 static const struct SysemuCPUOps riscv_sysemu_ops = { 2010 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 2011 .write_elf64_note = riscv_cpu_write_elf64_note, 2012 .write_elf32_note = riscv_cpu_write_elf32_note, 2013 .legacy_vmsd = &vmstate_riscv_cpu, 2014 }; 2015 #endif 2016 2017 #include "hw/core/tcg-cpu-ops.h" 2018 2019 static const struct TCGCPUOps riscv_tcg_ops = { 2020 .initialize = riscv_translate_init, 2021 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 2022 .restore_state_to_opc = riscv_restore_state_to_opc, 2023 2024 #ifndef CONFIG_USER_ONLY 2025 .tlb_fill = riscv_cpu_tlb_fill, 2026 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 2027 .do_interrupt = riscv_cpu_do_interrupt, 2028 .do_transaction_failed = riscv_cpu_do_transaction_failed, 2029 .do_unaligned_access = riscv_cpu_do_unaligned_access, 2030 .debug_excp_handler = riscv_cpu_debug_excp_handler, 2031 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 2032 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 2033 #endif /* !CONFIG_USER_ONLY */ 2034 }; 2035 2036 static bool riscv_cpu_is_dynamic(Object *cpu_obj) 2037 { 2038 return object_dynamic_cast(cpu_obj, TYPE_RISCV_DYNAMIC_CPU) != NULL; 2039 } 2040 2041 static void cpu_set_mvendorid(Object *obj, Visitor *v, const char *name, 2042 void *opaque, Error **errp) 2043 { 2044 bool dynamic_cpu = riscv_cpu_is_dynamic(obj); 2045 RISCVCPU *cpu = RISCV_CPU(obj); 2046 uint32_t prev_val = cpu->cfg.mvendorid; 2047 uint32_t value; 2048 2049 if (!visit_type_uint32(v, name, &value, errp)) { 2050 return; 2051 } 2052 2053 if (!dynamic_cpu && prev_val != value) { 2054 error_setg(errp, "Unable to change %s mvendorid (0x%x)", 2055 object_get_typename(obj), prev_val); 2056 return; 2057 } 2058 2059 cpu->cfg.mvendorid = value; 2060 } 2061 2062 static void cpu_get_mvendorid(Object *obj, Visitor *v, const char *name, 2063 void *opaque, Error **errp) 2064 { 2065 bool value = RISCV_CPU(obj)->cfg.mvendorid; 2066 2067 visit_type_bool(v, name, &value, errp); 2068 } 2069 2070 static void cpu_set_mimpid(Object *obj, Visitor *v, const char *name, 2071 void *opaque, Error **errp) 2072 { 2073 bool dynamic_cpu = riscv_cpu_is_dynamic(obj); 2074 RISCVCPU *cpu = RISCV_CPU(obj); 2075 uint64_t prev_val = cpu->cfg.mimpid; 2076 uint64_t value; 2077 2078 if (!visit_type_uint64(v, name, &value, errp)) { 2079 return; 2080 } 2081 2082 if (!dynamic_cpu && prev_val != value) { 2083 error_setg(errp, "Unable to change %s mimpid (0x%" PRIu64 ")", 2084 object_get_typename(obj), prev_val); 2085 return; 2086 } 2087 2088 cpu->cfg.mimpid = value; 2089 } 2090 2091 static void cpu_get_mimpid(Object *obj, Visitor *v, const char *name, 2092 void *opaque, Error **errp) 2093 { 2094 bool value = RISCV_CPU(obj)->cfg.mimpid; 2095 2096 visit_type_bool(v, name, &value, errp); 2097 } 2098 2099 static void cpu_set_marchid(Object *obj, Visitor *v, const char *name, 2100 void *opaque, Error **errp) 2101 { 2102 bool dynamic_cpu = riscv_cpu_is_dynamic(obj); 2103 RISCVCPU *cpu = RISCV_CPU(obj); 2104 uint64_t prev_val = cpu->cfg.marchid; 2105 uint64_t value, invalid_val; 2106 uint32_t mxlen = 0; 2107 2108 if (!visit_type_uint64(v, name, &value, errp)) { 2109 return; 2110 } 2111 2112 if (!dynamic_cpu && prev_val != value) { 2113 error_setg(errp, "Unable to change %s marchid (0x%" PRIu64 ")", 2114 object_get_typename(obj), prev_val); 2115 return; 2116 } 2117 2118 switch (riscv_cpu_mxl(&cpu->env)) { 2119 case MXL_RV32: 2120 mxlen = 32; 2121 break; 2122 case MXL_RV64: 2123 case MXL_RV128: 2124 mxlen = 64; 2125 break; 2126 default: 2127 g_assert_not_reached(); 2128 } 2129 2130 invalid_val = 1LL << (mxlen - 1); 2131 2132 if (value == invalid_val) { 2133 error_setg(errp, "Unable to set marchid with MSB (%u) bit set " 2134 "and the remaining bits zero", mxlen); 2135 return; 2136 } 2137 2138 cpu->cfg.marchid = value; 2139 } 2140 2141 static void cpu_get_marchid(Object *obj, Visitor *v, const char *name, 2142 void *opaque, Error **errp) 2143 { 2144 bool value = RISCV_CPU(obj)->cfg.marchid; 2145 2146 visit_type_bool(v, name, &value, errp); 2147 } 2148 2149 static void riscv_cpu_class_init(ObjectClass *c, void *data) 2150 { 2151 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 2152 CPUClass *cc = CPU_CLASS(c); 2153 DeviceClass *dc = DEVICE_CLASS(c); 2154 ResettableClass *rc = RESETTABLE_CLASS(c); 2155 2156 device_class_set_parent_realize(dc, riscv_cpu_realize, 2157 &mcc->parent_realize); 2158 2159 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 2160 &mcc->parent_phases); 2161 2162 cc->class_by_name = riscv_cpu_class_by_name; 2163 cc->has_work = riscv_cpu_has_work; 2164 cc->dump_state = riscv_cpu_dump_state; 2165 cc->set_pc = riscv_cpu_set_pc; 2166 cc->get_pc = riscv_cpu_get_pc; 2167 cc->gdb_read_register = riscv_cpu_gdb_read_register; 2168 cc->gdb_write_register = riscv_cpu_gdb_write_register; 2169 cc->gdb_num_core_regs = 33; 2170 cc->gdb_stop_before_watchpoint = true; 2171 cc->disas_set_info = riscv_cpu_disas_set_info; 2172 #ifndef CONFIG_USER_ONLY 2173 cc->sysemu_ops = &riscv_sysemu_ops; 2174 cc->get_arch_id = riscv_get_arch_id; 2175 #endif 2176 cc->gdb_arch_name = riscv_gdb_arch_name; 2177 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 2178 cc->tcg_ops = &riscv_tcg_ops; 2179 2180 object_class_property_add(c, "mvendorid", "uint32", cpu_get_mvendorid, 2181 cpu_set_mvendorid, NULL, NULL); 2182 2183 object_class_property_add(c, "mimpid", "uint64", cpu_get_mimpid, 2184 cpu_set_mimpid, NULL, NULL); 2185 2186 object_class_property_add(c, "marchid", "uint64", cpu_get_marchid, 2187 cpu_set_marchid, NULL, NULL); 2188 2189 device_class_set_props(dc, riscv_cpu_properties); 2190 } 2191 2192 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, 2193 int max_str_len) 2194 { 2195 char *old = *isa_str; 2196 char *new = *isa_str; 2197 int i; 2198 2199 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 2200 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 2201 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 2202 g_free(old); 2203 old = new; 2204 } 2205 } 2206 2207 *isa_str = new; 2208 } 2209 2210 char *riscv_isa_string(RISCVCPU *cpu) 2211 { 2212 int i; 2213 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 2214 char *isa_str = g_new(char, maxlen); 2215 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 2216 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 2217 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 2218 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 2219 } 2220 } 2221 *p = '\0'; 2222 if (!cpu->cfg.short_isa_string) { 2223 riscv_isa_string_ext(cpu, &isa_str, maxlen); 2224 } 2225 return isa_str; 2226 } 2227 2228 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 2229 { 2230 ObjectClass *class_a = (ObjectClass *)a; 2231 ObjectClass *class_b = (ObjectClass *)b; 2232 const char *name_a, *name_b; 2233 2234 name_a = object_class_get_name(class_a); 2235 name_b = object_class_get_name(class_b); 2236 return strcmp(name_a, name_b); 2237 } 2238 2239 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 2240 { 2241 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 2242 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 2243 2244 qemu_printf("%.*s\n", len, typename); 2245 } 2246 2247 void riscv_cpu_list(void) 2248 { 2249 GSList *list; 2250 2251 list = object_class_get_list(TYPE_RISCV_CPU, false); 2252 list = g_slist_sort(list, riscv_cpu_list_compare); 2253 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 2254 g_slist_free(list); 2255 } 2256 2257 #define DEFINE_CPU(type_name, initfn) \ 2258 { \ 2259 .name = type_name, \ 2260 .parent = TYPE_RISCV_CPU, \ 2261 .instance_init = initfn \ 2262 } 2263 2264 #define DEFINE_DYNAMIC_CPU(type_name, initfn) \ 2265 { \ 2266 .name = type_name, \ 2267 .parent = TYPE_RISCV_DYNAMIC_CPU, \ 2268 .instance_init = initfn \ 2269 } 2270 2271 static const TypeInfo riscv_cpu_type_infos[] = { 2272 { 2273 .name = TYPE_RISCV_CPU, 2274 .parent = TYPE_CPU, 2275 .instance_size = sizeof(RISCVCPU), 2276 .instance_align = __alignof__(RISCVCPU), 2277 .instance_init = riscv_cpu_init, 2278 .abstract = true, 2279 .class_size = sizeof(RISCVCPUClass), 2280 .class_init = riscv_cpu_class_init, 2281 }, 2282 { 2283 .name = TYPE_RISCV_DYNAMIC_CPU, 2284 .parent = TYPE_RISCV_CPU, 2285 .abstract = true, 2286 }, 2287 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 2288 #if defined(CONFIG_KVM) 2289 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 2290 #endif 2291 #if defined(TARGET_RISCV32) 2292 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 2293 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 2294 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 2295 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 2296 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 2297 #elif defined(TARGET_RISCV64) 2298 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 2299 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 2300 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 2301 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 2302 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 2303 DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), 2304 DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 2305 #endif 2306 }; 2307 2308 DEFINE_TYPES(riscv_cpu_type_infos) 2309