1 /* 2 * QEMU RISC-V CPU 3 * 4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms and conditions of the GNU General Public License, 9 * version 2 or later, as published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope it will be useful, but WITHOUT 12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 14 * more details. 15 * 16 * You should have received a copy of the GNU General Public License along with 17 * this program. If not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #include "qemu/osdep.h" 21 #include "qemu/qemu-print.h" 22 #include "qemu/ctype.h" 23 #include "qemu/log.h" 24 #include "cpu.h" 25 #include "cpu_vendorid.h" 26 #include "pmu.h" 27 #include "internals.h" 28 #include "time_helper.h" 29 #include "exec/exec-all.h" 30 #include "qapi/error.h" 31 #include "qemu/error-report.h" 32 #include "hw/qdev-properties.h" 33 #include "migration/vmstate.h" 34 #include "fpu/softfloat-helpers.h" 35 #include "sysemu/kvm.h" 36 #include "kvm_riscv.h" 37 38 /* RISC-V CPU definitions */ 39 40 #define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \ 41 (QEMU_VERSION_MINOR << 8) | \ 42 (QEMU_VERSION_MICRO)) 43 #define RISCV_CPU_MIMPID RISCV_CPU_MARCHID 44 45 static const char riscv_single_letter_exts[] = "IEMAFDQCPVH"; 46 47 struct isa_ext_data { 48 const char *name; 49 bool multi_letter; 50 int min_version; 51 int ext_enable_offset; 52 }; 53 54 #define ISA_EXT_DATA_ENTRY(_name, _m_letter, _min_ver, _prop) \ 55 {#_name, _m_letter, _min_ver, offsetof(struct RISCVCPUConfig, _prop)} 56 57 /** 58 * Here are the ordering rules of extension naming defined by RISC-V 59 * specification : 60 * 1. All extensions should be separated from other multi-letter extensions 61 * by an underscore. 62 * 2. The first letter following the 'Z' conventionally indicates the most 63 * closely related alphabetical extension category, IMAFDQLCBKJTPVH. 64 * If multiple 'Z' extensions are named, they should be ordered first 65 * by category, then alphabetically within a category. 66 * 3. Standard supervisor-level extensions (starts with 'S') should be 67 * listed after standard unprivileged extensions. If multiple 68 * supervisor-level extensions are listed, they should be ordered 69 * alphabetically. 70 * 4. Non-standard extensions (starts with 'X') must be listed after all 71 * standard extensions. They must be separated from other multi-letter 72 * extensions by an underscore. 73 */ 74 static const struct isa_ext_data isa_edata_arr[] = { 75 ISA_EXT_DATA_ENTRY(h, false, PRIV_VERSION_1_12_0, ext_h), 76 ISA_EXT_DATA_ENTRY(v, false, PRIV_VERSION_1_10_0, ext_v), 77 ISA_EXT_DATA_ENTRY(zicsr, true, PRIV_VERSION_1_10_0, ext_icsr), 78 ISA_EXT_DATA_ENTRY(zifencei, true, PRIV_VERSION_1_10_0, ext_ifencei), 79 ISA_EXT_DATA_ENTRY(zihintpause, true, PRIV_VERSION_1_10_0, ext_zihintpause), 80 ISA_EXT_DATA_ENTRY(zawrs, true, PRIV_VERSION_1_12_0, ext_zawrs), 81 ISA_EXT_DATA_ENTRY(zfh, true, PRIV_VERSION_1_11_0, ext_zfh), 82 ISA_EXT_DATA_ENTRY(zfhmin, true, PRIV_VERSION_1_12_0, ext_zfhmin), 83 ISA_EXT_DATA_ENTRY(zfinx, true, PRIV_VERSION_1_12_0, ext_zfinx), 84 ISA_EXT_DATA_ENTRY(zdinx, true, PRIV_VERSION_1_12_0, ext_zdinx), 85 ISA_EXT_DATA_ENTRY(zba, true, PRIV_VERSION_1_12_0, ext_zba), 86 ISA_EXT_DATA_ENTRY(zbb, true, PRIV_VERSION_1_12_0, ext_zbb), 87 ISA_EXT_DATA_ENTRY(zbc, true, PRIV_VERSION_1_12_0, ext_zbc), 88 ISA_EXT_DATA_ENTRY(zbkb, true, PRIV_VERSION_1_12_0, ext_zbkb), 89 ISA_EXT_DATA_ENTRY(zbkc, true, PRIV_VERSION_1_12_0, ext_zbkc), 90 ISA_EXT_DATA_ENTRY(zbkx, true, PRIV_VERSION_1_12_0, ext_zbkx), 91 ISA_EXT_DATA_ENTRY(zbs, true, PRIV_VERSION_1_12_0, ext_zbs), 92 ISA_EXT_DATA_ENTRY(zk, true, PRIV_VERSION_1_12_0, ext_zk), 93 ISA_EXT_DATA_ENTRY(zkn, true, PRIV_VERSION_1_12_0, ext_zkn), 94 ISA_EXT_DATA_ENTRY(zknd, true, PRIV_VERSION_1_12_0, ext_zknd), 95 ISA_EXT_DATA_ENTRY(zkne, true, PRIV_VERSION_1_12_0, ext_zkne), 96 ISA_EXT_DATA_ENTRY(zknh, true, PRIV_VERSION_1_12_0, ext_zknh), 97 ISA_EXT_DATA_ENTRY(zkr, true, PRIV_VERSION_1_12_0, ext_zkr), 98 ISA_EXT_DATA_ENTRY(zks, true, PRIV_VERSION_1_12_0, ext_zks), 99 ISA_EXT_DATA_ENTRY(zksed, true, PRIV_VERSION_1_12_0, ext_zksed), 100 ISA_EXT_DATA_ENTRY(zksh, true, PRIV_VERSION_1_12_0, ext_zksh), 101 ISA_EXT_DATA_ENTRY(zkt, true, PRIV_VERSION_1_12_0, ext_zkt), 102 ISA_EXT_DATA_ENTRY(zve32f, true, PRIV_VERSION_1_12_0, ext_zve32f), 103 ISA_EXT_DATA_ENTRY(zve64f, true, PRIV_VERSION_1_12_0, ext_zve64f), 104 ISA_EXT_DATA_ENTRY(zve64d, true, PRIV_VERSION_1_12_0, ext_zve64d), 105 ISA_EXT_DATA_ENTRY(zvfh, true, PRIV_VERSION_1_12_0, ext_zvfh), 106 ISA_EXT_DATA_ENTRY(zvfhmin, true, PRIV_VERSION_1_12_0, ext_zvfhmin), 107 ISA_EXT_DATA_ENTRY(zhinx, true, PRIV_VERSION_1_12_0, ext_zhinx), 108 ISA_EXT_DATA_ENTRY(zhinxmin, true, PRIV_VERSION_1_12_0, ext_zhinxmin), 109 ISA_EXT_DATA_ENTRY(smaia, true, PRIV_VERSION_1_12_0, ext_smaia), 110 ISA_EXT_DATA_ENTRY(ssaia, true, PRIV_VERSION_1_12_0, ext_ssaia), 111 ISA_EXT_DATA_ENTRY(sscofpmf, true, PRIV_VERSION_1_12_0, ext_sscofpmf), 112 ISA_EXT_DATA_ENTRY(sstc, true, PRIV_VERSION_1_12_0, ext_sstc), 113 ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval), 114 ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot), 115 ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt), 116 ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba), 117 ISA_EXT_DATA_ENTRY(xtheadbb, true, PRIV_VERSION_1_11_0, ext_xtheadbb), 118 ISA_EXT_DATA_ENTRY(xtheadbs, true, PRIV_VERSION_1_11_0, ext_xtheadbs), 119 ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo), 120 ISA_EXT_DATA_ENTRY(xtheadcondmov, true, PRIV_VERSION_1_11_0, ext_xtheadcondmov), 121 ISA_EXT_DATA_ENTRY(xtheadfmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadfmemidx), 122 ISA_EXT_DATA_ENTRY(xtheadfmv, true, PRIV_VERSION_1_11_0, ext_xtheadfmv), 123 ISA_EXT_DATA_ENTRY(xtheadmac, true, PRIV_VERSION_1_11_0, ext_xtheadmac), 124 ISA_EXT_DATA_ENTRY(xtheadmemidx, true, PRIV_VERSION_1_11_0, ext_xtheadmemidx), 125 ISA_EXT_DATA_ENTRY(xtheadmempair, true, PRIV_VERSION_1_11_0, ext_xtheadmempair), 126 ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync), 127 ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), 128 }; 129 130 static bool isa_ext_is_enabled(RISCVCPU *cpu, 131 const struct isa_ext_data *edata) 132 { 133 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 134 135 return *ext_enabled; 136 } 137 138 static void isa_ext_update_enabled(RISCVCPU *cpu, 139 const struct isa_ext_data *edata, bool en) 140 { 141 bool *ext_enabled = (void *)&cpu->cfg + edata->ext_enable_offset; 142 143 *ext_enabled = en; 144 } 145 146 const char * const riscv_int_regnames[] = { 147 "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", 148 "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", 149 "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", 150 "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", 151 "x28/t3", "x29/t4", "x30/t5", "x31/t6" 152 }; 153 154 const char * const riscv_int_regnamesh[] = { 155 "x0h/zeroh", "x1h/rah", "x2h/sph", "x3h/gph", "x4h/tph", "x5h/t0h", 156 "x6h/t1h", "x7h/t2h", "x8h/s0h", "x9h/s1h", "x10h/a0h", "x11h/a1h", 157 "x12h/a2h", "x13h/a3h", "x14h/a4h", "x15h/a5h", "x16h/a6h", "x17h/a7h", 158 "x18h/s2h", "x19h/s3h", "x20h/s4h", "x21h/s5h", "x22h/s6h", "x23h/s7h", 159 "x24h/s8h", "x25h/s9h", "x26h/s10h", "x27h/s11h", "x28h/t3h", "x29h/t4h", 160 "x30h/t5h", "x31h/t6h" 161 }; 162 163 const char * const riscv_fpr_regnames[] = { 164 "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", 165 "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", 166 "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", 167 "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", 168 "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", 169 "f30/ft10", "f31/ft11" 170 }; 171 172 static const char * const riscv_excp_names[] = { 173 "misaligned_fetch", 174 "fault_fetch", 175 "illegal_instruction", 176 "breakpoint", 177 "misaligned_load", 178 "fault_load", 179 "misaligned_store", 180 "fault_store", 181 "user_ecall", 182 "supervisor_ecall", 183 "hypervisor_ecall", 184 "machine_ecall", 185 "exec_page_fault", 186 "load_page_fault", 187 "reserved", 188 "store_page_fault", 189 "reserved", 190 "reserved", 191 "reserved", 192 "reserved", 193 "guest_exec_page_fault", 194 "guest_load_page_fault", 195 "reserved", 196 "guest_store_page_fault", 197 }; 198 199 static const char * const riscv_intr_names[] = { 200 "u_software", 201 "s_software", 202 "vs_software", 203 "m_software", 204 "u_timer", 205 "s_timer", 206 "vs_timer", 207 "m_timer", 208 "u_external", 209 "s_external", 210 "vs_external", 211 "m_external", 212 "reserved", 213 "reserved", 214 "reserved", 215 "reserved" 216 }; 217 218 static void register_cpu_props(DeviceState *dev); 219 220 const char *riscv_cpu_get_trap_name(target_ulong cause, bool async) 221 { 222 if (async) { 223 return (cause < ARRAY_SIZE(riscv_intr_names)) ? 224 riscv_intr_names[cause] : "(unknown)"; 225 } else { 226 return (cause < ARRAY_SIZE(riscv_excp_names)) ? 227 riscv_excp_names[cause] : "(unknown)"; 228 } 229 } 230 231 static void set_misa(CPURISCVState *env, RISCVMXL mxl, uint32_t ext) 232 { 233 env->misa_mxl_max = env->misa_mxl = mxl; 234 env->misa_ext_mask = env->misa_ext = ext; 235 } 236 237 static void set_priv_version(CPURISCVState *env, int priv_ver) 238 { 239 env->priv_ver = priv_ver; 240 } 241 242 static void set_vext_version(CPURISCVState *env, int vext_ver) 243 { 244 env->vext_ver = vext_ver; 245 } 246 247 static void riscv_any_cpu_init(Object *obj) 248 { 249 CPURISCVState *env = &RISCV_CPU(obj)->env; 250 #if defined(TARGET_RISCV32) 251 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 252 #elif defined(TARGET_RISCV64) 253 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); 254 #endif 255 set_priv_version(env, PRIV_VERSION_1_12_0); 256 register_cpu_props(DEVICE(obj)); 257 } 258 259 #if defined(TARGET_RISCV64) 260 static void rv64_base_cpu_init(Object *obj) 261 { 262 CPURISCVState *env = &RISCV_CPU(obj)->env; 263 /* We set this in the realise function */ 264 set_misa(env, MXL_RV64, 0); 265 register_cpu_props(DEVICE(obj)); 266 /* Set latest version of privileged specification */ 267 set_priv_version(env, PRIV_VERSION_1_12_0); 268 } 269 270 static void rv64_sifive_u_cpu_init(Object *obj) 271 { 272 CPURISCVState *env = &RISCV_CPU(obj)->env; 273 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 274 register_cpu_props(DEVICE(obj)); 275 set_priv_version(env, PRIV_VERSION_1_10_0); 276 } 277 278 static void rv64_sifive_e_cpu_init(Object *obj) 279 { 280 CPURISCVState *env = &RISCV_CPU(obj)->env; 281 RISCVCPU *cpu = RISCV_CPU(obj); 282 283 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVC | RVU); 284 register_cpu_props(DEVICE(obj)); 285 set_priv_version(env, PRIV_VERSION_1_10_0); 286 cpu->cfg.mmu = false; 287 } 288 289 static void rv64_thead_c906_cpu_init(Object *obj) 290 { 291 CPURISCVState *env = &RISCV_CPU(obj)->env; 292 RISCVCPU *cpu = RISCV_CPU(obj); 293 294 set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 295 set_priv_version(env, PRIV_VERSION_1_11_0); 296 297 cpu->cfg.ext_g = true; 298 cpu->cfg.ext_c = true; 299 cpu->cfg.ext_u = true; 300 cpu->cfg.ext_s = true; 301 cpu->cfg.ext_icsr = true; 302 cpu->cfg.ext_zfh = true; 303 cpu->cfg.mmu = true; 304 cpu->cfg.ext_xtheadba = true; 305 cpu->cfg.ext_xtheadbb = true; 306 cpu->cfg.ext_xtheadbs = true; 307 cpu->cfg.ext_xtheadcmo = true; 308 cpu->cfg.ext_xtheadcondmov = true; 309 cpu->cfg.ext_xtheadfmemidx = true; 310 cpu->cfg.ext_xtheadmac = true; 311 cpu->cfg.ext_xtheadmemidx = true; 312 cpu->cfg.ext_xtheadmempair = true; 313 cpu->cfg.ext_xtheadsync = true; 314 315 cpu->cfg.mvendorid = THEAD_VENDOR_ID; 316 } 317 318 static void rv128_base_cpu_init(Object *obj) 319 { 320 if (qemu_tcg_mttcg_enabled()) { 321 /* Missing 128-bit aligned atomics */ 322 error_report("128-bit RISC-V currently does not work with Multi " 323 "Threaded TCG. Please use: -accel tcg,thread=single"); 324 exit(EXIT_FAILURE); 325 } 326 CPURISCVState *env = &RISCV_CPU(obj)->env; 327 /* We set this in the realise function */ 328 set_misa(env, MXL_RV128, 0); 329 register_cpu_props(DEVICE(obj)); 330 /* Set latest version of privileged specification */ 331 set_priv_version(env, PRIV_VERSION_1_12_0); 332 } 333 #else 334 static void rv32_base_cpu_init(Object *obj) 335 { 336 CPURISCVState *env = &RISCV_CPU(obj)->env; 337 /* We set this in the realise function */ 338 set_misa(env, MXL_RV32, 0); 339 register_cpu_props(DEVICE(obj)); 340 /* Set latest version of privileged specification */ 341 set_priv_version(env, PRIV_VERSION_1_12_0); 342 } 343 344 static void rv32_sifive_u_cpu_init(Object *obj) 345 { 346 CPURISCVState *env = &RISCV_CPU(obj)->env; 347 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); 348 register_cpu_props(DEVICE(obj)); 349 set_priv_version(env, PRIV_VERSION_1_10_0); 350 } 351 352 static void rv32_sifive_e_cpu_init(Object *obj) 353 { 354 CPURISCVState *env = &RISCV_CPU(obj)->env; 355 RISCVCPU *cpu = RISCV_CPU(obj); 356 357 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVC | RVU); 358 register_cpu_props(DEVICE(obj)); 359 set_priv_version(env, PRIV_VERSION_1_10_0); 360 cpu->cfg.mmu = false; 361 } 362 363 static void rv32_ibex_cpu_init(Object *obj) 364 { 365 CPURISCVState *env = &RISCV_CPU(obj)->env; 366 RISCVCPU *cpu = RISCV_CPU(obj); 367 368 set_misa(env, MXL_RV32, RVI | RVM | RVC | RVU); 369 register_cpu_props(DEVICE(obj)); 370 set_priv_version(env, PRIV_VERSION_1_11_0); 371 cpu->cfg.mmu = false; 372 cpu->cfg.epmp = true; 373 } 374 375 static void rv32_imafcu_nommu_cpu_init(Object *obj) 376 { 377 CPURISCVState *env = &RISCV_CPU(obj)->env; 378 RISCVCPU *cpu = RISCV_CPU(obj); 379 380 set_misa(env, MXL_RV32, RVI | RVM | RVA | RVF | RVC | RVU); 381 register_cpu_props(DEVICE(obj)); 382 set_priv_version(env, PRIV_VERSION_1_10_0); 383 cpu->cfg.mmu = false; 384 } 385 #endif 386 387 #if defined(CONFIG_KVM) 388 static void riscv_host_cpu_init(Object *obj) 389 { 390 CPURISCVState *env = &RISCV_CPU(obj)->env; 391 #if defined(TARGET_RISCV32) 392 set_misa(env, MXL_RV32, 0); 393 #elif defined(TARGET_RISCV64) 394 set_misa(env, MXL_RV64, 0); 395 #endif 396 register_cpu_props(DEVICE(obj)); 397 } 398 #endif 399 400 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) 401 { 402 ObjectClass *oc; 403 char *typename; 404 char **cpuname; 405 406 cpuname = g_strsplit(cpu_model, ",", 1); 407 typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); 408 oc = object_class_by_name(typename); 409 g_strfreev(cpuname); 410 g_free(typename); 411 if (!oc || !object_class_dynamic_cast(oc, TYPE_RISCV_CPU) || 412 object_class_is_abstract(oc)) { 413 return NULL; 414 } 415 return oc; 416 } 417 418 static void riscv_cpu_dump_state(CPUState *cs, FILE *f, int flags) 419 { 420 RISCVCPU *cpu = RISCV_CPU(cs); 421 CPURISCVState *env = &cpu->env; 422 int i; 423 424 #if !defined(CONFIG_USER_ONLY) 425 if (riscv_has_ext(env, RVH)) { 426 qemu_fprintf(f, " %s %d\n", "V = ", riscv_cpu_virt_enabled(env)); 427 } 428 #endif 429 qemu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); 430 #ifndef CONFIG_USER_ONLY 431 { 432 static const int dump_csrs[] = { 433 CSR_MHARTID, 434 CSR_MSTATUS, 435 CSR_MSTATUSH, 436 /* 437 * CSR_SSTATUS is intentionally omitted here as its value 438 * can be figured out by looking at CSR_MSTATUS 439 */ 440 CSR_HSTATUS, 441 CSR_VSSTATUS, 442 CSR_MIP, 443 CSR_MIE, 444 CSR_MIDELEG, 445 CSR_HIDELEG, 446 CSR_MEDELEG, 447 CSR_HEDELEG, 448 CSR_MTVEC, 449 CSR_STVEC, 450 CSR_VSTVEC, 451 CSR_MEPC, 452 CSR_SEPC, 453 CSR_VSEPC, 454 CSR_MCAUSE, 455 CSR_SCAUSE, 456 CSR_VSCAUSE, 457 CSR_MTVAL, 458 CSR_STVAL, 459 CSR_HTVAL, 460 CSR_MTVAL2, 461 CSR_MSCRATCH, 462 CSR_SSCRATCH, 463 CSR_SATP, 464 CSR_MMTE, 465 CSR_UPMBASE, 466 CSR_UPMMASK, 467 CSR_SPMBASE, 468 CSR_SPMMASK, 469 CSR_MPMBASE, 470 CSR_MPMMASK, 471 }; 472 473 for (int i = 0; i < ARRAY_SIZE(dump_csrs); ++i) { 474 int csrno = dump_csrs[i]; 475 target_ulong val = 0; 476 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); 477 478 /* 479 * Rely on the smode, hmode, etc, predicates within csr.c 480 * to do the filtering of the registers that are present. 481 */ 482 if (res == RISCV_EXCP_NONE) { 483 qemu_fprintf(f, " %-8s " TARGET_FMT_lx "\n", 484 csr_ops[csrno].name, val); 485 } 486 } 487 } 488 #endif 489 490 for (i = 0; i < 32; i++) { 491 qemu_fprintf(f, " %-8s " TARGET_FMT_lx, 492 riscv_int_regnames[i], env->gpr[i]); 493 if ((i & 3) == 3) { 494 qemu_fprintf(f, "\n"); 495 } 496 } 497 if (flags & CPU_DUMP_FPU) { 498 for (i = 0; i < 32; i++) { 499 qemu_fprintf(f, " %-8s %016" PRIx64, 500 riscv_fpr_regnames[i], env->fpr[i]); 501 if ((i & 3) == 3) { 502 qemu_fprintf(f, "\n"); 503 } 504 } 505 } 506 } 507 508 static void riscv_cpu_set_pc(CPUState *cs, vaddr value) 509 { 510 RISCVCPU *cpu = RISCV_CPU(cs); 511 CPURISCVState *env = &cpu->env; 512 513 if (env->xl == MXL_RV32) { 514 env->pc = (int32_t)value; 515 } else { 516 env->pc = value; 517 } 518 } 519 520 static vaddr riscv_cpu_get_pc(CPUState *cs) 521 { 522 RISCVCPU *cpu = RISCV_CPU(cs); 523 CPURISCVState *env = &cpu->env; 524 525 /* Match cpu_get_tb_cpu_state. */ 526 if (env->xl == MXL_RV32) { 527 return env->pc & UINT32_MAX; 528 } 529 return env->pc; 530 } 531 532 static void riscv_cpu_synchronize_from_tb(CPUState *cs, 533 const TranslationBlock *tb) 534 { 535 RISCVCPU *cpu = RISCV_CPU(cs); 536 CPURISCVState *env = &cpu->env; 537 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 538 539 if (xl == MXL_RV32) { 540 env->pc = (int32_t)tb_pc(tb); 541 } else { 542 env->pc = tb_pc(tb); 543 } 544 } 545 546 static bool riscv_cpu_has_work(CPUState *cs) 547 { 548 #ifndef CONFIG_USER_ONLY 549 RISCVCPU *cpu = RISCV_CPU(cs); 550 CPURISCVState *env = &cpu->env; 551 /* 552 * Definition of the WFI instruction requires it to ignore the privilege 553 * mode and delegation registers, but respect individual enables 554 */ 555 return riscv_cpu_all_pending(env) != 0; 556 #else 557 return true; 558 #endif 559 } 560 561 static void riscv_restore_state_to_opc(CPUState *cs, 562 const TranslationBlock *tb, 563 const uint64_t *data) 564 { 565 RISCVCPU *cpu = RISCV_CPU(cs); 566 CPURISCVState *env = &cpu->env; 567 RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); 568 569 if (xl == MXL_RV32) { 570 env->pc = (int32_t)data[0]; 571 } else { 572 env->pc = data[0]; 573 } 574 env->bins = data[1]; 575 } 576 577 static void riscv_cpu_reset_hold(Object *obj) 578 { 579 #ifndef CONFIG_USER_ONLY 580 uint8_t iprio; 581 int i, irq, rdzero; 582 #endif 583 CPUState *cs = CPU(obj); 584 RISCVCPU *cpu = RISCV_CPU(cs); 585 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu); 586 CPURISCVState *env = &cpu->env; 587 588 if (mcc->parent_phases.hold) { 589 mcc->parent_phases.hold(obj); 590 } 591 #ifndef CONFIG_USER_ONLY 592 env->misa_mxl = env->misa_mxl_max; 593 env->priv = PRV_M; 594 env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); 595 if (env->misa_mxl > MXL_RV32) { 596 /* 597 * The reset status of SXL/UXL is undefined, but mstatus is WARL 598 * and we must ensure that the value after init is valid for read. 599 */ 600 env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl); 601 env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); 602 if (riscv_has_ext(env, RVH)) { 603 env->vsstatus = set_field(env->vsstatus, 604 MSTATUS64_SXL, env->misa_mxl); 605 env->vsstatus = set_field(env->vsstatus, 606 MSTATUS64_UXL, env->misa_mxl); 607 env->mstatus_hs = set_field(env->mstatus_hs, 608 MSTATUS64_SXL, env->misa_mxl); 609 env->mstatus_hs = set_field(env->mstatus_hs, 610 MSTATUS64_UXL, env->misa_mxl); 611 } 612 } 613 env->mcause = 0; 614 env->miclaim = MIP_SGEIP; 615 env->pc = env->resetvec; 616 env->bins = 0; 617 env->two_stage_lookup = false; 618 619 /* Initialized default priorities of local interrupts. */ 620 for (i = 0; i < ARRAY_SIZE(env->miprio); i++) { 621 iprio = riscv_cpu_default_priority(i); 622 env->miprio[i] = (i == IRQ_M_EXT) ? 0 : iprio; 623 env->siprio[i] = (i == IRQ_S_EXT) ? 0 : iprio; 624 env->hviprio[i] = 0; 625 } 626 i = 0; 627 while (!riscv_cpu_hviprio_index2irq(i, &irq, &rdzero)) { 628 if (!rdzero) { 629 env->hviprio[irq] = env->miprio[irq]; 630 } 631 i++; 632 } 633 /* mmte is supposed to have pm.current hardwired to 1 */ 634 env->mmte |= (PM_EXT_INITIAL | MMTE_M_PM_CURRENT); 635 #endif 636 env->xl = riscv_cpu_mxl(env); 637 riscv_cpu_update_mask(env); 638 cs->exception_index = RISCV_EXCP_NONE; 639 env->load_res = -1; 640 set_default_nan_mode(1, &env->fp_status); 641 642 #ifndef CONFIG_USER_ONLY 643 if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { 644 riscv_trigger_init(env); 645 } 646 647 if (kvm_enabled()) { 648 kvm_riscv_reset_vcpu(cpu); 649 } 650 #endif 651 } 652 653 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) 654 { 655 RISCVCPU *cpu = RISCV_CPU(s); 656 657 switch (riscv_cpu_mxl(&cpu->env)) { 658 case MXL_RV32: 659 info->print_insn = print_insn_riscv32; 660 break; 661 case MXL_RV64: 662 info->print_insn = print_insn_riscv64; 663 break; 664 case MXL_RV128: 665 info->print_insn = print_insn_riscv128; 666 break; 667 default: 668 g_assert_not_reached(); 669 } 670 } 671 672 /* 673 * Check consistency between chosen extensions while setting 674 * cpu->cfg accordingly, doing a set_misa() in the end. 675 */ 676 static void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) 677 { 678 CPURISCVState *env = &cpu->env; 679 uint32_t ext = 0; 680 681 /* Do some ISA extension error checking */ 682 if (cpu->cfg.ext_g && !(cpu->cfg.ext_i && cpu->cfg.ext_m && 683 cpu->cfg.ext_a && cpu->cfg.ext_f && 684 cpu->cfg.ext_d && 685 cpu->cfg.ext_icsr && cpu->cfg.ext_ifencei)) { 686 warn_report("Setting G will also set IMAFD_Zicsr_Zifencei"); 687 cpu->cfg.ext_i = true; 688 cpu->cfg.ext_m = true; 689 cpu->cfg.ext_a = true; 690 cpu->cfg.ext_f = true; 691 cpu->cfg.ext_d = true; 692 cpu->cfg.ext_icsr = true; 693 cpu->cfg.ext_ifencei = true; 694 } 695 696 if (cpu->cfg.ext_i && cpu->cfg.ext_e) { 697 error_setg(errp, 698 "I and E extensions are incompatible"); 699 return; 700 } 701 702 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { 703 error_setg(errp, 704 "Either I or E extension must be set"); 705 return; 706 } 707 708 if (cpu->cfg.ext_s && !cpu->cfg.ext_u) { 709 error_setg(errp, 710 "Setting S extension without U extension is illegal"); 711 return; 712 } 713 714 if (cpu->cfg.ext_h && !cpu->cfg.ext_i) { 715 error_setg(errp, 716 "H depends on an I base integer ISA with 32 x registers"); 717 return; 718 } 719 720 if (cpu->cfg.ext_h && !cpu->cfg.ext_s) { 721 error_setg(errp, "H extension implicitly requires S-mode"); 722 return; 723 } 724 725 if (cpu->cfg.ext_f && !cpu->cfg.ext_icsr) { 726 error_setg(errp, "F extension requires Zicsr"); 727 return; 728 } 729 730 if ((cpu->cfg.ext_zawrs) && !cpu->cfg.ext_a) { 731 error_setg(errp, "Zawrs extension requires A extension"); 732 return; 733 } 734 735 if (cpu->cfg.ext_zfh) { 736 cpu->cfg.ext_zfhmin = true; 737 } 738 739 if (cpu->cfg.ext_zfhmin && !cpu->cfg.ext_f) { 740 error_setg(errp, "Zfh/Zfhmin extensions require F extension"); 741 return; 742 } 743 744 if (cpu->cfg.ext_d && !cpu->cfg.ext_f) { 745 error_setg(errp, "D extension requires F extension"); 746 return; 747 } 748 749 /* The V vector extension depends on the Zve64d extension */ 750 if (cpu->cfg.ext_v) { 751 cpu->cfg.ext_zve64d = true; 752 } 753 754 /* The Zve64d extension depends on the Zve64f extension */ 755 if (cpu->cfg.ext_zve64d) { 756 cpu->cfg.ext_zve64f = true; 757 } 758 759 /* The Zve64f extension depends on the Zve32f extension */ 760 if (cpu->cfg.ext_zve64f) { 761 cpu->cfg.ext_zve32f = true; 762 } 763 764 if (cpu->cfg.ext_zve64d && !cpu->cfg.ext_d) { 765 error_setg(errp, "Zve64d/V extensions require D extension"); 766 return; 767 } 768 769 if (cpu->cfg.ext_zve32f && !cpu->cfg.ext_f) { 770 error_setg(errp, "Zve32f/Zve64f extensions require F extension"); 771 return; 772 } 773 774 if (cpu->cfg.ext_zvfh) { 775 cpu->cfg.ext_zvfhmin = true; 776 } 777 778 if (cpu->cfg.ext_zvfhmin && !cpu->cfg.ext_zve32f) { 779 error_setg(errp, "Zvfh/Zvfhmin extensions require Zve32f extension"); 780 return; 781 } 782 783 if (cpu->cfg.ext_zvfh && !cpu->cfg.ext_zfhmin) { 784 error_setg(errp, "Zvfh extensions requires Zfhmin extension"); 785 return; 786 } 787 788 /* Set the ISA extensions, checks should have happened above */ 789 if (cpu->cfg.ext_zhinx) { 790 cpu->cfg.ext_zhinxmin = true; 791 } 792 793 if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinxmin) { 794 cpu->cfg.ext_zfinx = true; 795 } 796 797 if (cpu->cfg.ext_zfinx) { 798 if (!cpu->cfg.ext_icsr) { 799 error_setg(errp, "Zfinx extension requires Zicsr"); 800 return; 801 } 802 if (cpu->cfg.ext_f) { 803 error_setg(errp, 804 "Zfinx cannot be supported together with F extension"); 805 return; 806 } 807 } 808 809 if (cpu->cfg.ext_zk) { 810 cpu->cfg.ext_zkn = true; 811 cpu->cfg.ext_zkr = true; 812 cpu->cfg.ext_zkt = true; 813 } 814 815 if (cpu->cfg.ext_zkn) { 816 cpu->cfg.ext_zbkb = true; 817 cpu->cfg.ext_zbkc = true; 818 cpu->cfg.ext_zbkx = true; 819 cpu->cfg.ext_zkne = true; 820 cpu->cfg.ext_zknd = true; 821 cpu->cfg.ext_zknh = true; 822 } 823 824 if (cpu->cfg.ext_zks) { 825 cpu->cfg.ext_zbkb = true; 826 cpu->cfg.ext_zbkc = true; 827 cpu->cfg.ext_zbkx = true; 828 cpu->cfg.ext_zksed = true; 829 cpu->cfg.ext_zksh = true; 830 } 831 832 if (cpu->cfg.ext_i) { 833 ext |= RVI; 834 } 835 if (cpu->cfg.ext_e) { 836 ext |= RVE; 837 } 838 if (cpu->cfg.ext_m) { 839 ext |= RVM; 840 } 841 if (cpu->cfg.ext_a) { 842 ext |= RVA; 843 } 844 if (cpu->cfg.ext_f) { 845 ext |= RVF; 846 } 847 if (cpu->cfg.ext_d) { 848 ext |= RVD; 849 } 850 if (cpu->cfg.ext_c) { 851 ext |= RVC; 852 } 853 if (cpu->cfg.ext_s) { 854 ext |= RVS; 855 } 856 if (cpu->cfg.ext_u) { 857 ext |= RVU; 858 } 859 if (cpu->cfg.ext_h) { 860 ext |= RVH; 861 } 862 if (cpu->cfg.ext_v) { 863 int vext_version = VEXT_VERSION_1_00_0; 864 ext |= RVV; 865 if (!is_power_of_2(cpu->cfg.vlen)) { 866 error_setg(errp, 867 "Vector extension VLEN must be power of 2"); 868 return; 869 } 870 if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { 871 error_setg(errp, 872 "Vector extension implementation only supports VLEN " 873 "in the range [128, %d]", RV_VLEN_MAX); 874 return; 875 } 876 if (!is_power_of_2(cpu->cfg.elen)) { 877 error_setg(errp, 878 "Vector extension ELEN must be power of 2"); 879 return; 880 } 881 if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) { 882 error_setg(errp, 883 "Vector extension implementation only supports ELEN " 884 "in the range [8, 64]"); 885 return; 886 } 887 if (cpu->cfg.vext_spec) { 888 if (!g_strcmp0(cpu->cfg.vext_spec, "v1.0")) { 889 vext_version = VEXT_VERSION_1_00_0; 890 } else { 891 error_setg(errp, 892 "Unsupported vector spec version '%s'", 893 cpu->cfg.vext_spec); 894 return; 895 } 896 } else { 897 qemu_log("vector version is not specified, " 898 "use the default value v1.0\n"); 899 } 900 set_vext_version(env, vext_version); 901 } 902 if (cpu->cfg.ext_j) { 903 ext |= RVJ; 904 } 905 906 set_misa(env, env->misa_mxl, ext); 907 } 908 909 static void riscv_cpu_realize(DeviceState *dev, Error **errp) 910 { 911 CPUState *cs = CPU(dev); 912 RISCVCPU *cpu = RISCV_CPU(dev); 913 CPURISCVState *env = &cpu->env; 914 RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(dev); 915 CPUClass *cc = CPU_CLASS(mcc); 916 int i, priv_version = -1; 917 Error *local_err = NULL; 918 919 cpu_exec_realizefn(cs, &local_err); 920 if (local_err != NULL) { 921 error_propagate(errp, local_err); 922 return; 923 } 924 925 if (cpu->cfg.priv_spec) { 926 if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { 927 priv_version = PRIV_VERSION_1_12_0; 928 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { 929 priv_version = PRIV_VERSION_1_11_0; 930 } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { 931 priv_version = PRIV_VERSION_1_10_0; 932 } else { 933 error_setg(errp, 934 "Unsupported privilege spec version '%s'", 935 cpu->cfg.priv_spec); 936 return; 937 } 938 } 939 940 if (priv_version >= PRIV_VERSION_1_10_0) { 941 set_priv_version(env, priv_version); 942 } 943 944 /* Force disable extensions if priv spec version does not match */ 945 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 946 if (isa_ext_is_enabled(cpu, &isa_edata_arr[i]) && 947 (env->priv_ver < isa_edata_arr[i].min_version)) { 948 isa_ext_update_enabled(cpu, &isa_edata_arr[i], false); 949 #ifndef CONFIG_USER_ONLY 950 warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx 951 " because privilege spec version does not match", 952 isa_edata_arr[i].name, env->mhartid); 953 #else 954 warn_report("disabling %s extension because " 955 "privilege spec version does not match", 956 isa_edata_arr[i].name); 957 #endif 958 } 959 } 960 961 if (cpu->cfg.mmu) { 962 riscv_set_feature(env, RISCV_FEATURE_MMU); 963 } 964 965 if (cpu->cfg.pmp) { 966 riscv_set_feature(env, RISCV_FEATURE_PMP); 967 968 /* 969 * Enhanced PMP should only be available 970 * on harts with PMP support 971 */ 972 if (cpu->cfg.epmp) { 973 riscv_set_feature(env, RISCV_FEATURE_EPMP); 974 } 975 } 976 977 if (cpu->cfg.debug) { 978 riscv_set_feature(env, RISCV_FEATURE_DEBUG); 979 } 980 981 982 #ifndef CONFIG_USER_ONLY 983 if (cpu->cfg.ext_sstc) { 984 riscv_timer_init(cpu); 985 } 986 #endif /* CONFIG_USER_ONLY */ 987 988 /* Validate that MISA_MXL is set properly. */ 989 switch (env->misa_mxl_max) { 990 #ifdef TARGET_RISCV64 991 case MXL_RV64: 992 case MXL_RV128: 993 cc->gdb_core_xml_file = "riscv-64bit-cpu.xml"; 994 break; 995 #endif 996 case MXL_RV32: 997 cc->gdb_core_xml_file = "riscv-32bit-cpu.xml"; 998 break; 999 default: 1000 g_assert_not_reached(); 1001 } 1002 assert(env->misa_mxl_max == env->misa_mxl); 1003 1004 riscv_cpu_validate_set_extensions(cpu, &local_err); 1005 if (local_err != NULL) { 1006 error_propagate(errp, local_err); 1007 return; 1008 } 1009 1010 #ifndef CONFIG_USER_ONLY 1011 if (cpu->cfg.pmu_num) { 1012 if (!riscv_pmu_init(cpu, cpu->cfg.pmu_num) && cpu->cfg.ext_sscofpmf) { 1013 cpu->pmu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1014 riscv_pmu_timer_cb, cpu); 1015 } 1016 } 1017 #endif 1018 1019 riscv_cpu_register_gdb_regs_for_features(cs); 1020 1021 qemu_init_vcpu(cs); 1022 cpu_reset(cs); 1023 1024 mcc->parent_realize(dev, errp); 1025 } 1026 1027 #ifndef CONFIG_USER_ONLY 1028 static void riscv_cpu_set_irq(void *opaque, int irq, int level) 1029 { 1030 RISCVCPU *cpu = RISCV_CPU(opaque); 1031 CPURISCVState *env = &cpu->env; 1032 1033 if (irq < IRQ_LOCAL_MAX) { 1034 switch (irq) { 1035 case IRQ_U_SOFT: 1036 case IRQ_S_SOFT: 1037 case IRQ_VS_SOFT: 1038 case IRQ_M_SOFT: 1039 case IRQ_U_TIMER: 1040 case IRQ_S_TIMER: 1041 case IRQ_VS_TIMER: 1042 case IRQ_M_TIMER: 1043 case IRQ_U_EXT: 1044 case IRQ_VS_EXT: 1045 case IRQ_M_EXT: 1046 if (kvm_enabled()) { 1047 kvm_riscv_set_irq(cpu, irq, level); 1048 } else { 1049 riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); 1050 } 1051 break; 1052 case IRQ_S_EXT: 1053 if (kvm_enabled()) { 1054 kvm_riscv_set_irq(cpu, irq, level); 1055 } else { 1056 env->external_seip = level; 1057 riscv_cpu_update_mip(cpu, 1 << irq, 1058 BOOL_TO_MASK(level | env->software_seip)); 1059 } 1060 break; 1061 default: 1062 g_assert_not_reached(); 1063 } 1064 } else if (irq < (IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX)) { 1065 /* Require H-extension for handling guest local interrupts */ 1066 if (!riscv_has_ext(env, RVH)) { 1067 g_assert_not_reached(); 1068 } 1069 1070 /* Compute bit position in HGEIP CSR */ 1071 irq = irq - IRQ_LOCAL_MAX + 1; 1072 if (env->geilen < irq) { 1073 g_assert_not_reached(); 1074 } 1075 1076 /* Update HGEIP CSR */ 1077 env->hgeip &= ~((target_ulong)1 << irq); 1078 if (level) { 1079 env->hgeip |= (target_ulong)1 << irq; 1080 } 1081 1082 /* Update mip.SGEIP bit */ 1083 riscv_cpu_update_mip(cpu, MIP_SGEIP, 1084 BOOL_TO_MASK(!!(env->hgeie & env->hgeip))); 1085 } else { 1086 g_assert_not_reached(); 1087 } 1088 } 1089 #endif /* CONFIG_USER_ONLY */ 1090 1091 static void riscv_cpu_init(Object *obj) 1092 { 1093 RISCVCPU *cpu = RISCV_CPU(obj); 1094 1095 cpu->cfg.ext_ifencei = true; 1096 cpu->cfg.ext_icsr = true; 1097 cpu->cfg.mmu = true; 1098 cpu->cfg.pmp = true; 1099 1100 cpu_set_cpustate_pointers(cpu); 1101 1102 #ifndef CONFIG_USER_ONLY 1103 qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 1104 IRQ_LOCAL_MAX + IRQ_LOCAL_GUEST_MAX); 1105 #endif /* CONFIG_USER_ONLY */ 1106 } 1107 1108 static Property riscv_cpu_extensions[] = { 1109 /* Defaults for standard extensions */ 1110 DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), 1111 DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), 1112 DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, false), 1113 DEFINE_PROP_BOOL("m", RISCVCPU, cfg.ext_m, true), 1114 DEFINE_PROP_BOOL("a", RISCVCPU, cfg.ext_a, true), 1115 DEFINE_PROP_BOOL("f", RISCVCPU, cfg.ext_f, true), 1116 DEFINE_PROP_BOOL("d", RISCVCPU, cfg.ext_d, true), 1117 DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), 1118 DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), 1119 DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), 1120 DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), 1121 DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), 1122 DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), 1123 DEFINE_PROP_BOOL("sscofpmf", RISCVCPU, cfg.ext_sscofpmf, false), 1124 DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), 1125 DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), 1126 DEFINE_PROP_BOOL("Zihintpause", RISCVCPU, cfg.ext_zihintpause, true), 1127 DEFINE_PROP_BOOL("Zawrs", RISCVCPU, cfg.ext_zawrs, true), 1128 DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), 1129 DEFINE_PROP_BOOL("Zfhmin", RISCVCPU, cfg.ext_zfhmin, false), 1130 DEFINE_PROP_BOOL("Zve32f", RISCVCPU, cfg.ext_zve32f, false), 1131 DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), 1132 DEFINE_PROP_BOOL("Zve64d", RISCVCPU, cfg.ext_zve64d, false), 1133 DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), 1134 DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), 1135 DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), 1136 1137 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), 1138 DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), 1139 DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), 1140 DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), 1141 1142 DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false), 1143 DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false), 1144 DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false), 1145 1146 DEFINE_PROP_BOOL("zba", RISCVCPU, cfg.ext_zba, true), 1147 DEFINE_PROP_BOOL("zbb", RISCVCPU, cfg.ext_zbb, true), 1148 DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), 1149 DEFINE_PROP_BOOL("zbkb", RISCVCPU, cfg.ext_zbkb, false), 1150 DEFINE_PROP_BOOL("zbkc", RISCVCPU, cfg.ext_zbkc, false), 1151 DEFINE_PROP_BOOL("zbkx", RISCVCPU, cfg.ext_zbkx, false), 1152 DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), 1153 DEFINE_PROP_BOOL("zk", RISCVCPU, cfg.ext_zk, false), 1154 DEFINE_PROP_BOOL("zkn", RISCVCPU, cfg.ext_zkn, false), 1155 DEFINE_PROP_BOOL("zknd", RISCVCPU, cfg.ext_zknd, false), 1156 DEFINE_PROP_BOOL("zkne", RISCVCPU, cfg.ext_zkne, false), 1157 DEFINE_PROP_BOOL("zknh", RISCVCPU, cfg.ext_zknh, false), 1158 DEFINE_PROP_BOOL("zkr", RISCVCPU, cfg.ext_zkr, false), 1159 DEFINE_PROP_BOOL("zks", RISCVCPU, cfg.ext_zks, false), 1160 DEFINE_PROP_BOOL("zksed", RISCVCPU, cfg.ext_zksed, false), 1161 DEFINE_PROP_BOOL("zksh", RISCVCPU, cfg.ext_zksh, false), 1162 DEFINE_PROP_BOOL("zkt", RISCVCPU, cfg.ext_zkt, false), 1163 1164 DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), 1165 DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), 1166 DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), 1167 DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), 1168 1169 DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false), 1170 1171 /* Vendor-specific custom extensions */ 1172 DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false), 1173 DEFINE_PROP_BOOL("xtheadbb", RISCVCPU, cfg.ext_xtheadbb, false), 1174 DEFINE_PROP_BOOL("xtheadbs", RISCVCPU, cfg.ext_xtheadbs, false), 1175 DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false), 1176 DEFINE_PROP_BOOL("xtheadcondmov", RISCVCPU, cfg.ext_xtheadcondmov, false), 1177 DEFINE_PROP_BOOL("xtheadfmemidx", RISCVCPU, cfg.ext_xtheadfmemidx, false), 1178 DEFINE_PROP_BOOL("xtheadfmv", RISCVCPU, cfg.ext_xtheadfmv, false), 1179 DEFINE_PROP_BOOL("xtheadmac", RISCVCPU, cfg.ext_xtheadmac, false), 1180 DEFINE_PROP_BOOL("xtheadmemidx", RISCVCPU, cfg.ext_xtheadmemidx, false), 1181 DEFINE_PROP_BOOL("xtheadmempair", RISCVCPU, cfg.ext_xtheadmempair, false), 1182 DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false), 1183 DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false), 1184 1185 /* These are experimental so mark with 'x-' */ 1186 DEFINE_PROP_BOOL("x-j", RISCVCPU, cfg.ext_j, false), 1187 /* ePMP 0.9.3 */ 1188 DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), 1189 DEFINE_PROP_BOOL("x-smaia", RISCVCPU, cfg.ext_smaia, false), 1190 DEFINE_PROP_BOOL("x-ssaia", RISCVCPU, cfg.ext_ssaia, false), 1191 1192 DEFINE_PROP_BOOL("x-zvfh", RISCVCPU, cfg.ext_zvfh, false), 1193 DEFINE_PROP_BOOL("x-zvfhmin", RISCVCPU, cfg.ext_zvfhmin, false), 1194 1195 DEFINE_PROP_END_OF_LIST(), 1196 }; 1197 1198 /* 1199 * Register CPU props based on env.misa_ext. If a non-zero 1200 * value was set, register only the required cpu->cfg.ext_* 1201 * properties and leave. env.misa_ext = 0 means that we want 1202 * all the default properties to be registered. 1203 */ 1204 static void register_cpu_props(DeviceState *dev) 1205 { 1206 RISCVCPU *cpu = RISCV_CPU(OBJECT(dev)); 1207 uint32_t misa_ext = cpu->env.misa_ext; 1208 Property *prop; 1209 1210 /* 1211 * If misa_ext is not zero, set cfg properties now to 1212 * allow them to be read during riscv_cpu_realize() 1213 * later on. 1214 */ 1215 if (cpu->env.misa_ext != 0) { 1216 cpu->cfg.ext_i = misa_ext & RVI; 1217 cpu->cfg.ext_e = misa_ext & RVE; 1218 cpu->cfg.ext_m = misa_ext & RVM; 1219 cpu->cfg.ext_a = misa_ext & RVA; 1220 cpu->cfg.ext_f = misa_ext & RVF; 1221 cpu->cfg.ext_d = misa_ext & RVD; 1222 cpu->cfg.ext_v = misa_ext & RVV; 1223 cpu->cfg.ext_c = misa_ext & RVC; 1224 cpu->cfg.ext_s = misa_ext & RVS; 1225 cpu->cfg.ext_u = misa_ext & RVU; 1226 cpu->cfg.ext_h = misa_ext & RVH; 1227 cpu->cfg.ext_j = misa_ext & RVJ; 1228 1229 /* 1230 * We don't want to set the default riscv_cpu_extensions 1231 * in this case. 1232 */ 1233 return; 1234 } 1235 1236 for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { 1237 qdev_property_add_static(dev, prop); 1238 } 1239 } 1240 1241 static Property riscv_cpu_properties[] = { 1242 DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), 1243 1244 DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0), 1245 DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID), 1246 DEFINE_PROP_UINT64("mimpid", RISCVCPU, cfg.mimpid, RISCV_CPU_MIMPID), 1247 1248 #ifndef CONFIG_USER_ONLY 1249 DEFINE_PROP_UINT64("resetvec", RISCVCPU, env.resetvec, DEFAULT_RSTVEC), 1250 #endif 1251 1252 DEFINE_PROP_BOOL("short-isa-string", RISCVCPU, cfg.short_isa_string, false), 1253 1254 DEFINE_PROP_BOOL("rvv_ta_all_1s", RISCVCPU, cfg.rvv_ta_all_1s, false), 1255 DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), 1256 DEFINE_PROP_END_OF_LIST(), 1257 }; 1258 1259 static gchar *riscv_gdb_arch_name(CPUState *cs) 1260 { 1261 RISCVCPU *cpu = RISCV_CPU(cs); 1262 CPURISCVState *env = &cpu->env; 1263 1264 switch (riscv_cpu_mxl(env)) { 1265 case MXL_RV32: 1266 return g_strdup("riscv:rv32"); 1267 case MXL_RV64: 1268 case MXL_RV128: 1269 return g_strdup("riscv:rv64"); 1270 default: 1271 g_assert_not_reached(); 1272 } 1273 } 1274 1275 static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) 1276 { 1277 RISCVCPU *cpu = RISCV_CPU(cs); 1278 1279 if (strcmp(xmlname, "riscv-csr.xml") == 0) { 1280 return cpu->dyn_csr_xml; 1281 } else if (strcmp(xmlname, "riscv-vector.xml") == 0) { 1282 return cpu->dyn_vreg_xml; 1283 } 1284 1285 return NULL; 1286 } 1287 1288 #ifndef CONFIG_USER_ONLY 1289 #include "hw/core/sysemu-cpu-ops.h" 1290 1291 static const struct SysemuCPUOps riscv_sysemu_ops = { 1292 .get_phys_page_debug = riscv_cpu_get_phys_page_debug, 1293 .write_elf64_note = riscv_cpu_write_elf64_note, 1294 .write_elf32_note = riscv_cpu_write_elf32_note, 1295 .legacy_vmsd = &vmstate_riscv_cpu, 1296 }; 1297 #endif 1298 1299 #include "hw/core/tcg-cpu-ops.h" 1300 1301 static const struct TCGCPUOps riscv_tcg_ops = { 1302 .initialize = riscv_translate_init, 1303 .synchronize_from_tb = riscv_cpu_synchronize_from_tb, 1304 .restore_state_to_opc = riscv_restore_state_to_opc, 1305 1306 #ifndef CONFIG_USER_ONLY 1307 .tlb_fill = riscv_cpu_tlb_fill, 1308 .cpu_exec_interrupt = riscv_cpu_exec_interrupt, 1309 .do_interrupt = riscv_cpu_do_interrupt, 1310 .do_transaction_failed = riscv_cpu_do_transaction_failed, 1311 .do_unaligned_access = riscv_cpu_do_unaligned_access, 1312 .debug_excp_handler = riscv_cpu_debug_excp_handler, 1313 .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint, 1314 .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint, 1315 #endif /* !CONFIG_USER_ONLY */ 1316 }; 1317 1318 static void riscv_cpu_class_init(ObjectClass *c, void *data) 1319 { 1320 RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); 1321 CPUClass *cc = CPU_CLASS(c); 1322 DeviceClass *dc = DEVICE_CLASS(c); 1323 ResettableClass *rc = RESETTABLE_CLASS(c); 1324 1325 device_class_set_parent_realize(dc, riscv_cpu_realize, 1326 &mcc->parent_realize); 1327 1328 resettable_class_set_parent_phases(rc, NULL, riscv_cpu_reset_hold, NULL, 1329 &mcc->parent_phases); 1330 1331 cc->class_by_name = riscv_cpu_class_by_name; 1332 cc->has_work = riscv_cpu_has_work; 1333 cc->dump_state = riscv_cpu_dump_state; 1334 cc->set_pc = riscv_cpu_set_pc; 1335 cc->get_pc = riscv_cpu_get_pc; 1336 cc->gdb_read_register = riscv_cpu_gdb_read_register; 1337 cc->gdb_write_register = riscv_cpu_gdb_write_register; 1338 cc->gdb_num_core_regs = 33; 1339 cc->gdb_stop_before_watchpoint = true; 1340 cc->disas_set_info = riscv_cpu_disas_set_info; 1341 #ifndef CONFIG_USER_ONLY 1342 cc->sysemu_ops = &riscv_sysemu_ops; 1343 #endif 1344 cc->gdb_arch_name = riscv_gdb_arch_name; 1345 cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; 1346 cc->tcg_ops = &riscv_tcg_ops; 1347 1348 device_class_set_props(dc, riscv_cpu_properties); 1349 } 1350 1351 static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_str_len) 1352 { 1353 char *old = *isa_str; 1354 char *new = *isa_str; 1355 int i; 1356 1357 for (i = 0; i < ARRAY_SIZE(isa_edata_arr); i++) { 1358 if (isa_edata_arr[i].multi_letter && 1359 isa_ext_is_enabled(cpu, &isa_edata_arr[i])) { 1360 new = g_strconcat(old, "_", isa_edata_arr[i].name, NULL); 1361 g_free(old); 1362 old = new; 1363 } 1364 } 1365 1366 *isa_str = new; 1367 } 1368 1369 char *riscv_isa_string(RISCVCPU *cpu) 1370 { 1371 int i; 1372 const size_t maxlen = sizeof("rv128") + sizeof(riscv_single_letter_exts); 1373 char *isa_str = g_new(char, maxlen); 1374 char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); 1375 for (i = 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { 1376 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { 1377 *p++ = qemu_tolower(riscv_single_letter_exts[i]); 1378 } 1379 } 1380 *p = '\0'; 1381 if (!cpu->cfg.short_isa_string) { 1382 riscv_isa_string_ext(cpu, &isa_str, maxlen); 1383 } 1384 return isa_str; 1385 } 1386 1387 static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) 1388 { 1389 ObjectClass *class_a = (ObjectClass *)a; 1390 ObjectClass *class_b = (ObjectClass *)b; 1391 const char *name_a, *name_b; 1392 1393 name_a = object_class_get_name(class_a); 1394 name_b = object_class_get_name(class_b); 1395 return strcmp(name_a, name_b); 1396 } 1397 1398 static void riscv_cpu_list_entry(gpointer data, gpointer user_data) 1399 { 1400 const char *typename = object_class_get_name(OBJECT_CLASS(data)); 1401 int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); 1402 1403 qemu_printf("%.*s\n", len, typename); 1404 } 1405 1406 void riscv_cpu_list(void) 1407 { 1408 GSList *list; 1409 1410 list = object_class_get_list(TYPE_RISCV_CPU, false); 1411 list = g_slist_sort(list, riscv_cpu_list_compare); 1412 g_slist_foreach(list, riscv_cpu_list_entry, NULL); 1413 g_slist_free(list); 1414 } 1415 1416 #define DEFINE_CPU(type_name, initfn) \ 1417 { \ 1418 .name = type_name, \ 1419 .parent = TYPE_RISCV_CPU, \ 1420 .instance_init = initfn \ 1421 } 1422 1423 static const TypeInfo riscv_cpu_type_infos[] = { 1424 { 1425 .name = TYPE_RISCV_CPU, 1426 .parent = TYPE_CPU, 1427 .instance_size = sizeof(RISCVCPU), 1428 .instance_align = __alignof__(RISCVCPU), 1429 .instance_init = riscv_cpu_init, 1430 .abstract = true, 1431 .class_size = sizeof(RISCVCPUClass), 1432 .class_init = riscv_cpu_class_init, 1433 }, 1434 DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), 1435 #if defined(CONFIG_KVM) 1436 DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), 1437 #endif 1438 #if defined(TARGET_RISCV32) 1439 DEFINE_CPU(TYPE_RISCV_CPU_BASE32, rv32_base_cpu_init), 1440 DEFINE_CPU(TYPE_RISCV_CPU_IBEX, rv32_ibex_cpu_init), 1441 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32_sifive_e_cpu_init), 1442 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32_imafcu_nommu_cpu_init), 1443 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32_sifive_u_cpu_init), 1444 #elif defined(TARGET_RISCV64) 1445 DEFINE_CPU(TYPE_RISCV_CPU_BASE64, rv64_base_cpu_init), 1446 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64_sifive_e_cpu_init), 1447 DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64_sifive_u_cpu_init), 1448 DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), 1449 DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), 1450 DEFINE_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), 1451 #endif 1452 }; 1453 1454 DEFINE_TYPES(riscv_cpu_type_infos) 1455