1 /* 2 * QEMU RISC-V CPU QOM header 3 * 4 * Copyright (c) 2023 Ventana Micro Systems Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms and conditions of the GNU General Public License, 8 * version 2 or later, as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef RISCV_CPU_QOM_H 20 #define RISCV_CPU_QOM_H 21 22 #include "hw/core/cpu.h" 23 #include "qom/object.h" 24 25 #define TYPE_RISCV_CPU "riscv-cpu" 26 27 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 28 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 29 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 30 31 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 32 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 33 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 34 #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 35 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 36 #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 37 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 38 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 39 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 40 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 41 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 42 #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") 43 #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 44 45 #if defined(TARGET_RISCV32) 46 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 47 #elif defined(TARGET_RISCV64) 48 # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 49 #endif 50 51 typedef struct CPUArchState CPURISCVState; 52 53 OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 54 55 /** 56 * RISCVCPUClass: 57 * @parent_realize: The parent class' realize handler. 58 * @parent_phases: The parent class' reset phase handlers. 59 * 60 * A RISCV CPU model. 61 */ 62 struct RISCVCPUClass { 63 /*< private >*/ 64 CPUClass parent_class; 65 /*< public >*/ 66 DeviceRealize parent_realize; 67 ResettablePhases parent_phases; 68 }; 69 70 #endif /* RISCV_CPU_QOM_H */ 71