185840bd2SDaniel Henrique Barboza /* 285840bd2SDaniel Henrique Barboza * QEMU RISC-V CPU QOM header 385840bd2SDaniel Henrique Barboza * 485840bd2SDaniel Henrique Barboza * Copyright (c) 2023 Ventana Micro Systems Inc. 585840bd2SDaniel Henrique Barboza * 685840bd2SDaniel Henrique Barboza * This program is free software; you can redistribute it and/or modify it 785840bd2SDaniel Henrique Barboza * under the terms and conditions of the GNU General Public License, 885840bd2SDaniel Henrique Barboza * version 2 or later, as published by the Free Software Foundation. 985840bd2SDaniel Henrique Barboza * 1085840bd2SDaniel Henrique Barboza * This program is distributed in the hope it will be useful, but WITHOUT 1185840bd2SDaniel Henrique Barboza * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1285840bd2SDaniel Henrique Barboza * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 1385840bd2SDaniel Henrique Barboza * more details. 1485840bd2SDaniel Henrique Barboza * 1585840bd2SDaniel Henrique Barboza * You should have received a copy of the GNU General Public License along with 1685840bd2SDaniel Henrique Barboza * this program. If not, see <http://www.gnu.org/licenses/>. 1785840bd2SDaniel Henrique Barboza */ 1885840bd2SDaniel Henrique Barboza 1985840bd2SDaniel Henrique Barboza #ifndef RISCV_CPU_QOM_H 2085840bd2SDaniel Henrique Barboza #define RISCV_CPU_QOM_H 2185840bd2SDaniel Henrique Barboza 2285840bd2SDaniel Henrique Barboza #include "hw/core/cpu.h" 2385840bd2SDaniel Henrique Barboza #include "qom/object.h" 2485840bd2SDaniel Henrique Barboza 2585840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU "riscv-cpu" 26*9e1a30d3SDaniel Henrique Barboza #define TYPE_RISCV_DYNAMIC_CPU "riscv-dynamic-cpu" 2785840bd2SDaniel Henrique Barboza 2885840bd2SDaniel Henrique Barboza #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU 2985840bd2SDaniel Henrique Barboza #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) 3085840bd2SDaniel Henrique Barboza #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU 3185840bd2SDaniel Henrique Barboza 3285840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") 3385840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32") 3485840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64") 3585840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_BASE128 RISCV_CPU_TYPE_NAME("x-rv128") 3685840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex") 3785840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_SHAKTI_C RISCV_CPU_TYPE_NAME("shakti-c") 3885840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") 3985840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34") 4085840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") 4185840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") 4285840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") 4385840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") 4485840bd2SDaniel Henrique Barboza #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") 4585840bd2SDaniel Henrique Barboza 4685840bd2SDaniel Henrique Barboza #if defined(TARGET_RISCV32) 4785840bd2SDaniel Henrique Barboza # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE32 4885840bd2SDaniel Henrique Barboza #elif defined(TARGET_RISCV64) 4985840bd2SDaniel Henrique Barboza # define TYPE_RISCV_CPU_BASE TYPE_RISCV_CPU_BASE64 5085840bd2SDaniel Henrique Barboza #endif 5185840bd2SDaniel Henrique Barboza 5285840bd2SDaniel Henrique Barboza typedef struct CPUArchState CPURISCVState; 5385840bd2SDaniel Henrique Barboza 5485840bd2SDaniel Henrique Barboza OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) 5585840bd2SDaniel Henrique Barboza 5685840bd2SDaniel Henrique Barboza /** 5785840bd2SDaniel Henrique Barboza * RISCVCPUClass: 5885840bd2SDaniel Henrique Barboza * @parent_realize: The parent class' realize handler. 5985840bd2SDaniel Henrique Barboza * @parent_phases: The parent class' reset phase handlers. 6085840bd2SDaniel Henrique Barboza * 6185840bd2SDaniel Henrique Barboza * A RISCV CPU model. 6285840bd2SDaniel Henrique Barboza */ 6385840bd2SDaniel Henrique Barboza struct RISCVCPUClass { 6485840bd2SDaniel Henrique Barboza /*< private >*/ 6585840bd2SDaniel Henrique Barboza CPUClass parent_class; 6685840bd2SDaniel Henrique Barboza /*< public >*/ 6785840bd2SDaniel Henrique Barboza DeviceRealize parent_realize; 6885840bd2SDaniel Henrique Barboza ResettablePhases parent_phases; 6985840bd2SDaniel Henrique Barboza }; 7085840bd2SDaniel Henrique Barboza #endif /* RISCV_CPU_QOM_H */ 71